Freescale Semiconductor, Inc. MOTOROLA Document order number: MC33883/D Rev 6.0, 01/2004 SEMICONDUCTOR TECHNICAL DATA 33883 H-Bridge Gate Driver IC Freescale Semiconductor, Inc... The 33883 is an H-bridge gate driver (also known as a full-bridge predriver) IC with integrated charge pump and independent high- and low-side gate driver channels. The gate driver channels are independently controlled by four separate input terminals, thus allowing the device to be optionally configured as two independent high-side gate drivers and two independent low-side gate drivers. The low-side channels are referenced to ground. The high-side channels are floating. H-BRIDGE GATE DRIVER IC The gate driver outputs can source and sink up to 1.0 A peak current pulses, permitting large gate-charge MOSFETs to be driven and/or high Pulse Width Modulation (PWM) frequencies to be utilized. A linear regulator is incorporated, providing a 15 V typical gate supply to the low-side gate drivers. Features • VCC Operating Voltage Range from 5.5 V up to 55 V • VCC2 Operating Voltage Range from 5.5 V up to 28 V • • • • • • • DW SUFFIX CASE 751D-06 20-TERMINAL SOICW CMOS/LSTTL Compatible I/O 1.0 A Peak Gate Driver Current Built-In High-Side Charge Pump Undervoltage Lockout (UVLO) Overvoltage Lockout (OVLO) Global Enable with <10 µA Sleep Mode Supports PWM up to 100 kHz ORDERING INFORMATION Device Temperature Range (TA) Package MC33883DW/R2 -40°C to 125°C 20 SOICW 33883 Simplified SimplifiedApplication Application Diagram Diagram VBAT VBOOST 33883 VCC CP_OUT VCC2 G_EN LR_OUT C1 C2 MCU GATE_HS1 SRC_HS1 GATE_LS1 GATE_HS2 IN_HS1 IN_LS1 IN_HS2 IN_LS2 © Motorola, Inc. 2004 SRC_HS2 GATE_LS2 GND For More Information On This Product, Go to: www.freescale.com DC Motor Freescale Semiconductor, Inc. CCP C2 C1 VCC, VCC2 Undervoltage/ Overvoltage Detection VCC2 VCC VCC2 VCC VDD C1 Charge Pump EN C2 VPOS GND G_EN GND GND_A GND2 Linear Reg +14.5 V TSD1 VDD /VPOS Level Shift Pulse Generator BRG_EN TSD1 LR_OUT HIGH- AND LOW-SIDE CONTROL WITH CHARGE PUMP HIGH-SIDE CHANNEL IN_LS1 CLR_OUT LR_OUT VCC Control and Logic Control and Logic TSD1 Thermal Shutdown VDD /VCC Level Shift Pulse Generator IN Output VDD /VPOS Level Shift Pulse Generator HIGH-SIDE CHANNEL BRG_EN IN_LS2 TSD2 Control and Logic GATE_HS1 SRC_HS1 GATE_LS1 GND1 CP_OUT IN Output OUT Driver TSD2 Thermal Shutdown GATE_HS2 SRC_HS2 LR_OUT VDD /VCC Level Shift Pulse Generator LOW-SIDE CHANNEL GND1 GND2 OUT Driver VCC Control and Logic OUT Driver LR_OUT BRG_EN TSD2 CP_OUT IN Output LOW-SIDE CHANNEL IN_HS2 5.5 V – 55 V CP_OUT +5.0 V BRG_EN IN_HS1 CCP_OUT VDD EN 5.5 V– 28 V VCC CP_OUT GND2 VCC2 VCC2 Freescale Semiconductor, Inc... VCC IN Output OUT Driver GATE_LS2 GND2 GND_A Figure 1. 33883 Simplified Internal Block Diagram 33883 2 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. VCC 1 20 G_EN C2 2 19 CP_OUT SRC_HS1 3 18 4 17 GATE_HS1 IN_HS1 IN_LS1 GATE_LS1 5 16 6 15 SRC_HS2 GATE_HS2 IN_HS2 IN_LS2 GATE_LS2 7 14 8 13 GND1 LR_OUT 9 12 10 11 GND2 C1 GND_A VCC2 Freescale Semiconductor, Inc... TERMINAL FUNCTION DESCRIPTION Terminal Terminal Name Formal Name 1 VCC Supply Voltage 1 2 C2 Charge Pump Capacitor 3 CP_OUT Charge Pump Out 4 SRC_HS1 Source 1 Output High Side 5 GATE_HS1 Gate 1 Output High Side 6 IN_HS1 Input High Side 1 Logic input control of high-side 1 gate (i.e., IN_HS1 logic HIGH = GATE_HS1 HIGH). 7 IN_LS1 Input Low Side 1 Logic input control of low-side 1 gate (i.e., IN_LS1 logic HIGH = GATE_LS1 HIGH). 8 GATE_LS1 Gate 1 Output Low Side 9 GND1 Ground 1 10 LR_OUT Linear Regulator Output 11 VCC2 Supply Voltage 2 Device power supply 2. 12 GND_A Analog Ground Device analog ground. 13 C1 Charge Pump Capacitor 14 GND2 Ground 2 15 GATE_LS2 Gate 2 Output Low Side 16 IN_LS2 Input Low Side 2 Logic input control of low-side 2 gate (i.e., IN_LS2 logic HIGH = GATE_LS2 HIGH). 17 IN_HS2 Input High Side 2 Logic input control of high-side 2 gate (i.e., IN_HS2 logic HIGH = GATE_HS2 HIGH). 18 GATE_HS2 Gate 2 Output High Side 19 SRC_HS2 Source 2 Output High Side 20 G_EN Global Enable MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Definition Device power supply 1. External capacitor for internal charge pump. External reservoir capacitor for internal charge pump. Source of high-side 1 MOSFET Gate of high-side 1 MOSFET. Gate of low-side 1 MOSFET. Device ground 1. Output of internal linear regulator. External capacitor for internal charge pump. Device ground 2. Gate of low-side 2 MOSFET. Gate of high-side 2 MOSFET. Source of high-side 2 MOSFET. Logic input Enable control of device (i.e., G_EN logic HIGH = Full Operation, G_EN logic LOW = Sleep Mode). For More Information On This Product, Go to: www.freescale.com 33883 3 Freescale Semiconductor, Inc. MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted. Rating Symbol Value Unit Supply Voltage 1 VCC -0.3 to 65 V Supply Voltage 2 (Note 1) VCC2 -0.3 to 35 V Linear Regulator Output Voltage VLR_OUT -0.3 to 18 V High-Side Floating Supply Absolute Voltage VCP_OUT -0.3 to 65 V High-Side Floating Source Voltage VSRC_HS -1.0 to 65 V IS 250 mA VGATE_HS -0.3 to 65 V High-Side Gate Source Voltage VGATE_HS - VSRC_HS -0.3 to 20 V High-Side Floating Supply Gate Voltage VCP_OUT - VGATE_HS -0.3 to 65 V VGATE_LS -0.3 to 17 V VG_EN -0.3 to 35 V Logic Input Voltage VIN -0.3 to 10 V Charge Pump Capacitor Voltage VC1 -0.3 to VLR_OUT V Charge Pump Capacitor Voltage VC2 -0.3 to 65 V High-Side Source Current from CP_OUT in Switch ON State Freescale Semiconductor, Inc... High-Side Gate Voltage Low-Side Gate Voltage Wake-Up Voltage V ESD Voltage Human Body Model on All Pins (VCC and VCC2 as Two Power Supplies) (Note 2) VESD1 ±1500 Machine Model (Note 3) VESD2 ±130 PD 1.25 W RθJA 100 °C/W Power Dissipation and Thermal Characteristics Maximum Power Dissipation @ 25°C Thermal Resistance (Junction to Ambient) Operating Junction Temperature Storage Temperature Terminal Soldering Temperature (Note 4) TJ -40 to 150 °C TSTG -65 to 150 °C TSOLDER 240 °C Notes 1. VCC2 can sustain load dump pulse of 40 V, 400 ms, 2.0 Ω. 2. ESD1 testing is performed in accordance with the Human Body Model (CZAP =100 pF, RZAP =1500 Ω). 3. ESD2 testing is performed in accordance with the Machine Model (CZAP =200 pF, RZAP =0 Ω). 4. Terminal soldering temperature limit is for 10 second maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 33883 4 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions VCC = 12 V, VCC2 = 12 V, CCP = 33 nF, G_EN = 4.5 V unless otherwise noted. Typical values for TA = 25°C and min/max values for TA = -40°C to 125°C unless otherwise noted. Characteristic Symbol Min Typ Max Unit Supply Voltage 1 for Output High-Side Driver and Charge Pump VCC 5.5 – 55 V Supply Voltage 2 for Linear Regulation VCC2 5.5 – 28 V VCP_OUT VCC+4 – VCC +11 but < 65 V Logic 1 Input Voltage (IN_LS and IN_HS) VIH 2.0 – 10 V Logic 0 Input Voltage (IN_LS and IN_HS) VIL – – 0.8 V Logic 1 Input Current IIN+ 200 – 1000 4.5 5.0 VCC2 – 200 500 – – 1.5 12.5 – 16.5 VCC2 -1.5 – – 4.0 – – VCC = 12 V, ILOAD = 0 mA, CCP_OUT = 1.0 µF 7.5 – – VCC = 12 V, ILOAD = 7.0 mA, CCP_OUT = 1.0 µF 7.0 – – VCC2 = VCC = 5.5 V, ILOAD = 0 mA, CCP_OUT = 1.0 µF 2.3 – – VCC2 = VCC = 5.5 V, ILOAD = 7.0 mA, CCP_OUT = 1.0 µF 1.8 – – VCC = 55 V, ILOAD = 0 mA, CCP_OUT = 1.0 µF 7.5 – – VCC = 55 V, ILOAD = 7.0 mA, CCP_OUT = 1.0 µF 7.0 – – -2.0 – 2.0 -1.5 – – OPERATING CONDITIONS High-Side Floating Supply Absolute Voltage Freescale Semiconductor, Inc... LOGIC µA VIN = 5.0 V Wake-Up Input Voltage (G_EN) VG_EN Wake-Up Input Current (G_EN) IG_EN µA VG_EN = 14 V IG_EN2 Wake-Up Input Current (G_EN) V mA VG_EN = 28 V LINEAR REGULATOR V VLR_OUT Linear Regulator VLR_OUT @ VCC2 from 15 V to 28 V, ILOAD from 0 mA to 20 mA VLR_OUT @ ILOAD = 20 mA VLR_OUT @ ILOAD = 20 mA, VCC2 = 5.5 V, VCC = 5.5 V CHARGE PUMP Charge Pump Output Voltage, Reference to VCC Peak Current Through Pin C1 Under Rapidly Changing VCC Voltages (see Figure 11, page 14) Minimum Peak Voltage at Pin C1 Under Rapidly Changing VCC Voltages (see Figure 11, page 14) MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA VCP_OUT IC1 VC1min For More Information On This Product, Go to: www.freescale.com V A V 33883 5 Freescale Semiconductor, Inc. STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions VCC = 12 V, VCC2 = 12 V, CCP = 33 nF, G_EN = 4.5 V unless otherwise noted. Typical values for TA = 25°C and min/max values for TA = -40°C to 125°C unless otherwise noted. Characteristic Symbol Min Typ Max – – 10 – – 10 – 2.2 – – 0.7 – – – 5.0 – – 5.0 – – 5.0 – – 12 – – 9.0 Unit SUPPLY VOLTAGE VG_EN = 0 V and VCC = 55 V VG_EN = 0 V and VCC = 12 V mA IVCCop Operating VCC Supply Current (Note 5) VCC = 55 V and VCC2 = 28 V VCC = 12 V and VCC2 = 12 V Freescale Semiconductor, Inc... µA IVCCsleep Quiescent VCC Supply Current Additional Operating VCC Supply Current for Each Logic Input Terminal Active IVCClog VCC = 55 V and VCC2 = 28 V (Note 6) mA µA IVCC2sleep Quiescent VCC2 Supply Current VG_EN = 0 V and VCC = 12 V VG_EN = 0 V and VCC = 28 V mA IVCC2op Operating VCC2 Supply Current (Note 5) VCC = 55 V and VCC2 = 28 V VCC = 12 V and VCC2 = 12 V Additional Operating VCC2 Supply Current for Each Logic Input Terminal IVCC2log mA Active VCC = 55 V and VCC2 = 28 V (Note 6) – – 5.0 Undervoltage Shutdown VCC UV 4.0 5.0 5.5 V Undervoltage Shutdown VCC2 (Note 7) UV2 4.0 5.0 5.5 V Overvoltage Shutdown VCC OV 57 61 65 V Overvoltage Shutdown VCC2 OV2 29.5 31 35 V – – 22 – – 22 – 100 200 – – 18 OUTPUT Ω RDS Output Sink Resistance (Turned Off) Idischarge LSS = 50 mA , VSRC_HS = 0 V (Note 8) Ω RDS Output Source Resistance (Turned On) Icharge HSS = 50 mA, VCP_OUT = 20 V (Note 8) Charge Current of the External High-Side MOSFET Through GATE_HSn Terminal (Note 8) Icharge HSS mA Vmax Maximum Voltage (VGATE_HS - VSRC_HS) INH = Logic 1, ISmax = 5.0 mA V Notes 5. Logic input terminal inactive (high impedance). 6. 7. 8. 33883 6 High-frequency PWM-ing (» 20 kHz) of the logic inputs will result in greater power dissipation within the device. Care must be taken to remain within the package power handling rating. The device may exhibit predictable behavior between 4.0 V and 5.5 V. See Figure 3, page 10, for a description of charge current. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions VCC = 12 V, VCC2 = 12 V, CCP = 33 nF, G_EN = 4.5 V unless otherwise noted. Typical values for TA = 25°C and min/max values for TA = -40°C to 125°C unless otherwise noted. Characteristic Symbol Min Typ Max – 200 300 – 80 180 Unit TIMING CHARACTERISTICS ns tpd Propagation Delay High Side and Low Side CLOAD = 5.0 nF, Between 50% Input to 50% Output (Note 9) (see Figure 2) tr Turn-On Rise Time ns CLOAD = 5.0 nF, 10% to 90% (Note 9), (Note 10) (see Figure 2) tf Turn-Off Fall Time ns – Freescale Semiconductor, Inc... CLOAD = 5.0 nF, 10% to 90% (Note 9), (Note 10) (see Figure 2) 80 180 Notes 9. CLOAD corresponds to a capacitor between GATE_HS and SRC_HS for the high side and between GATE_LS and ground for low side. 10. Rise time is given by time needed to change the gate from 1.0 V to 10 V (vice versa for fall time). 50% 50% IN_HS or IN_LS GATE_HS or GATE_LS t pd t pd 50% 50% tr tf 10% 90% 90% 10% Figure 2. Timing Characteristics MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33883 7 Freescale Semiconductor, Inc. SYSTEM/APPLICATION INFORMATION INTRODUCTION The 33883 is an H-bridge gate driver (or full-bridge predriver) with integrated charge pump and independent high- and lowside driver channels. It has the capability to drive large gate- charge MOSFETs and supports high PWM frequency. In sleep mode its supply current is very low. FUNCTIONAL TERMINAL DESCRIPTION Freescale Semiconductor, Inc... Supply Voltage Terminals (VCC and VCC2) The VCC and VCC2 terminals are the power supply inputs to the device. VCC is used for the output high-side drivers and the charge pump. VCC2 is used for the linear regulation. They can be connected together or independent with different voltage values. The device can operate with VCC up to 55 V and VCC2 up to 28 V. The VCC and VCC2 terminals have undervoltage (UV) and overvoltage (OV) shutdown. If one of the supply voltage drops below the undervoltage threshold or rises above the overvoltage threshold, the gate outputs are switched LOW in order to switch off the external MOSFETs. When the supply returns to a level that is above the UV threshold or below the OV threshold, the device resumes normal operation according to the established condition of the input terminals. Input High- and Low-Side Terminals (IN_HSn and IN_LSn) The IN_HSn and IN_LSn terminals are input control terminals used to control the gate outputs. These terminals are 5.0 V CMOS-compatible inputs with hysteresis. IN_HSn and IN_LSn independently control GATE_HSn and GATE_LSn, respectively. During wake-up, the logic is supplied from the G_EN terminal. There is no internal circuit to prevent the external highside and low-side MOSFETs from conducting at the same time. Source Output High-Side Terminals (SRC_HSn) The SRC_HSn terminals are the sources of the external high-side MOSFETs. The external high-side MOSFETs are controlled using the IN_HSn inputs. 33883 8 Gate High- and Low-Side Terminals (GATE_HSn and GATE_LSn) The GATE_HSn and GATE_LSn terminals are the gates of the external high- and low-side MOSFETs. The external highand low-side MOSFETs are controlled using the IN_HSn and IN_LSn inputs. G_EN Terminal The G_EN terminal is used to place the device in a sleep mode. When the G_EN terminal voltage is a logic LOW state, the device is in sleep mode. The device is enabled and fully operational when the G_EN terminal voltage is logic HIGH, typically 5.0 V. Charge Pump Out Terminal (CP_OUT) The CP_OUT terminal is used to connect an external reservoir capacitor for the charge pump. Charge Pump Capacitor Terminals (C1 and C2) The C1 and C2 terminals are used to connect an external capacitor for the charge pump. Linear Regulator Output Terminal (LR_OUT) The LR_OUT terminal is the output of the internal regulator. It is used to connect an external capacitor. Ground Terminals (GNDn and GND_A) These terminals are the ground terminals of the device. They should be connected together with a very low impedance connection. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Table 1. Functional Truth Table Conditions G_EN IN_HSn IN_LSn Gate_HSn Gate_LSn Comments Sleep 0 x x 0 0 Device is in Sleep mode. The gates are at low state. Normal 1 1 1 1 1 Normal mode. The gates are controlled independently. Normal 1 0 0 0 0 Normal mode. The gates are controlled independently. Undervoltage 1 x x 0 0 The device is currently in fault mode. The gates are at low state. Once the fault is removed, the 33883 recovers its normal mode. Overvoltage 1 x x 0 0 The device is currently in fault mode. The gates are at low state. Once the fault is removed, the 33883 recovers its normal mode. Overtemperature on High-Side Gate Driver 1 1 x 0 x The device is currently in fault mode. The high-side gate is at low state. Once the fault is removed, the 33883 recovers its normal mode. Overtemperature on Low-Side Gate Driver 1 x 1 x 0 The device is currently in fault mode. The low-side gate is at low state. Once the fault is removed, the 33883 recovers its normal mode. x = Don’t care. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33883 9 Freescale Semiconductor, Inc. DEVICE DESCRIPTION Driver Characteristics Figure 3 represents the external circuit of the high-side gate driver. In the schematic, HSS represents the switch that is used to charge the external high-side MOSFET through the GATE_HS terminal. LSS represents the switch that is used to discharge the external high-side MOSFET through the GATE_HS terminal. The same schematic can be applied to the external low-side MOSFET driver simply by replacing terminal CP_OUT with terminal LR_OUT, terminal GATE_HS with terminal GATE_LS, and terminal SRC_HS with GND. The different voltages and current of the high-side gate driver are illustrated in Figure 4. The output driver sources a peak current of up to 1.0 A for 200 ns to turn on the gate. After 200 ns, 100 mA is continuously provided to maintain the gate charged. The output driver sinks a high current to turn off the gate. This current can be up to 1.0 A peak for a 100 nF load. IN_HS1 0 HSSpulse_IN Freescale Semiconductor, Inc... CP_OUT 0 HSS HSS DC_IN IGATE_HS HSSDC_IN Icharge HSS GATE_HS1 Idischarge LSS IN_HS1 HSSpulse_IN LSS LSS_IN 180 kΩ Icharge HSS 18V LSS_IN 0 1.0 A Peak 100 mA Typical SRC_HS1 0 Idischarge LSS Figure 3. High-Side Gate Driver Functional Schematic 1.0 A Peak 0 IGATE_HS 1.0 A Peak 100 mA Typical 0 -1.0 A Peak Note GATE_HS is loaded with a 100 nF capacitor in the chronograms. A smaller load will give lower peak and DC charge or discharge currents. Figure 4. High-Side Gate Driver Chronograms 33883 10 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. APPLICATION REQUIREMENTS Turn-On Turn-Off For turn-on, the current required to charge the gate source capacitor Ciss in the specified time can be calculated as follows: The peak current for turn-off can be obtained in the same way as for turn-on, with the exception that peak current for fall time, tf, is substituted for tr: I P = Qg /t r = 80 nC/80 ns ≈ 1.0 A Freescale Semiconductor, Inc... Where Q g is power MOSFET gate charge and t r is peak current for rise time. Flyback spike charges lowside gate via Crss charge current Irss up to 2.0 A. Causes increased uncontrolled turn-on of low-side MOSFET. Crss Flyback spike pulls down high-side source VGS. Delays turn-off of highside MOSFET. VBAT Crss VBAT I P = Qg /t f = 80 nC/80 ns ≈ 1.0 A In addition to the dynamic current required to turn off or on the MOSFET, various application-related switching scenarios must be considered. These scenarios are presented in Figure 5. In order to withstand high dV/dt spikes, a low resistive path between gate and source is implemented during the OFFstate. Flyback spike charges lowside gate via Crss charge current Irss up to 2.0 A. Delays turn-off of low-side MOSFET. Crss VBAT OFF OFF Ciss GATE_HS ILOAD L1 Ciss GATE_HS ILOAD L1 Ciss Crss Crss Crss GATE_HS Irss Flyback spike pulls down high-side source VGS. Causes increased uncontrolled turn-on of high-side MOSFET. Crss VBAT VGATE -VDRN GATE_HS ILOAD L1 Ciss L1 ILOAD Crss VGATE GATE_LS OFF Ciss Driver Requirement: Low Resistive GateSource Path During OFF-State GATE_LS OFF Ciss Driver Requirement: Low Resistive GateSource Path During OFF-State. High Peak Sink Current Capability GATE_LS Ciss Driver Requirement: High Peak Sink Current Capability GATE_LS Ciss Driver Requirement: Low Resistive GateSource Path During OFF-State Figure 5. OFF-State Driver Requirement MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33883 11 Freescale Semiconductor, Inc. Low-Drop Linear Regulator External Capacitors Choice The low-drop linear regulator is supplied by VCC2. If VCC2 exceeds 15.0 V, the output is limited to 14.5 V (typical). External capacitors on the charge pump and on the linear regulator are necessary to supply high peak current absorbed during switching. The low-drop linear regulator provides the 5.0 V for the logic section of the driver, the Vgs_ls buffered at LR_OUT, and the +14.5 V for the charge pump, which generates the CP_OUT The low-drop linear regulator provides 4.0 mA average current per driver stage. In case of the full bridge, that means approximately 16 mA — 8.0 mA for the high side and 8.0 mA for the low side. Freescale Semiconductor, Inc... Note: The average current required to switch a gate with a frequency of 100 kHz is: Figure 7 represents a simplified circuitry of the high-side gate driver. Transistors Tosc1 and Tosc2 are the oscillator-switching MOSFETs. When Tosc1 is on, the oscillator is at low level. When Tosc2 is on, the oscillator is at high level. The capacitor CCP_OUT provides peak current to the high-side MOSFET through HSS during turn-on (3). VLR_OUT VLR-OUT CP_out CP_OUT Tosc2 Tosc2 ICP = Qg * f PWM = 80 nC * 100 kHz = 8.0 mA Ccp CCP In a full-bridge application only one high side and one low side switches on or off at the same time. C1 C1 D1 D1 C2 C2 D2 D2 Tosc1 Tosc1 Charge Pump The charge pump generates the high-side driver supply voltage (CP_OUT), buffered at CCP_OUT. Figure 6 shows the charge pump basic circuit without load. (2) V LR_OUT VLR_OUT Osc. OSC. C Ccp_out CP_OUT D1 D1 VCP_OUT CP_OUT VVcc CC (3) T1 HSS GATE_HS GATE_HS Ccp CCP LSS A C2 C1 CCcp_out CP_OUT Rg Rg T2 HS MOSFET High-Side MOSFET SRC_HS SRC_HS D2 D2 (1) LS VVbat CC Low-Side MOSFET MOSFET Figure 6. Charge Pump Basic Circuit When the oscillator is in low state [(1) in Figure 6], CCP is charged through D2 until its voltage reaches VCC - VD2. When the oscillator is in high state (2), CCP is discharged though D1 in CCP_OUT, and final voltage of the charge pump, VCP_OUT, is Vcc + VLR_OUT - 2VD. The frequency of the 33883 oscillator is about 330 kHz. 33883 12 Terminals pins Figure 7. High-Side Gate Driver MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. CCP CCP_OUT CCP choice depends on power MOSFET characteristics and the working switching frequency. Figure 8 contains two diagrams that depict the influence of CCP value on VCP_OUT average voltage level. The diagrams represent two different frequencies for two power MOSFETs, MTP60N06HD and MPT36N06V. Figure 9 depicts the simplified CCP_OUT current and voltage waveforms. fPWM is the working switching frequency. VCP_OUT V Cp_out rage V Cp_out Average VCP_OUT 21 VVcp_out (V) CP_OUT (v) High Side High Side Turn On turn on in low Low in State state ∆V ∆ VCcp CP_OUT _ out 20 kHz 20KhZ 100 100 kHz KhZ 20.5 ICP_OUT I Cp_out 20 ffPWM PWM f=330kHz f = 330 kHz 19.5 19 18.5 18 5 25 45 65 Peak Peak Current Current 85 Figure 9. Simplified CCP_OUT Current and Voltage Waveforms C (nF) Ccp CP(nF) MTP60N06HD (Qg=50nC) MTP60N06HD (Qg = 50 nC) MTP60N06HD (Qg = 50 nC) 21.5 20 kHz As shown above, at high-side MOSFET turn-on VCP_OUT voltage decreases. This decrease can be calculated according to the CCP_OUT value as follows: 100 kHz 21 Vcp_out (V)(V) VCP_OUT Freescale Semiconductor, Inc... Oscillator Oscillator in high High in Oscillator State Oscillator state ∆VCP_OUT = 20.5 CCP_OUT Where Qg is power MOSFET gate charge. 20 19.5 CLR_OUT CLR_OUT provides peak current needed by the low-side MOSFET turn-on. VLR_OUT decrease is as follows: 19 18.5 5 Qg 25 45 65 85 CCcp (nF) CP (nF) ∆VLR_OUT = Qg CLR_OUT MTP36N06V (Qg = 40 nC) Figure 8. VCP_OUT Versus CCP The smaller the CCP value is, the smaller the VCP_OUT value is. Moreover, for the same CCP value, when the switching frequency increases, the average VCP_OUT level decreases. For most of the applications, a typical value of 33 nF is recommended. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Typical Values of Capacitors In most working cases the following typical values are recommended for a well-performing charge pump: CCP = 33 nF, CCP_OUT = 470 nF, and CLR_OUT = 470 nF These values give a typical 100 mV voltage ripple on VCP_OUT and VLR_OUT with Qg = 50 nC. For More Information On This Product, Go to: www.freescale.com 33883 13 Freescale Semiconductor, Inc. Protection Load Dump and Reverse Battery Gate Protection The low-side driver is supplied from the built-in low-drop regulator. The high-side driver is supplied from the internal charge pump buffered at CP_OUT. Freescale Semiconductor, Inc... The low-side gate is protected by the internal linear regulator, which ensures that VGATE_LS does not exceed the maximum VGS. Especially when working with the charge pump, the voltage at CP_OUT can be up to 65 V. The high-side gate is clamped internally in order to avoid a VGS exceeding 18 V. Gate protection does not include a flyback voltage clamp that protects the driver and the external MOSFET from a flyback voltage that can occur when driving inductive load. This flyback voltage can reach high negative voltage values and needs to be clamped externally, as shown in Figure 10. LR_OUT IN Output Driver M1 GATE_HS VGS < 14 V L1 Inductive Flyback Voltage Clamp M2 OUT dV/dt at VCC For positive transitions at terminal C2, the absolute value of the minimum peak current, I C1min, is specified at 2.0 A for a t C1min duration of 600 ns. Under All Conditions Dcl Output Driver There is temperature shutdown protection per each halfbridge. Temperature shutdown protects the circuitry against temperature damage by switching off the output drivers. Its typical value is 175°C with an hysteresis of 15°C. In some applications a large dV/dt at terminal C2 owing to sudden changes at VCC can cause large peak currents flowing through terminal C1, as shown in Figure 11. VCC SRC_HS IN Temperature Protection VCC voltage must be higher than (SRC_HS voltage minus a diode drop voltage) to avoid perturbation of the high-side driver. CP_OUT OUT VCC and VCC2 can sustain load a dump pulse of 40 V and double battery of 24 V. Protection against reverse polarity is ensured by the external power MOSFET with the free-wheeling diodes forming a conducting pass from ground to VCC. Additional protection is not provided within the circuit. To protect the circuit an external diode can be put on the battery line. It is not recommended putting the diode on the ground line. For negative transitions at terminal C2, the maximum peak current, IC1max, is specified at 2.0 A for a t C1max duration of 600 ns. Current sourced by terminal C1 during a large dV/dt will result in a negative voltage at terminal C1 (Figure 11). The minimum peak voltage VC1min is specified at -1.5 V for a duration of t C1max = 600 ns. A series resistor with the charge pump capacitor (Ccp) capacitor can be added in order to limit the surge current. GATE_LS Figure 10. Gate Protection and Flyback Voltage Clamp VCC IC1max t C1min I (C1+C2) 0A t C1max I C1min V(LR_OUT) V(C1) 0V VC1min Figure 11. Limits of C1 Current and Voltage with Large Values of dV/dt 33883 14 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. dV/dt at VCC2 In the case of rapidly changing VCC voltages, the large dV/dt may result in perturbations of the high-side driver, thereby forcing the driver into an OFF state. The addition of capacitors C3 and C4, as shown in Figure 12, reduces the dV/dt of the source line, consequently reducing driver perturbation. Typical values for R3/R4 and C3/C4 are 10 Ω and 10 nF, respectively. When the external high-side MOSFET is on, in case of rapid negative change of VCC2 the voltage (VGATE_HS - VSRC_HS) can be higher than the specified 18 V. In this case a resistance in the SRC line is necessary to limit the current to 5.0 mA max. It will protect the internal zener placed between GATE_HS and SRC terminals. VBAT VBOOST VCC Freescale Semiconductor, Inc... VCC2 G_EN CCP 33 nF C1 C2 MCU IN_HS1 IN_LS1 IN_HS2 IN_LS2 33883 VCC VCC2 G_EN C1 CP_OUT LR_OUT CCP_OUT 470 nF CLR_OUT 470 nF SRC_HS1 IN_HS1 GATE_LS1 50 Ω R4 R3 C3 10 nF M3 R2 50 Ω GATE_HS1 C2 M1 R1 C4 10 nF 10 Ω 10 Ω DC Motor GATE_HS2 IN_LS1 SRC_HS2 IN_HS2 GATE_LS2 IN_LS2 M2 50 Ω M4 GND 50 Ω Figure 12. Application Schematic with External Protection Circuit MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33883 15 Freescale Semiconductor, Inc. PACKAGE DIMENSIONS DW SUFFIX 20-TERMINAL SOICW PLASTIC PACKAGE CASE 751D-06 ISSUE H 0.25 10X PIN'S NUMBER B M A 10.55 10.05 1 2.65 2.35 0.25 0.10 20X 20 6 M T A B 18X PIN 1 INDEX Freescale Semiconductor, Inc... 0.49 0.35 0.25 1.27 4 A NOTES: 1. 2. 12.95 12.65 3. A 4. 11 10 T 7.6 7.4 B SEATING PLANE 20X 0.1 T 5. 5 0.75 0.25 X45 6. 0.32 0.23 1.0 0.4 SECTION A-A 33883 16 DIMENSIONS ARE IN MILLIMETERS. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. DATUMS A AND B TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15mm PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. THIS DIMENSION DOES NOT INCLUDE INTER-LEAD FLASH OR PROTRUSIONS. INTER-LEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25mm PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.62mm. 7 0 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... NOTES MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33883 17 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... NOTES 33883 18 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... NOTES MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33883 19 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. 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