July 2000 PRELIMINARY ML4832* Electronic Dimming Ballast Controller GENERAL DESCRIPTION FEATURES The ML4832 is a complete solution for a dimmable/nondimmable, high power factor, high efficiency electronic ballast. The BiCMOS ML4832 contains controllers for “boost” type power factor correction as well as for a dimming ballast. ■ Complete power factor correction and dimming ballast control in one IC ■ Low distortion, high efficiency continuous boost, average current sensing PFC section ■ Programmable start scenario for rapid or instant start lamps ■ Lamp current feedback for dimming control ■ Variable frequency dimming and starting ■ Programmable restart for lamp out condition to reduce ballast heating ■ Over-temperature shutdown replaces external heat sensor for safety ■ PFC overvoltage comparator eliminates output “runaway” due to load removal ■ Large oscillator amplitude and gain modulator improves noise immunity ■ Low start-up current <0.5mA The power factor circuit uses the average current sensing method with a gain modulator and overvoltage protection. This system produces a power factor of better than 0.99 with low input current THD at > 95% efficiency. Special care has been taken in the design of the ML4832 to increase system noise immunity by using a high amplitude oscillator, and a current-fed multiplier. An overvoltage protection comparator inhibits the PFC section in the event of a lamp out or lamp failure condition. The ballast section provides for programmable starting scenarios with programmable preheat and lamp out-ofsocket interrupt times. The IC controls lamp output through frequency modulation using lamp current feedback. (* Indicates part is End Of Life as of July 1, 2000) BLOCK DIAGRAM INTERRUPT 7 8 RSET RT/CT LAMP FB VARIABLE FREQUENCY OSCILLATOR LFB OUT 9 5 6 OUTPUT DRIVERS 10 RX/CX PRE-HEAT AND INTERRUPT TIMERS OUT A CONTROL & GATING LOGIC OUT B PFC OUT 2 4 3 1 18 IA OUT 14 13 15 IA+ ISINE EA OUT EA–/OVP POWER FACTOR CONTROLLER PGND VCC UNDER-VOLTAGE AND THERMAL SHUTDOWN VREF GND 12 16 17 11 1 ML4832 PIN CONFIGURATION ML4832 18-Pin SOIC (S18) ML4832 18-Pin DIP (P18) EA OUT IA OUT ISINE IA+ LAMP FB LFB OUT RSET RT/CT INTERRUPT 1 18 2 17 3 16 4 15 5 14 6 13 7 12 8 11 9 10 EA–/OVP EA OUT 1 18 EA–/OVP VREF IA OUT 2 17 VREF VCC ISINE 3 16 VCC IA+ 4 15 PFC OUT OUT A LAMP FB 5 14 OUT A OUT B LFB OUT 6 13 OUT B P GND RSET 7 12 P GND RT/CT 8 11 GND INTERRUPT 9 10 RX/CX PFC OUT GND RX/CX TOP VIEW TOP VIEW PIN DESCRIPTION PIN# NAME FUNCTION PIN# NAME FUNCTION 9 INTERRUPT Input used for lamp-out detection and restart. A voltage greater than 7.5 volts resets the chip and causes a restart after a programmable interval. 10 RX/CX Sets the timing for the preheat, dimming lockout, and interrupt 1 EA OUT PFC error amplifier output and compensation node 2 IA OUT Output and compensation node of the PFC average current transconductance amplifier 3 ISINE PFC gain modulator input 4 IA+ Non-inverting input of the PFC average current transconductance amplifier and peak current sense point of the PFC cycle by cycle current limit comparator 11 GND Ground 12 P GND Power ground for the IC 13 OUT B Ballast MOSFET drive output Inverting input of an error amplifier used to sense (and regulate) lamp arc current. Also the input node for dimming control. 14 OUT A Ballast MOSFET drive output 15 PFC OUT Power Factor MOSFET drive output Output from the lamp current error transconductance amplifier used for lamp current loop compensation 16 VCC Positive supply for the IC 17 VREF Buffered output for the 7.5V voltage reference 18 EA–/OVP Inverting input to PFC error amplifier and OVP comparator input 5 6 7 8 2 LAMP FB LFB OUT RSET External resistor which sets oscillator FMAX, and RX/CX charging current RT/CT Oscillator timing components ML4832 ABSOLUTE MAXIMUM RATINGS Maximum Forced Voltage (IA OUT) ................................................. –0.3V to 7.5V Junction Temperature ............................................. 150°C Storage Temperature Range...................... –65°C to 150°C Lead Temperature (Soldering 10 sec.) ..................... 260°C Thermal Resistance (qJA) Plastic PDIP ..................................................... 70°C/W Plastic SOIC ................................................... 100°C/W Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Supply Current (ICC) ............................................... 60mA Output Current, Source or Sink (OUT A, OUT B, PFC OUT) DC ................................................................... 250mA Output Energy (capacitive load per cycle) ............... 1.5mJ Gain Modulator ISINE Input ..................................... 10mA Analog Inputs ....................................... –0.3V to VCC –2V IA+ Input Voltage .............................................. –3V to 2V Maximum Forced Voltage (EA OUT, LFB OUT) ................................ –0.3V to 7.7V Maximum Forced Current (EA OUT, IA OUT, LFB OUT) ............................ ±20mA OPERATING CONDITIONS Temperature Range ML4832C .................................................. 0°C to 85°C ELECTRICAL CHARACTERISTICS Unless otherwise specified, RSET = 22.1kW, RT = 15.8kW, CT = 1.5nF, C(VCC) = 1µF, ISINE = 200µA, VCC = 12.5V, TA = Operating Temperature Range (Note 1) PARAMETER CONDITIONS MIN TYP MAX 40 90 120 0.2 0.4 UNITS PFC CURRENT SENSE AMPLIFIER Output Low ISINE = 0mA, VEA OUT = 0V, VIA+ = –0.3V, RL = ¥ Output High ISINE = 1.5mA, VEA–/OVP = VIA+ = 0V, RL = ¥ Source Current ISINE = 1.5mA, VEA–/OVP = VIA+ = 0V, VIA OUT = 6V, TJ = 25ºC Sink Current ISINE = 0mA, VIA OUT = 0.3V, VIA+ = –0.6V VEA OUT = 0V, VEA–/OVP = 5V, TJ = 25ºC µ W Small Signal Transconductance V 6.3 6.8 V –0.05 –0.15 –0.25 mA 0.03 0.07 0.16 mA –0.3 –1.0 µA 55 90 PFC VOLTAGE FEEDBACK AMPLIFIER/LAMP CURRENT AMPLIFIER Small Signal Transconductance 30 Input Voltage Range –0.3 µ W Input Bias Current 5.0 V 0.2 0.4 V 7.1 7.5 7.8 V Output Low VLAMP FB = VEA–/OVP = 3V, RL = ¥ Output High VLAMP FB = VEA–/OVP = 2V, RL = ¥ Source Current VLAMP FB = VEA–/OVP = 0V, VEA OUT = VLFB OUT = 7V, TJ = 25ºC –0.06 –0.15 –0.30 mA Sink Current VLAMP FB = VEA–/OVP = 5V, VEA OUT = VLFB OUT = 0.3V, TJ = 25ºC 0.06 0.12 0.28 mA 3 ML4832 ELECTRICAL CHARACTERISTICS (Continued) PARAMETER CONDITIONS MIN TYP MAX UNITS GAIN MODULATOR Output Voltage (VMUL) ISINE = 100µA, VEA OUT = 3V 85 mV ISINE = 300µA, VEA OUT = 3V 260 mV ISINE =100µA, VEA OUT = 6V 200 mV ISINE = 300µA, VEA OUT = 6V 600 mV Output Voltage Limit ISINE = 1.5mA, VEA–/OVP = 0V Offset Voltage ISINE Input Voltage 1.1 V ISINE = 0µA, VEA–/OVP = 0V 15 mV ISINE = 150µA, VEA–/OVP = 3V 15 mV ISINE = 200µA 0.9 1 0.8 1.4 1.8 V –0.85 –1.0 –1.15 V PFC CURRENT — LIMIT COMPARATOR Current-Limit Threshold Propagation Delay 100mV step and 100mV overdrive 100 ns OSCILLATOR Initial Accuracy TA = 25°C Voltage Stability VCCZ – 4.0V < VCC < VCCZ – 0.5V 72 Temperature Stability Total Variation Line, temperature CT Discharge Current 80 kHz 1 % 2 % 69 Ramp Valley to Peak CT Charging Current 76 83 2.5 kHz V VLAMP FB = 3V, VRT/CT = 2.5V, VRX/CX = 0.9V (Preheat) –90 –113 –130 µA VLAMP FB = 3V, VRT/CT = 2.5V, RX/CX = Open –180 –230 –260 µA 4.0 5.5 7.0 mA 0.64 0.91 1.30 µs 7.4 7.5 7.6 V VRT/CT = 2.5V Output Drive Deadtime REFERENCE SECTION Output Voltage TA = 25°C, IO = 1mA Line regulation VCCZ – 4.0V < VCC < VCCZ – 0.5V 8 25 mV Load regulation 1mA < IO < 5mA 2 15 mV Temperature stability 0.4 7.35 % Total Variation Line, load, temp 7.65 V Output Noise Voltage 10Hz to 10kHz 50 µV Long Term Stability TJ = 125°C, 1000 hrs 5 mV Initial Preheat Period 0.8 s Subsequent Preheat Period 0.7 s Start Period 1.2 s Interrupt Period 5.7 s PREHEAT AND INTERRUPT TIMER (RX = 680KW, CX = 4.7µF) Pin 10 Charging Current 4 –24 –28 –33 µA ML4832 ELECTRICAL CHARACTERISTICS (Continued) PARAMETER CONDITIONS MIN TYP MAX UNITS 0.4 0.7 1.0 V 7.0 7.3 7.7 V 0.1 µA PREHEAT AND INTERRUPT TIMER (RX = 680KW, CX = 4.7µF) CONTINUIED Pin 10 Open Circuit Voltage VCC < Start-up threshold Pin 10 Maximum Voltage Input Bias Current VRX/CX = 1.2V Preheat Lower Threshold 1.05 1.22 1.36 V Preheat Upper Threshold 4.4 4.77 5.15 V Interrupt Recovery Threshold 1.05 1.22 1.36 V Start Period End Threshold 6.05 6.6 7.35 V 7.15 7.4 7.65 V 0.1 µA INTERRUPT INPUT Interrupt Threshold Input Bias Current RSET Voltage 2.4 2.5 2.6 V OVP Threshold 2.65 2.75 2.85 V Hysteresis 0.20 0.25 0.27 V OVP COMPARATOR Propagation Delay 1.4 µs OUTPUTS Output Voltage Low Output Voltage High IOUT = 20mA 0.1 0.2 V IOUT = 200mA 1.0 2.0 V IOUT = –20mA VCC – 0.2 VCC – 0.1 V IOUT = –200mA VCC – 2.0 VCC – 1.0 V Output Voltage Low in UVLO IOUT = 10mA, VCC 8V Output Rise/Fall Time CL = 1000pF 0.2 20 V ns UNDER-VOLTAGE LOCKOUT AND BIAS CIRCUITS IC Shunt Voltage (VCCZ) ICC = 15mA Start-up Current Operating Current 14.2 15.0 15.8 V VCC = Start-up threshold –0.2V 0.34 0.48 mA VCC = 12.5V, VIA+ = 0V, VEA–/OVP = VLAMP FB = 2.3V, IA OUT = open RT = 16.2kW, RSET = 22.1kW VCC = 12.5V, CL = 0 5.5 8.0 mA Start-up Threshold VCC – 1.2 VCCZ – 1.0 VCC – 0.8 V Shutdown Threshold VCC – 5.5 VCCZ – 5.0 VCC – 4.5 V Shutdown Temperature (TJ) 120 °C Hysteresis (TJ) 30 °C Note 1: Limits are guaranteed by 100% testing, sampling or correlation with worst case test conditions. 5 ML4832 FUNCTIONAL DESCRIPTION OVERVIEW GAIN MODULATOR The ML4832 consists of an average current controlled continuous boost power factor front end section with a flexible ballast control section. Start-up and lamp-out retry timing are controlled by the selection of external timing components, allowing for control of a wide variety of different lamp types. The ballast section controls the lamp power using frequency modulation (FM) with additional programmability provided to adjust the VCO frequency range. This allows for the IC to be used with a variety of different output networks. The ML4832 gain modulator provides high immunity to the disturbances caused by high power switching. The rectified line input sine wave is converted to a current via a series resistor. In this way, small amounts of ground noise produce an insignificant effect on the reference to the PWM comparator. The output of the gain modulator appears on the positive terminal of the IA amplifier to form the reference for the current error amplifier. Please refer to Figure 1. POWER FACTOR SECTION The ML4832 power factor section is an average current sensing boost mode PFC control circuit which is architecturally similar to that found in the ML4821. For detailed information on this control architecture, please refer to Application Note 16 and the ML4821 data sheet. VMUL = ISINE × 1VEA−0.7V6 34 . mA (1) where: ISINE is the current in the dropping resistor, VEA is the output of the error amplifier (Pin 1). The output of the gain modulator is limited to 1.0V. 7 10 16 17 11 2 LFB OUT RSET RX/CX VARIABLE FREQUENCY OSC PREHEAT TIMER UNDER-VOLTAGE AND THERMAL SHUTDOWN VREF – + –VMUL+ IA + 8 R S – PFC OUT Q 15 + –1V PWM (PFC) OUT A Q 14 + T GAIN MODULATORS ISINE OUT B Q 13 EA OUT – EA –/OVP 2.5V – + 2.75V + OVP Figure 1. ML4832 Block Diagram 6 9 VREF RT/CT IA OUT – 18 INTERRUPT 5 GND 7k 1 LAMP FB – – 3 2.5V + VCC 7k 4 + 6 P GND 12 ML4832 FUNCTIONAL DESCRIPTION (Continued) TRANSCONDUCTANCE AMPLIFIERS AVERAGE CURRENT AND OUTPUT VOLTAGE REGULATION The PWM regulator in the PFC control section will act to offset the positive voltage caused by the multiplier output by producing an offsetting negative voltage on the current sense resistor at IA+. A cycle-by-cycle current limit is included to protect the MOSFET from high speed current transients. When the voltage at IA+ goes negative by more than 1V, the PWM cycle is terminated. The PFC voltage feedback, PFC current sense, and the loop current amplifiers are all implemented as operational transconductance amplifiers. They are designed to have low small signal forward transconductance such that a large value of load resistor (R1) and a low value ceramic capacitor (<1µF) can be used for AC coupling (C1) in the frequency compensation network. The compensation network shown in Figure 2 will introduce a zero and a pole at: For more information on compensating the average current and boost voltage error amplifier loops, see ML4821 data sheet. fZ = OVERVOLTAGE PROTECTION AND INHIBIT The OVP pin serves to protect the power circuit from being subjected to excessive voltages if the load should change suddenly (lamp removal). A divider from the high voltage DC bus sets the OVP trip level. When the voltage on EA–/OVP exceeds 2.75V, the PFC transistors are inhibited. The ballast section will continue to operate. 18 – 2.5V + 1 2π R1C1 fP = 1 2π R1C 2 (2) Figure 3 shows the output configuration for the operational transconductance amplifiers. A DC path to ground or VCC at the output of the transconductance amplifiers will introduce an offset error. R1 C2 C1 Figure 2. Compensation Network CURRENT MIRROR IN OUT IQ + IQ – iO gmVIN 2 io = gmVIN gmVIN 2 VIN Differential 0 Linear Slope Region IN OUT CURRENT MIRROR Figure 3. Output Configuration Figure 4. Transconductance Amplifier Characteristics 7 ML4832 FUNCTIONAL DESCRIPTION (Continued) The magnitude of the offset voltage that will appear at the input is given by VOS = io/gm. For an io of 1mA and a gm of 0.05 µmhos the input referred offset will be 20mV. Capacitor C1 as shown in Figure 2 is used to block the DC current to minimize the adverse effect of offsets. Slew rate enhancement is incorporated into all of the operational transconductance amplifiers in the ML4832. This improves the recovery of the circuit in response to power up and transient conditions. The response to large signals will be somewhat non-linear as the transconductance amplifiers change from their low to high transconductance mode. This is illustrated in Figure 4. FOSC = t CHG = RT C T In The VCO frequency ranges are controlled by the output of the LFB amplifier. As lamp current decreases, LFB OUT rises in voltage, causing the CT charging current to decrease, thereby causing the oscillator frequency to decrease. Since the ballast output network attenuates high frequencies, the power to the lamp will be increased. VREF + ICH R T − VTL + ICH RT − VTH 1 0.51× RT C T 1.25/3.75 1. The output of the preheat timer 2. The voltage at LFB OUT In preheat condition, charging current is fixed at ICHG (PREHEAT) = 25 . RSET CONTROL tDIS – CT 5.5mA VTH = 3.75V CT VTL = 1.25V Figure 5. Oscillator Block Diagram and Timing 8 (5) When LFB OUT is high, ICH = 0 and the minimum frequency occurs. The charging current varies according to two control inputs to the oscillator: + 8 (4) This assumes that tCHG >> tDIS. CLOCK RT/CT The oscillator’s minimum frequency is set when ICH = 0 where: VREF ICHG RT REF REF The oscillator frequency is determined by the following equations: 17 V V FOSC ≅ OSCILLATOR (3) and BALLAST OUTPUT SECTION The IC controls output power to the lamps via frequency modulation with non-overlapping conduction. This means that both ballast output drivers will be low during the discharging time tDIS of the oscillator capacitor CT. 1 t CHG + tDIS tCHG (6) ML4832 FUNCTIONAL DESCRIPTION (Continued) In running mode, charging current decreases as the VPIN6 rises from 0V to VOH of the LAMP FB amplifier. The highest frequency will be attained when ICHG is highest, which is attained when LFB OUT is at 0V: ICHG(0) = 5 (7) R SET Highest lamp power, and lowest output frequency are attained when LFB OUT is at its maximum output voltage (VOH). In this condition, the minimum operating frequency of the ballast is set per (5) above. For the IC to be used effectively in dimming ballasts with higher Q output networks a larger CT value and lower RT value can be used, to yield a smaller frequency excursion over the control range (VLFB OUT). The discharge current is set to 5.5mA. Assuming that IDIS >> IRT: t DIS(VCO) ≅ 600 × CT (8) IC BIAS, UNDER-VOLTAGE LOCKOUT AND THERMAL SHUTDOWN The IC includes a shunt regulator which will limit the voltage at VCC to 15V (VCCZ). The IC should be fed with a current limited source, typically derived from the ballast transformer auxiliary winding. When VCC is below VCCZ – 1.1V, the IC draws less than 0.48mA of quiescent current and the outputs are off. This allows the IC to start using a “bleed resistor” from the rectified AC line. To help reduce ballast cost, the ML4832 includes a temperature sensor which will inhibit ballast operation if the IC’s junction temperature exceeds 120°C. In order to use this sensor in lieu of an external sensor, care should be taken when placing the IC to ensure that it is sensing temperature at the physically appropriate point in the ballast. The ML4832’s die temperature can be estimated with the following equation: T J ≅ TA × PD × 65° C / W (9) STARTING, RE-START, PREHEAT AND INTERRUPT The lamp starting scenario implemented in the ML4832 is designed to maximize lamp life and minimize ballast heating during lamp out conditions. The circuit in Figure 7 controls the lamp starting scenarios: Filament preheat and lamp out interrupt. CX is charged with a current of IRSET/4 and discharged through RX. The voltage at CX is initialized to 0.7V (VBE) at power up. The time for CX to rise to 4.8V is the filament preheat time. During that time, the oscillator charging current (ICHG) is 2.5/RSET. This will produce a high frequency for filament preheat, but will not produce sufficient voltage to ignite the lamp. After cathode heating, the inverter frequency drops to FMIN causing a high voltage to appear to ignite the lamp. If the voltage does not drop when the lamp is supposed to have ignited, the lamp voltage feedback coming into pin 9 rises to above VREF, the CX charging current is shut off and the inverter is inhibited until CX is discharged by RX to the 1.2V threshold. Shutting off the inverter in this manner prevents the inverter from generating excessive heat when VCC VCCZ VON 0.625 RSET VOFF RX/CX + 10 HEAT CX t ICC 1.2/4.8 – RX 6.8 5.5mA + 1.2/6.8 DIMMING LOCKOUT – INHIBIT R 0.34mA t 9 INT VREF Figure 6. Typical VCC and ICC Waveforms when the ML4832 is Started with a Bleed Resistor from the Rectified AC Line and Bootstrapped from an Auxiliary Winding. – Q S + Figure 7. Lamp Preheat and Interrupt Timers 9 ML4832 FUNCTIONAL DESCRIPTION (Continued) the lamp fails to strike or is out of socket. Typically this time is set to be fairly long by choosing a large value of RX. LFB OUT is ignored by the oscillator until CX reaches 6.8V threshold. The lamps are therefore driven to full power and then dimmed. The CX pin is clamped to about 7.5V. A summary of the operating frequencies in the various operating modes is shown below. OPERATING MODE OPERATING FREQUENCY Preheat [F(MAX) to F(MIN)] 2 Dimming Lock-out F(MIN) DIMMING CONTROL F(MIN) TO F(MAX) 6.8 4.8 RX/CX 1.2 .65 0 HEAT DIMMING LOCKOUT 7.5 INT INHIBIT Figure 8. Lamp Starting and Restart Timing 10 ML4832 TYPICAL APPLICATIONS Figures 9 and 10 show ballast schematics, both nondimming and dimming. These are power-factor corrected 60W ballasts designed to operate two series connected F32T8 fluorescent lamps. Both Schematics, Figures 9 and 10, are of previously published ML4831 circuits that have been modified for ML4832 compatibility. The value changes and component additions made for ML4832 compatibility were for different amplifier compensation, bootstrap/bias and protection and do not effect the validity of the circuit description, operational information or equations. TO CONVERT FROM AN EXISTING NON-DIMMING ML4831 TO THE ML4832: TO CONVERT FROM AN EXISTING DIMMING ML4831 TO THE ML4832: Resistors Resistors Change: Add: Delete: to 51kW, 1/4 W, 5% carbon film to 51kW, 1/4 W, 5% carbon film R6, R7 to 866kW, 1/4 W, 1%, metal film R6, R11 to 866kW, 1/4 W, 1%, metal film R7 to 75kW, 1/4 W, 5%, carbon film R7 to 75kW, 1/4 W, 5%, carbon film R18 to 470W, 1/4 W, 5%, carbon film R18 to 470W, 1/4 W, 5%, carbon film R13 to 5.76kW, 1/4 W, 1%, metal film R13 to 5.76kW, 1/4 W, 1%, metal film R14 to 499kW, 1/4 W, 5%, carbon film R14 to 499kW, 1/4 W, 5%, carbon film R24 75kW, 1/4 W, 5%, carbon film R26 to 200kW, 1/4 W, 5%, carbon film R22 51W, 1/4 W, 5%, carbon film R23 100W, 1/4 W, 5%, carbon film R4 Add: Delete: C5 to 10nF, 63V, 10% ceramic Capacitors C7 to 180pF, 100V, 5% ceramic Change: C11 to C12 R4 R32 75kW, 1/4 W, 5%, carbon film R30 51W, 1/4 W, 5%, carbon film R31 100W, 1/4 W, 5%, carbon film R9 C5 to 10nF, 63V, 10% ceramic 1nF, 100V, 10% ceramic C7 to 180pF, 100V, 5% ceramic to 100nF, 100V, 10% ceramic C25 to 1nF, 100V, 10% ceramic C18 to 100µF, 16V, 20% electrolytic C12 to 100nF, 100V, 10% ceramic C20 to 100µF, 25V, 20% electrolytic C24 to 100µF, 16V, 20% electrolytic 33nF, 50V, 20% ceramic C20 to 100µF, 25V, 20% electrolytic C23 Magnetics Change: Add: R9 Capacitors Change: Change: Add: T1 to TSD-882 C27 33nF, 50V, 20% ceramic C26 100nF, 100V, 10% ceramic Diodes Delete: D10, D13 Magnetics Change: T1 to TSD-882 11 12 L1 Figure 9. 220V Non-Dimming Ballast R23 100Ω R1 1.0Ω D4 1A R4 51kΩ C7 C5 C12 C11 10nF 100nF 1nF 180pF R14 499kΩ D6 1A D5 1A C2 2.2nF D3 C1* C3 1A 2.2nF 0.15µF *Note: Only One Chassis Ground NEUTRAL 220 VAC F1 8 7 D9 1A 9 10 R5 15.4kΩ C6 2.2nF R6 866kΩ R8 22Ω 11 10 9 C4 R15 0.1µF 324k 12 8 13 14 15 16 7 6 5 4 3 17 18 1 2 R21 5kΩ C13 10µF C10 47µF D7 1A Q1 2.5A R18 470Ω T1 D12 1A R10 11.5kΩ D13 0.1A C20 R11 100µF 866kΩ C23 33nF D2 1A D1 1A ML4832 HOT TP3 C18 100µF R24 75kΩ R7 75kΩ 7 6 C14 C15 C16 0.22µF 0.22µF 100pF TP2 R13 5.76kΩ R12 442kΩ R20 442kΩ 8 1 2 3 R22 51Ω C17 1µF T2 TP1 R19 51Ω R3 9.1kΩ R2 1kΩ Q3 IRF820 R17 51Ω Q2 IRF820 C19 D11 IN4148 C22 33nF 7 6 8 1 9 2 3 4 C21 0.001µF C8 4700pF C9 33nF T3 R16 1kΩ D8 IN4148 TP4 TP5 B B Y Y R R ML4832 HOT L2 C27 33nF R31 100Ω R1 1.0Ω D2 1A R6 866kΩ R11 866kΩ R5 15.4kΩ R3 220kΩ D1 1A C4 C12 C25 C7 C5 10nF 100nF 1nF 180pF 3.3µF R2 4.3kΩ D4 1A D3 1A R4 R14 499kΩ 51kΩ D6 1A D5 1A C3 0.15nF C2 2.2nF C1* 2.2nF *Note: Only One Chassis Ground NEUTRAL 220 VAC F1 D9 1A 9 10 C6 2.2nF 10 TP3 R15 324kΩ 11 9 12 13 14 15 16 8 7 6 5 4 3 17 18 2 1 R18 470Ω R8 22Ω C13 10µF C10 47µF Q1 2.5A D7 1A R25 5kΩ T1 R10 11.5kΩ C20 100µF 8 7 D15 1A ML4832 L1 R16 10kΩ C15 0.22µF C24 100µF R32 75kΩ R7 75kΩ C14 0.22µF D16 5.1V R29 1.3kΩ R13 5.76kΩ R12 442kΩ R23 442kΩ 8 1 2 3 R30 51 C17 1µF T2 C16 100pF 7 6 Q2 2.5A Q3 2.5A C21 1µF R20 10kΩ D11 0.1A TP2 TP1 R19 51Ω R17 51Ω R22 11kΩ R26 200kΩ R24 64.9kΩ 6 5 2 3 8 3 9 4 1 2 C9 15nF T4 – + 4 IC1 – + 8 R27 200kΩ C8 4700pF 7 6 C26 100nF C22 0.33µF TP4 7 1 TP5 10 1 D8 0.1A R28 20kΩ 6 T5 5 B B Y Y R R ML4832 Figure 10. 220V Dimming Ballast 13 ML4832 PHYSICAL DIMENSIONS inches (millimeters) Package: P18 18-Pin PDIP 0.890 - 0.910 (22.60 - 23.12) 18 0.240 - 0.260 0.295 - 0.325 (6.09 - 6.61) (7.49 - 8.26) PIN 1 ID 1 0.045 MIN (1.14 MIN) (4 PLACES) 0.050 - 0.065 (1.27 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN) 0.170 MAX (4.32 MAX) SEATING PLANE 0.016 - 0.022 (0.40 - 0.56) 0.125 MIN (3.18 MIN) 0º - 15º 0.008 - 0.012 (0.20 - 0.31) Package: S18 18-Pin SOIC 0.449 - 0.463 (11.40 - 11.76) 18 0.291 - 0.301 0.398 - 0.412 (7.39 - 7.65) (10.11 - 10.47) PIN 1 ID 1 0.024 - 0.034 (0.61 - 0.86) (4 PLACES) 0.050 BSC (1.27 BSC) 0.095 - 0.107 (2.41 - 2.72) 0º - 8º 0.090 - 0.094 (2.28 - 2.39) 14 0.012 - 0.020 (0.30 - 0.51) SEATING PLANE 0.005 - 0.013 (0.13 - 0.33) 0.022 - 0.042 (0.56 - 1.07) 0.009 - 0.013 (0.22 - 0.33) ML4832 ORDERING INFORMATION © Micro Linear 1999. PART NUMBER TEMPERATURE RANGE PACKAGE ML4832CP (End of Life) ML4832CS (Obsolete) 0°C to 85°C 0°C to 85°C Molded PDIP (P18) SOIC (S18) is a registered trademark of Micro Linear Corporation. All other trademarks are the property of their respective owners. Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174; 5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669; 5,825,165; 5,825,223; 5,838,723; 5.844,378; 5,844,941. Japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. Other patents are pending. Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application. 02/19/99 Printed in U.S.A. DS4832-01 2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295 15