For Communications Equipment MN86157 Shading Correction LSI Features Choice of correction range (50% or 75%) depending on extent of shading distortion Parallel A/D converter functions Resolution: 7 bits A6 A7 A8 A9 A10 A11 N.C. MODE ENBO CKSH ENBI A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 D4 33 32 31 30 29 28 27 26 25 24 23 The MN86157 contains a 7-bit A/D converter for use in correcting, at the bit level, shading distortion for signals from image sensors, optics, and similar sources. It uses external RAM to support adaptive correction that responds to changes in distortion patterns. It also uses ROM to provide fixed correction when a white reference plane signal is not available. The chip is also usable as a stand-alone A/D converter. Pin Assignment 22 21 20 19 18 17 16 15 14 13 12 34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 Overview Conversion speed: max. 5 MHz Note: This is the guaranteed design value for the chip used as a stand-alone A/D converter. The guaranteed value at shipment is ±3 LSB Ability to start and stop clock in the middle of a line to support CdS contacting image sensors and other devices with variable scanning rates Overflow pin that simplifies task of adding auto background control (ABC) circuit Single 5 volt power supply Guaranteed TTL levels for input Applications Facsimile equipment D5 D6 ROS MOE OVF/DB6 DB5 DB4 DB3 DB2 DB1 DB0 Non-linearity: ±1/2 LSB (TOP VIEW) QFP044-P-1010 SHST R/W INHI VSS VDD N.C. VREFL VIN VREFH VDD OE ENBO CKSH ENBI SHST INHI MODE VREFL VREFH VR 25 24 23 22 20 26 ADC 12 Controller 7 7 7 7 DistortionCoefficient ROM RAM or ROM 7 7 Selector 7 SHADING CORRECTOR LSI Multiplier 7 7 19 18 13 3 5 6 12 DB0 to 5 VSS VDD VDD ROS OVF/DB6 OE MN86157 For Communications Equipment Block Diagram Selector D0 to 6 Selector A0 to 11 21 R/W 4 MOE For Communications Equipment MN86157 Block Configuration The MN86157 consists of four basic blocks: (1) A/D converter, (2) distortion coefficient mapping ROM, (3) multiplier, and (4) controller. The following are brief descriptions of each block. (1) A/D converter This uses comparison with the reference voltages to convert the scanner's image data signal from the VIN pin to a 7-bit digital output. (2) Distortion coefficient mapping ROM This constitutes a look-up table for converting the A/D converter output to a final value for storage in the external RAM. (3) Multiplier This provides high-speed parallel multiplication of 7 × 7 bits data. (4) Controller This controls operation of the shading correction circuits, the A/D converter, and interface to external ROM or RAM. MN86157 Operation Shading correction (MODE pin at "H" level) • Fixed distortion coefficients (external memory is ROM) This configuration provides 6-bit corrected data using fixed distortion coefficients stored in an external ROM and thus invariant. • Adaptive distortion coefficients (external memory is RAM) This configuration provides 6-bit corrected data using distortion coefficients, stored in external RAM, that the chip constantly updates using white reference plane line training. • Pixels per line The chip supports line lengths up to 4096 pixels with a built-in 12-bit address counter supporting interfaces to two 211 × 8-bit RAM chips or the equivalent of a 2732 ROM (212 × 8 bits). • Input clock The chip uses an input clock signal with a frequency twice that of the image clock. • Selecting correction range The ROS pin provides a choice of two correction ranges and consequently correction precisions. ROS • • Correction Range Correction Precision H 50% ±1.5% L 75% ±3.0% Correction start/stop function Pulling the INHI pin to "L" level in the middle of a line suspends correction and maintains the output data at its current value. Returning the pin to "H" level restarts correction. Auto clamp and overflow functions for output data If the image input signal level exceeds the white reference plane level, the chip clamps the output data at the full-scale value (3FH) and drives the overflow pin (OVF) at "H" level. MN86157 For Communications Equipment Stand-alone A/D converter (MODE pin at "L" level, A10 pin at "L" level) • In this configuration, the chip functions as a parallel A/D converter consisting of 128 chopper comparators. Resolution: 7 bits Non-linearity: ±1/2 LSB Conversion speed: max. 5 MHz Analog input range: 3V p-p (VDD 5V) • Clock mode selection The A11 pin provides a choice of two clock modes. A11 L CKSH: Input Clock Conditions Supply a clock signal with a frequency twice that of the input image clock. *1 SHST: Supply the A/D start signal for use in synchronizing phase. CKSH: Supply a clock signal with a frequency twice that of the input image clock. *2 H ENBI: Supply a clock signal with the same frequency as the input image clock. Notes *1: ENBI *2: SHST: Keep this pin at "H" level. For Communications Equipment MN86157 Pin Descriptions Parameter A/D Pin No. 15 Symbol VIN I/O I Function Description Analog image signal input Remarks converter 14 VREFH — Reference voltage input "H" level reference voltage input block 16 VREFL — Reference ground "L" level reference voltage input MULT 11 to 6 DB 0 to 5 O Corrected image signal output MODE: H /A/D converter data output /MODE: L 5 OVF/DB6 O Corrected image signal overflow MODE: H 12 OE I CTL 23 ENBI I converter 22 SHST I converter block output/A/D converter data output /MODE: L block 24 CKSH I Output enable signal input H: Pins are high-impedance; for DB0 – DB5 and OVF L: Pins provide output Enable signal input for single line Start input for reading white Low pulse reference signal signals start. Clock signal input The frequency must be twice that of the image clock. 20 INHI I Signal for suspending correction in the middle of a line and holding the output at the current value 25 ENBO 3 ROS 26 MODE 39 to 28 O H: Normal correction operation; L: Stop and hold Enable signal for corrected image data output RAM /ROM IO converter block 40 to 44, 1, 2 I Correction range selection I Operating mode selection A 0 to 11 O RAM/ROM address output D 0 to 6 I/O RAM/ROM data I/O 21 R/W O RAM read/write signal 4 MOE O RAM/ROM output enable signal H: 50% correction; L: 75% correction H: Shading correction; L: A/D conversion only MN86157 For Communications Equipment AG VSS D6 to GND D0 AG ENBO(O) MOE ROS A11 SHST(I) SHST ENBI(I) ENBI A10 to A0 CKSH(I) CKSH PIX VIN MODE D0 to D6 WE OE CS A0 to A10 ENBO INHI(I) ROS (H/L) D0 to D6 OE CS A0 to A10 VR MN86157 AG VREF 5V R/W VDD VDD WE AVDD 5V RAM (4 Kilowords × 8 bits) RAM (4 Kilowords × 8 bits) OE AG DB5 to DB0 DB0 to 5(O) Application Circuit Example #1: Using RAM For Communications Equipment MN86157 OE DB0 AG DB5 to DB0 to 5(O) Application Circuit Example #2: Using ROM AG VSS GND INHI(I) INHI ENBI(I) ENBI CKSH(I) CKSH ROS(H/L) MOE A11 to A0 ROS SHST MODE ROM 2732 D6 CE ENBO VIN ENBO(O) VR PIX VREF 5V MN86157 AG VDD VDD OE A11 to A0 AVDD 5V D0 to AG D6 to D0 MN86157 For Communications Equipment Packing Dimensions (Unit: mm) QFP044-P-1010 12.30±0.40 10.00±0.20 33 23 22 44 12.30±0.40 10.00±0.20 (1.00) 34 12 0.10 SEATING PLANE 0.10±0.10 0 to 10° 1.15±0.20 +0.10 2.00±0.20 (1.00) 11 0.35±0.10 0.15 -0.05 0.80 2.10±0.30 1 0.60±0.20