E2C0024-27-Y4 ¡ Semiconductor MSC1230 ¡ Semiconductor This version: Nov. 1997 MSC1230 Previous version: Jul. 1996 111-Bit 2/3-Duty Controller/Driver with Digital Dimming Function GENERAL DESCRIPTION The MSC1230 is a Bi-CMOS display driver with digital dimming function. It enables switching between 1/3-duty vacuum fluorescent (VF) display tube and universal VF display tube by pin control. The MSC1230 consists of a 112-bit shift register, a 111-bit latch, a 10-bit digital dimming circuit, 37 segment drivers, and 3 grid drivers. The MSC1230 provides an interface with a microcomputer only by three signal lines: CS, DATA-IN, and CLOCK. By using the chip select function, the DATA-IN and CLOCK signal lines can be shared by other peripheral circuits. FEATURES • • • • • • Power supply voltage : VDD=8 V to 18 V (built-in 5 V regulator for logic circuit) Operating temperature range : Ta=–40 °C to +85 °C 37-segment driver outputs : IOH=–6 mA at VOH = VDD –0.8 V 3-grid driver outputs : IOH=–30 mA at VOH = VDD –0.8 V Built-in digital dimming circuit (10-bit resolution) Switchable between 1/3-duty VF display tube and universal VF display tube* When SEL pin is left open : Selects universal VF display tube (The grids GRID1, GRID2, and GRID1+GRID2 are turned on repeatedly in this order) When SEL pin is used at 0 V : Selects 1/3-duty VF display tube (The grids GRID1, GRID2, and GRID3 are turned on repeatedly in this order) • Built-in oscillation circuit (external R and C) • Built-in Power-On-Reset circuit • Package: 56-pin plastic QFP (QFP56-P-910-0.65-2K)(Product name: MSC1230GS-2K) * A universal VF display tube is a display tube for which, like a gate array, the user can freely design characters and patterns on the master layer (grid). (Pattern can be created without gaps between grids.) Since the outline dimensions of the display tube and the grid layout are predetermined, desired patterns can be displayed in a short time. The universal VF display tube is used for the display parts for audio equipment, household appliances, and automobile equipment. 1/13 ¡ Semiconductor MSC1230 BLOCK DIAGRAM SEG37 SEG1 GRID3 VDD3 GRID1 VDD1 VDD2 37-bit Segment Driver DGND 5V REG. 5V POR POR 3-bit Grid Driver VDD=8 - 18V 37bit data 37 1 111 37-Segment Control VCC=5.0V (Regurator) LGND 37 111 37 37 75 74 CS 38 37 1 111-bit Latch Control Circuit 111-bit data 112 111 DATA-IN 107106 CLOCK 97 96 112-bit Shift Register 1 10-bit data 10-bit Latch 10-bit data OSC0 OSC OSC1 10-bit Digital Diming 5V POR Timing Generator SEL 112bits=0: Digital Dimming Mode 112bits=1: VF Data Input Mode INPUT AND OUTPUT CONFIGURATION l Schematic Diagram 1 of l Schematic Diagram 2 of l Schematic Diagram of Logic Portion Input Circuit Logic Portion Input Circuit Driver Output Circuit VDD VDD (5V Reg.) INPUT (5V Reg.) VDD OUTPUT COLn GND GND VDD GND GND GND GND 2/13 ¡ Semiconductor MSC1230 43 SEG10 44 SEG11 45 SEG12 46 SEG13 47 VDD1 48 NC 49 DGND 50 NC 52 SEG14 53 SEG15 54 SEG16 55 SEG17 56 SEG18 51 VDD2 PIN CONFIGURATION (TOP VIEW) SEG27 9 34 SEG1 SEG28 10 33 NC SEG29 11 32 GRID1 SEG30 12 31 GRID2 SEG31 13 30 GRID3 SEG32 14 29 VDD3 DATA-IN 28 35 SEG2 CLOCK 27 36 SEG3 SEG26 8 CS 26 SEG25 7 SEL 25 37 SEG4 OSC0 24 38 SEG5 SEG24 6 OSC1 23 SEG23 5 NC 22 39 SEG6 NC 20 LGND 21 40 SEG7 SEG22 4 SEG37 19 SEG21 3 SEG36 18 41 SEG8 SEG35 17 SEG20 2 SEG34 16 42 SEG9 SEG33 15 SEG19 1 NC: No connection 56-Pin Plastic QFP 3/13 ¡ Semiconductor MSC1230 PIN DESCRIPTION Pin 34 to 46, 52 to 56, 1 to 19 30 to 32 Symbol SEG1 to 37 Type Decription O Output pins for segment signals for driving VF display tube. GRID1 to 3 O Output pins for grid signals for driving VF display tube. The GRID3 output is not used when the universal VF display tube is used. 25 SEL I When at a "L" level, this pin selects 1/3-duty VF display tube. When at a "H" level (or when used in the open state), this pin selects universal VF display tube. 28 DATA-IN I Pin for series data input from microprocessor. Data is input to the shift register on the rising edge of the CLOCK signal. 27 CLOCK I Serial clock input pin. Data is input through the DATA-IN pin at the rising edge of the serial clock. 24 OSC0 I 23 OSC1 O 26 CS I RC oscillator connecting pins. Connect a resistor between the OSC1 and OSC0 pins and a capacitor between the OSC0 pin and the ground. Chip select input pin. Circuit operation is valid when this pin is at a "L" level. 47 51 29 VDD1 VDD2 VDD3 — Power supply pins. When using these pins, connect each of them to the power supply. 49 DGND — 21 LGND — Ground pins for driver and logic. These pins can be connected with each other when they are used. 4/13 ¡ Semiconductor MSC1230 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Ratings Unit Supply Voltage VDD V VIN — All inputs –0.3 to +20 Input Voltage –0.3 to +6.0 V Storage Temperature TSTG — –65 to +150 °C PD Ta=85°C 400 mW Power Dissipation RECOMMENDED OPERATING CONDITIONS Symbol Condition Min. Typ. Max. Unit Supply Voltage Parameter VDD — 8 — 18 V High Level Input Voltage (1) VIH1 All inputs except OSC0 3.8 — 5.5 V High Level Input Voltage (2) VIH2 OSC0 4.5 — 5.5 V Low Level Input Voltage (1) VIL1 All inputs except OSC0 0.0 — 0.8 V Low Level Input Voltage (2) VIL2 OSC0 0.0 — 0.5 V fC — — — 250 kHz Oscillation Frequency fOSC R=4.7 kW, C=10 pF — 3.2 — MHz Frame Frequency fFR fOSC=3.2 MHz — 260 — Hz Operating Temperature Top — –40 — 85 °C Clock Frequency 5/13 ¡ Semiconductor MSC1230 ELECTRICAL CHARACTERISTICS DC Characteristics (Ta=–40 to +85°C, VDD=8 to 18V) Parameter "H" Input Voltage (1) *1 "H" Input Voltage (2) *2 "L" Input Voltage (1) *1 "L" Input Voltage (2) *2 "H" Input Current (1) *3 "H" Input Current (2) *4 "L" Input Current (1) *3 "L" Input Current (2) *4 "H" Output Voltage (1) *5 "H" Output Voltage (2) *6 "L" Output Voltage Supply Current *1 *2 *3 *4 *5 *6 *7 *7 Symbol Condition Min. Max. Unit VIH1 — 3.8 5.5 V VIH2 — 4.5 5.5 V VIL1 — 0.0 0.8 V VIL2 — 0.0 0.5 V IIH1 VIH=5 V –5 5 mA IIH2 VIH=5 V –200 200 mA IIL1 VIL=0 V –5 5 mA IIL2 VIL=0 V –0.6 –0.1 mA VOH1 VDD=9.5 V IOH1=–6 mA VDD –0.8 — V VOH2 VDD=9.5 V IOH2=–30 mA VDD –0.8 — V VOL1 VDD=9.5 V IOL1=500 mA — 2 V VOL2 VDD=9.5 V IOL2=200 mA — 1 V VOL3 VDD=9.5 V IOL3=2 mA — 0.3 V IDD fosc=3.2 MHz no Load — 13 mA All input pins except OSC0 OSC0 pin CS, CLOCK and DATA-IN pins SEL pin SEG1 to SEG37 pins GRID1 to GRID3 pins SEG1 to SEG37 and GRID1 to GRID 3 pins 6/13 ¡ Semiconductor MSC1230 AC Characteristics (Ta=–40 to +85°C, VDD=8 to 18V) Min. Max. Unit Symbol Condition Oscillation Frequency fOSC R=4.7 kW , C=10 pF 2 4.4 MHz External Input Frequency into OSC0 fOSCI External input only 2.7 3.7 MHz fC — — 250 kHz Clock Pulse Width tCW — 1.3 — ms DATA Setup Time tDS — 1 — ms DATA Hold Time tDH — 200 — ns CS Pulse Width tCSW — 8 — ms CS Off Time tCSL — 32 — ms CS Setup Time CS-Clock Time tCSS — 2 — ms CS Hold Time Clock-CS Time tCSH — 2 — ms CS-All Data Output Delay tODS CI=100 pF — 8 ms Slew Rate (All Drivers) tR CI=100 pF t=20% to 80% or 80% to 20% — 5 ms CS Time at Power-on tPCS — 300 — ms Hold Time at Power-off tPOF When monuted on the unit VDD=0.0 V 5 — ms Rise Time at Power-on tPRZ When monuted on the unit — 100 ms Parameter Clock Frequency 7/13 ¡ Semiconductor MSC1230 tcsw CS tCSL tcss 3.8V 0.8V fc tcw CLOCK tDS DATA-IN tDH tDS VALID tcw tDH tCSH tDS VALID tDH 3.8V 0.8V 3.8V 0.8V VALID Figure 1. Data Input Timing tCSW CS tODS tODS tR tR 3.8V 0.8V 80% 20% SEG1-37 GRID1-3 Figure 2. SEG or GRID Driver Output Timing VDD1, 2, 3 tPCS tPOF tPRZ 8V 0V 3.8V 0.8V CS Figure 3. Power-on Timing 8/13 ¡ Semiconductor MSC1230 FUNCTIONAL DESCRIPTION Power-on Reset When power is turned on, the IC is initialized by the internal power-on reset circuit. The status of the internal circuit after initialization is as follows: – The contents of the shift registers and latches are set to "0". – The digital dimming duty cycle is set to "0". Data Input Data input to the DATA-IN pin is valid only when the CS pin is at a "L" level. The input data to DATA-IN is shifted into the shift registers on the rising edge of the clock. The data is automatically loaded to the latches on the rising edge of the CS pin. When M0 = "1", the IC enters the display data input mode and a total of 112 bits of data are input. When M0 = "0", the IC enters the digital dimming data input mode and a total of 16 bits of data are input. [Data Format] 1) Display Data Input Mode Input Data : VF Display Data : Mode Select Data (M0) : Bit 112 111 110 .... M0 D111 D110 .... Mode Data (1 bit) 112 bits 111 bits 1 bit 97 96 95 94 93 92 91 D97 D96 D95 D94 D93 D92 D91 .... .... 4 D4 3 D3 2 D2 1 D1 First in Display Data (111 bits) 2) Bit correspondence between segment outputs and shift registers 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 SEG 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 G1 BIT 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 G2 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 G3 9/13 ¡ Semiconductor MSC1230 3) Input Format for VF data Byte c7 c6 c5 c4 c3 c2 c1 c0 1 D8 D7 D6 D5 D4 D3 D2 D1 2 D16 D15 D14 D13 D12 D11 D10 D9 3 D24 D23 D22 D21 D20 D19 D18 D17 4 D32 D31 D30 D29 D28 D27 D26 D25 5 D40 D39 D38 D37 D36 D35 D34 D33 6 D48 D47 D46 D45 D44 D43 D42 D41 7 D56 D55 D54 D53 D52 D51 D50 D49 8 D64 D63 D62 D61 D60 D59 D58 D57 9 D72 D71 D70 D69 D68 D67 D66 D65 10 D80 D79 D78 D77 D76 D75 D74 D73 11 D88 D87 D86 D85 D84 D83 D82 D81 12 D96 D95 D94 D93 D92 D91 D90 D89 13 D104 D103 D102 D101 D100 D99 D98 D97 14 M0 D111 D110 D109 D108 D107 D106 D105 4) Digital Dimming Data Input Mode This data consists of 10 bits. The output duty changes in the range of 0/1024 (0%) to 1016/1024 (99%) for each grid. The 10-bit digital dimming data is input from the LSB. Input Data : 16 bits Digital Dimming Data : 10 bits Mode Select Data : 1 bit Bit 112 111 M0 xx Mode Data (1bit) 110 xx 109 xx (MSB) 108 xx 107 xx 106 105 10 9 MSB 104 8 103 7 102 6 101 5 100 4 Dimming Data (10 bits) INPUT DATA 99 3 98 2 97 1 LSB First in (LSB) DUTY CYCLE 0 0 0 0 0 0 0 0 0 0 0/1024 0 0 0 0 0 0 0 0 0 1 1/1024 1 1 1 1 1 1 1 0 0 0 1016/1024 1 1 1 1 1 1 1 1 1 1 1016/1024 10/13 ¡ Semiconductor MSC1230 5) Input Format for Dimming Data Byte c7 c6 c5 c4 c3 c2 c1 c0 1 8 7 6 5 4 3 2 1 2 M0 xx xx xx xx xx 10 9 6) Function Mode M0 FUNCTION 0 Display Data Input Mode 1 Digital Dimming Data Input Mode GRID/SEG Driver Operation and Digital Dimming Figures 4 and 5 show the timing for the GRID and SEG drivers in universal VFD mode and 1/3 duty VFD mode, respectively. Figure 6 shows an example of timing for digital dimming operation in 1/3 duty VFD mode. (When the duty cycle in the dimming data is 508/1024) GRID1 GRID2 3072 bit time (1 display cycle) GRID3 3 bit time SEG1-37 1019 bit time 5 bit time 8 bit time 1024 bit time * 1 bit time=4/fOSC Figure 4. Duty Cycle Timing (Universal VFD Mode) 11/13 ¡ Semiconductor MSC1230 GRID1 GRID2 3072 bit time (1 display cycle) GRID3 3 bit time SEG1-37 1019 bit time 5 bit time 8 bit time 1024 bit time Figure 5. Duty Cycle Timing (1/3 Duty Mode) 508 508 GRID1 3072 bit time GRID2 GRID3 511 508 1024 SEG1-37 Figure 6. Duty Cycle Timing (1/3 Duty Mode) (When digital dimming data is changed from 3F8H to 1FFH) ≠ ≠ 1016 bit time 511 bit time 12/13 ¡ Semiconductor MSC1230 PACKAGE DIMENSIONS (Unit : mm) QFP56-P-910-0.65-2K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.43 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 13/13