ONSEMI NB6L72

NB6L72
2.5V / 3.3V Differential 2 X 2
Crosspoint Switch with
LVPECL Outputs
Multi−Level Inputs w/ Internal Termination
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Description
The NB6L72 is a high−bandwidth fully differential 2 x 2 Crosspoint
Switch with internal source termination and LVPECL output structure,
optimized for low skew and minimal jitter. The differential inputs
incorporate internal 50 W termination resistors and will accept
LVPECL, CML, LVDS, LVCMOS, or LVTTL logic levels. The
SELECT inputs are single−ended and can be driven with
LVCMOS/LVTTL.
The differential LVPECL outputs provide 800 mV output swings
when externally terminated with a 50 W resistor to VCC – 2.0 V.
The device is offered in a small 3 mm x 3 mm 16−pin QFN package.
The NB6L72 is a member of the ECLinPS MAXt family of high
performance products.
Features
•
•
•
•
•
•
•
•
•
•
•
•
Maximum Input Clock Frequency > 3.0GHz
Maximum Input Data Rate > 5 Gb/s
425 ps Typical Propagation Delay
100 ps Typical Rise and Fall Times
0.5 ps maximum RMS Clock Jitter
LVPECL, CML or LVDS Input Compatible
Differential LVPECL Outputs, 780 mV Amplitude, Typical
Operating Range: VCC = 2.375 V to 3.63 V with GND = 0 V
Internal 50 W Input Termination Provided
Functionally Compatible with Existing 2.5 V/3.3 V LVEL, LVEP, EP,
and SG Devices
−40°C to +85°C Ambient Operating Temperature
These are Pb−Free Devices
© Semiconductor Components Industries, LLC, 2006
December, 2006 − Rev. 0
1
MARKING
DIAGRAM*
1
1
QFN−16
MN SUFFIX
CASE 485G
16
NB6L
72
ALYWG
G
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
Publication Order Number:
NB6L72/D
NB6L72
VTD0
D0
50 W
50 W
2
2
D0
2
D1
2
Q0
2
Q0
D1
50 W
VTD1
+
50 W
VCC
GND
2
SEL0
2
75 kW
2
2
Q1
2
SEL1
Q1
75 kW
Figure 1. Logic/Block Diagram
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2
NB6L72
SEL0
1
D0
2
GND
Q0
Q0
VCC
16
15
14
13
Exposed Pad (EP)
12
VCC
11
Q1
Table 1. INPUT/OUTPUT SELECT TRUTH TABLE
SEL0*
SEL1*
Q0
Q1
L
L
D0
D0
H
L
D1
D0
L
H
D0
D1
H
H
D1
D1
NB6L72
D0
3
10
Q1
VTD0
4
9
GND
*Defaults LOW when left open
5
VTD1
6
7
8
D1
D1
SEL1
Figure 2. Pin Configuration (Top View)
Table 2. PIN DESCRIPTION
Pin
Name
I/O
1
SEL0
LVTTL, LVCMOS
Input
Description
2
D0
LVPECL, CML,
LVDS, LVTTL,
LVCMOS, Input
Noninverted Differential Input. Note 1.
3
D0
LVPECL, CML,
LVDS, LVTTL,
LVCMOS, Input
Inverted Differential Input. Note 1.
4
VTD0
−
Internal 50 W Termination Pin. Note 1.
5
VTD1
−
Internal 50 W termination pin. Note 1.
6
D1
LVPECL, CML,
LVDS, LVTTL,
LVCMOS, Input
Noninverted Differential Input. Note 1.
7
D1
LVPECL, CML,
LVDS, LVTTL,
LVCMOS, Input
Inverted Differential Input. Note 1.
8
SEL1
LVTTL,LVCMOS
Input
Select Logic Input control that selects D0 or D1 to output Q1. See Table 1, Select Input
Function Table. Pin defaults LOW when left open
9
GND
−
10
Q1
LVPECL Output
Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC − 2.0 V.
11
Q1
LVPECL Output
Noninverted Differential Output. Typically Terminated with 50 W Resistor to VCC − 2.0 V.
12
VCC
−
Positive Supply Voltage
13
VCC
−
Positive Supply Voltage
14
Q0
LVPECL Output
Inverted Differential Reset Input. Typically Terminated with 50 W Resistor to VCC − 2.0 V.
15
Q0
LVPECL Output
Noninverted Differential Reset Input. Typically Terminated with 50 W Resistor to VCC − 2.0 V.
16
GND
−
Negative Supply Voltage
−
EP
−
The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for
improved heat transfer out of package. The exposed pad must be attached to a heat−sinking
conduit. The pad is not electrically connected to the die, but is recommended to be
electrically and thermally connected to GND on the PC board.
Select Logic Input control that selects D0 or D1 to output Q0. See Table 1, Select Input
Function Table. Pin defaults LOW when left open
Negative Supply Voltage
1. In the differential configuration when the input termination pin (VTDn, VTDn) are connected to a common termination voltage or left open,
and if no signal is applied on Dn/Dn input, then the device will be susceptible to self−oscillation.
2. All VCC and GND pins must be externally connected to a power supply for proper operation.
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NB6L72
Table 3. ATTRIBUTES
Characteristics
Value
ESD Protection
Human Body Model
Machine Model
Moisture Sensitivity
16−QFN
Flammability Rating
Oxygen Index: 28 to 34
> 2 kV
> 200 V
Level 1
UL 94 V−0 @ 0.125 in
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Rating
Unit
4.0
V
4.0
V
2.8
V
Static
Surge
45
80
mA
mA
Output Current (LVPECL Output)
Continuous
Surge
50
100
mA
mA
TA
Operating Temperature Range
QFN−16
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance
(Junction−to−Ambient) (Note 3)
0 lfpm
500 lfpm
QFN−16
QFN−16
42
35
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
(Note 3)
QFN−16
4
°C/W
Tsol
Wave Solder Pb−Free
265
°C
VCC
Positive Power Supply
GND = 0 V
VIO
Positive Input/Output Voltage
GND = 0 V
VINPP
Differential Input Voltage
IIN
Input Current Through RT (50 W Resistor)
IOUT
Condition 2
−0.5 v VIo v VCC + 0.5
|D − D|
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB6L72
Table 5. DC CHARACTERISTICS, Multi−Level Inputs VCC = 2.375 V to 3.63 V, GND = 0 V, TA = −40°C to +85°C
Characteristic
Symbol
Min
Typ
Max
Unit
40
60
80
mA
VCC = 3.3 V
VCC = 2.5 V
VCC − 1075
2225
1425
VCC − 950
2350
1550
VCC − 825
2475
1675
mV
VCC = 3.3 V
VCC = 2.5 V
VCC − 1825
1475
675
VCC − 1725
1575
775
VCC − 1625
1675
875
mV
1125
VCC − 75
mV
POWER SUPPLY CURRENT
ICC
Power Supply Current (Inputs and Outputs Open)
LVPECL OUTPUTS (Notes 4 and 5)
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (see Figures 4 and 5) (Note 6)
Vth
Input Threshold Reference Voltage Range (Note 7)
VIH
Single−ended Input HIGH Voltage
Vth + 75
VCC
mV
VIL
Single−ended Input LOW Voltage
GND
Vth − 75
mV
VISE
Single−ended Input Voltage Amplitude (VIH − VIL)
150
2800
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (see Figures 7 and 9)
VIHD
Differential Input HIGH Voltage
1200
VCC
mV
VILD
Differential Input LOW Voltage
GND
VCC − 150
mV
VID
Differential Input Voltage (Dn, Dn) (VIHD − VILD)
150
2800
mV
VCMR
Input Common Mode Range (Differential Configuration) (Note 9)
1125
VCC – 75
mV
IIH
Input HIGH Current Dn/Dn, (VTDn/VTDn Open)
−10
50
mA
IIL
Input LOW Current Dn/Dn, (VTDn/VTDn Open)
−50
10
mA
SINGLE−ENDED LVCMOS/LVTTL CONTROL INPUTS
VIH
Single−ended Input HIGH Voltage
2000
VCC
mV
VIL
Single−ended Input LOW Voltage
GND
800
mV
IIH
Input HIGH Current
−10
10
mA
IIL
Input LOW Current
−150
0
mA
60
W
TERMINATION RESISTORS
RTIN
Internal Input Termination Resistor
40
50
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. LVPECL outputs loaded with 50 W to VCC − 2.0 V for proper operation.
5. Input and output parameters vary 1:1 with VCC.
6. Vth, VIH, VIL,, and VISE parameters must be complied with simultaneously.
7. Vth is applied to the complementary input when operating in single−ended mode.
8. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously.
9. VCMR minimum varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential
input signal.
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NB6L72
Table 6. AC CHARACTERISTICS VCC = 2.375 V to 3.63 V, VEE = 0 V, or VCC = 0 V, VEE = −2.375 V to −3.63 V,
TA = −40°C to +85°C; (Note 10)
Symbol
Characteristic
Min
Typ
fin ≤ 1.5 GHz
fin ≤ 2.5 GHz
fin ≤ 3.0 GHz
520
380
320
800
650
500
Dn to Qn
SELn to Qn
325
425
525
ps
5
20
15
80
ps
50
60
%
0.2
0.3
0.5
1
ps
2800
mV
160
ps
VOUTPP
Output Voltage Amplitude (@ VINPPmin)
(Note 14) (See Figure 4)
tPLH,
tPHL
Propagation Delay (@0.5GHz)
tSKEW
Duty Cycle Skew (Note 11)
Within Device Skew
Device to Device Skew (Note 12)
tDC
Output Clock Duty Cycle
(Reference Duty Cycle = 50%)
fin ≤ 3.0 GHz
tJITTER
RMS Random Clock Jitter (Note 13)
fin = 2.5 GHz
fin = 3.0 GHz
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 14)
tr,tf
Output Rise/Fall Times @ 0.5 GHz (20% − 80%)
40
150
Q, Q
100
Max
Unit
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10. Measured by forcing VINPP (minimum) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC – 2.0 V. Input edge
rates 40 ps (20% − 80%).
11. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 0.5 GHz.
12. Device to device skew is measured between outputs under identical transition @ 0.5 GHz.
13. Additive RMS jitter with 50% duty cycle clock signal.
14. Input and output voltage swing is a single−ended measurement operating in differential mode.
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NB6L72
VTD
VCC
50 W
RC
RC
D
I
D
50 W
VTD
Figure 3. Input Structure
VCC
Vthmax
D
VIH
VIHmax
VILmax
Vth
VIH
Vth
VIL
Vth
VIL
Vthmin
D
Vth
Figure 5. Vth Diagram
D
D
D
D
Figure 6. Differential Inputs
Driven Differentially
VIHD(MAX)
VIHD
VILD
D
VINPP = VIH(D) − VIL(D)
D
VIHD
VID = VIHD − VILD
Q
VILD
VOUTPP = VOH(Q) − VOL(Q)
Q
VIHD(MIN)
GND
VID = |VIHD(D) − VILD(D)|
Figure 7. Differential Inputs Driven Differentially
VILD
VCMR
VILmin
GND
Figure 4. Differential Input Driven
Single−Ended
VCC
VIHmin
tPD
tPD
VILD(MIN)
Figure 8. VCMR Diagram
Figure 9. AC Reference Measurement
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NB6L72
VCC
VCC
VCC
NB6L72
ZO = 50 W
LVPECL
Driver
VCC
ZO = 50 W
D
50 W
VT = VCC − 2 V
ZO = 50 W
LVDS
Driver
50 W
NB6L72
D
50 W
VT = Open
ZO = 50 W
D
50 W
D
GND
GND
GND
GND
Figure 10. LVPECL Interface
Figure 11. LVDS Interface
VCC
VCC
NB6L72
ZO = 50 W
CML
Driver
D
50 W
VT = VCC
ZO = 50 W
50 W
D
GND
GND
Figure 12. Standard 50 W Load CML Interface
VCC
VCC
ZO = 50 W
Differential
Driver
VCC
VCC
NB6L72
ZO = 50 W
D
50 W
VT = VREFAC*
ZO = 50 W
Single−Ended
Driver
50 W
D
GND
Figure 13. Capacitor−Coupled
Differential Interface
(VT Connected to VREFAC)
NB6L72
D
50 W
VT = VREFAC*
50 W
D
GND
GND
Figure 14. Capacitor−Coupled
Single−Ended Interface
(VT Connected to VREFAC)
*VREFAC bypassed to ground with a 0.01 mF capacitor
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(Open)
GND
NB6L72
Zo = 50 W
Q
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
VOUTPP OUTPUT VOLTAGE AMPLITUDE (mV)
(TYPICAL)
Figure 15. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
800
700
600
500
400
300
200
100
0
0
1
2
3
fout, CLOCK OUTPUT FREQUENCY (GHz)
Figure 16. Output Voltage Amplitude (VOUTPP) versus Output
Frequency at Ambient Temperature (Typical)
ORDERING INFORMATION
Package
Shipping †
NB6L72MNG
QFN−16
(Pb−free)
123 Units / Rail
NB6L72MNR2G
QFN−16
(Pb−free)
3000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NB6L72
PACKAGE DIMENSIONS
D
PIN 1
LOCATION
A
B
ÇÇ
ÇÇ
0.15 C
16 PIN QFN
MN SUFFIX
CASE 485G−01
ISSUE C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM
MINIMUM SPACING BETWEEN LEAD TIP
AND FLAG
E
TOP VIEW
0.15 C
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
(A3)
0.10 C
A
16 X
0.08 C
SIDE VIEW
SEATING
PLANE
A1
C
SOLDERING FOOTPRINT*
D2
16X
L
5
NOTE 5
e
0.575
0.022
9
E2
K
12
1
16
16X
3.25
0.128
0.30
0.012
EXPOSED PAD
e
13
1.50
0.059
3.25
0.128
b
0.10 C A B
0.05 C
EXPOSED PAD
8
4
16X
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.18
0.30
3.00 BSC
1.65
1.85
3.00 BSC
1.65
1.85
0.50 BSC
0.18 TYP
0.30
0.50
BOTTOM VIEW
NOTE 3
0.50
0.02
0.30
0.012
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ECLinPS MAX is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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Phone: 81−3−5773−3850
Email: [email protected]
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Order Literature: http://www.onsemi.com/litorder
For additional information, please contact your
local Sales Representative.
NB6L72/D