NCP1217 Enhanced PWM Current−Mode Controller for High−Power Universal Off−Line Supplies Housed in an SO−8 or PDIP−7 package, the NCP1217 represents the enhanced version of the NCP1203−based controllers. Thanks to its high drive capability, NCP1217 drives large gate−charge MOSFETs, which together with internal ramp compensation and built−in overvoltage protection, ease the design of modern AC/DC adapters. NCP1217 offers a true alternative to UC384X−based designs. With an internal structure operating at different fixed frequencies (65–100–133 kHz), the controller features a high−voltage start−up FET, which ensures a clean and loss less start−up sequence. Its current−mode control topology provides an excellent input audio− susceptibility and inherent pulse−by−pulse control. Internal ramp compensation easily prevents subharmonic oscillations from taking place in continuous conduction mode designs. When the current setpoint falls below a given value, e.g. the output power demand diminishes, the IC automatically enters the so−called skip cycle mode and provides excellent efficiency at light loads. Because this occurs at a user adjustable low peak current, no acoustic noise takes place. The NCP1217 features two efficient protective circuitries: 1) In presence of an overcurrent condition, the output pulses are disabled and the device enters a safe burst mode, trying to restart. Once the default has gone, the device auto−recovers. 2) If an external signal (e.g. a temperature sensor) pulls pin1 above 3.2 V, output pulses are immediately stopped and the NCP1217 stays latched in this position. Reset occurs when the VCC collapses to ground, e.g. the user unplugs the power supply. http://onsemi.com MINIATURE PWM CONTROLLER FOR HIGH POWER AC/DC WALL ADAPTERS AND OFFLINE BATTERY CHARGERS MARKING DIAGRAMS 8 SO−8 D SUFFIX CASE 751 8 17Dyy ALYW 1 1 PDIP−7 P SUFFIX CASE 626B P1217Pxxx AWL YYWW 8 1 1 Features • • • • • • • • • • • Current−Mode with Adjustable Skip−Cycle Capability Built−in Internal Ramp Compensation Auto−Recovery Internal Output Short−Circuit Protection Full Latch−Off if Adjustment Pin is Brought High Extremely Low No−Load Standby Power Internal Temperature Shutdown 500 mA Peak Current Capability Fixed Frequency Versions at 65 kHz, 100 kHz and 133 kHz Direct Optocoupler Connection Internal Leading Edge Blanking SPICE Models Available for TRANsient and AC Analysis Typical Applications • • • • High Power AC/DC Converters for TVs, Set−Top Boxes, etc. Offline Adapters for Notebooks Telecom DC−DC Converters All Power Supplies xxx yy = Device Code: 065, 100 or 133 = Device Code: 06 for 65 10 for 100 13 for 133 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week PIN CONNECTIONS Adj 1 8 HV FB 2 7 NC CS 3 6 VCC Gnd 4 5 Drv (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 15 of this data sheet. Semiconductor Components Industries, LLC, 2003 September, 2003 − Rev. 0 1 Publication Order Number: NCP1217/D NCP1217 See Application Section VOUT + Aux. + NCP1217 Adj 1 FB 2 EMI FILTER Gnd Drv 4 8 7 CS VCC 3 UNIVERSAL INPUT HV 6 5 Ramp Adjustment + Figure 1. Typical Application Example ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PIN FUNCTION DESCRIPTION Pin No. Pin Name Function Description 1 Adj Adjust the skipping peak current This pin lets you adjust the level at which the cycle skipping process takes place. Shorting this pin to ground permanently disables the skip cycle feature. By bringing this pin above 3.1 V, you permanently shut off the device. 2 FB Sets the peak current setpoint By connecting an optocoupler to this pin, the peak current setpoint is adjusted accordingly to the output power demand. 3 CS Current sense input This pin senses the primary current and routes it to the internal comparator via an L.E.B. By inserting a resistor in series with the pin, you control the amount of ramp compensation you need. 4 Gnd The IC ground 5 Drv Driving pulses The driver’s output to an external MOSFET. 6 VCC Supplies the IC This pin is connected to an external bulk capacitor of typically 22 F. 7 NC 8 HV − − Ensures a clean and lossless start−up sequence This unconnected pin ensures adequate creepage distance. Connected to the high−voltage rail, this pin injects a constant current into the VCC capacitor during the start−up sequence. http://onsemi.com 2 NCP1217 Latch−Off Comparator + − Adj 1 + − HV 8 Set 3.1 V HV Current Source UVLO Reset Latch 80 k FB 1.1 V 2 Skip Cycle Comparator + − NC 7 UVLO High and Low Internal VCC 24 k Reset Current Sense 250 ns L.E.B. 3 65−100−133 kHz Clock Q Flip−Flop DCmax = 74% Set VCC Q Overload Management Reset 6 19 k Ramp Compensation 20 k Drv Ground 4 + − 57 k + − VREF 25 k ±500 mA 1V 5 Figure 2. Internal Circuit Architecture ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ MAXIMUM RATINGS Rating Symbol Value Unit VCC 16 V − −0.3 to 10 V Maximum Voltage on Pin 8 (HV), Pin 6 (VCC) Decoupled to Ground with 10 F VHV 500 V Maximum Voltage on Pin 8 (HV), Pin 6 (VCC) Grounded VHV 450 V − 5.0 mA Thermal Resistance, Junction−to−Case RθJ−C 57 °C/W Thermal Resistance, Junction−to−Air, PDIP−7 Version Thermal Resistance, Junction−to−Air, SO−8 Version RθJ−A RθJ−A 100 178 °C/W Maximum Junction Temperature Power Supply Voltage Power Supply Voltage on All Other Pins Except Pin 8 (HV), Pin 6 (VCC) and Pin 5 (Drv) Maximum Current into All Pins Except VCC (6) and HV (8) when 10 V ESD Diodes are Activated TJMAX 150 °C Temperature Shutdown − 155 °C Hysteresis in Shutdown − 30 °C Storage Temperature Range − −60 to +150 °C ESD Capability, HBM Model (All Pins Except VCC and HV) − 2.0 kV ESD Capability, Machine Model − 200 V http://onsemi.com 3 NCP1217 ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = 0°C to +125°C, Max TJ = 150°C, VCC= 11 V unless otherwise noted.) Characteristic Pin Symbol Min Typ Max Unit SUPPLY SECTION (All frequency versions, unless otherwise noted) Turn−On Threshold Level, VCC Going Up 6 VCCON 11.8 12.8 13.8 V Minimum Operating Voltage After Turn−On 6 VCCmin 6.9 7.6 8.3 V VCC Decreasing Level at which the Latch−Off Phase Ends 6 VCClatch − 5.6 − V Internal IC Consumption, No Output Load on Pin 5, FSW = 65 kHz 6 ICC1 − 960 1110 (Note 1) A Internal IC Consumption, No Output Load on Pin 5, FSW = 100 kHz 6 ICC1 − 1020 1180 (Note 1) A Internal IC Consumption, No Output Load on Pin 5, FSW = 133 kHz 6 ICC1 − 1060 1200 (Note 1) A Internal IC Consumption, 1.0 nF Output Load on Pin 5, FSW = 65 kHz 6 ICC2 − 1.7 2.0 (Note 1) mA Internal IC Consumption, 1.0 nF Output Load on Pin 5, FSW = 100 kHz 6 ICC2 − 2.1 2.4 (Note 1) mA Internal IC Consumption, 1.0 nF Output Load on Pin 5, FSW = 133 kHz 6 ICC2 − 2.4 2.9 (Note 1) mA Internal IC Consumption, Latch−Off Phase, VCC = 6.0 V 6 ICC3 − 230 − A High−Voltage Current Source, VCC = 10 V 8 IC1 3.5 (Note 2) 6.0 7.8 mA High−Voltage Current Source, VCC = 0 8 IC2 − 7.0 − mA Output Voltage Rise−Time @ CL = 1.0 nF, 10−90% of a 12 V Output Signal 5 Tr − 60 − ns Output Voltage Fall−Time @ CL = 1.0 nF, 10−90% of a 12 V Output Signal 5 Tf − 20 − ns Source Resistance 5 ROH 15 20 35 Sink Resistance 5 ROL 5.0 10 18 INTERNAL START−UP CURRENT SOURCE (TJ 0°C) DRIVE OUTPUT CURRENT COMPARATOR (Pin 5 Unloaded) Input Bias Current @ 1.0 V Input Level on Pin 3 3 IIB − 0.02 − A Maximum Internal Current Setpoint 3 ILimit 0.9 1.0 1.1 V Default Internal Current Setpoint for Skip Cycle Operation 3 ILskip − 330 − mV Propagation Delay from Current Detection to Gate OFF State 3 TDEL − 90 150 ns Leading Edge Blanking Duration 3 TLEB − 250 − ns Oscillation Frequency, 65 kHz Version − fOSC 58.5 65 71.5 kHz Oscillation Frequency, 100 kHz Version − fOSC 90 100 110 kHz Oscillation Frequency, 133 kHz Version − fOSC 120 133 146 kHz Maximum Duty−Cycle, NCP1217 − Dmax 69 74 80 % INTERNAL OSCILLATOR (VCC = 11 V, Pin 5 Loaded by 1.0 k) 1. Maximum Value @ TJ = 0°C. 2. Minimum Value @ TJ = 125°C. http://onsemi.com 4 NCP1217 ELECTRICAL CHARACTERISTICS (continued) (For typical values TJ = 25°C, for min/max values TJ = 0°C to +125°C, Max TJ = 150°C, VCC= 11 V unless otherwise noted.) Characteristic Pin Symbol Min Typ Max Unit FEEDBACK SECTION (VCC = 11 V, Pin 5 Loaded by 1.0 k) Internal Pull−Up Resistor 2 Rup − 19 − k Pin 2 (FB) to Internal Current Setpoint Division Ratio − Iratio − 3.3 − − Default Skip Mode Level 1 Vskip 0.93 1.1 1.26 V Pin 1 Internal Output Impedance 1 Zout − 27 − kΩ Internal Ramp Level @ 25°C (Note 3) 3 Vramp 2.6 2.9 3.2 V Internal Ramp Resistance to CS Pin 3 Rramp − 19 − kΩ 1 Vlatch 2.69 3.10 3.42 V SKIP CYCLE GENERATION INTERNAL RAMP COMPENSATION ADJUSTMENT LATCH−OFF LEVEL Latching Level 3. A 1.0 M resistor is connected to the ground for the measurement. 80 14.0 70 13.5 60 VCCOFF, (V) HV PIN LEAKAGE CURRENT @ 500V (µA) TYPICAL CHARACTERISTICS 50 40 30 13.0 12.5 12.0 20 11.5 10 0 −25 0 25 50 75 11.0 −25 125 100 0 50 75 100 TEMPERATURE (°C) Figure 3. High Voltage Pin Leakage Current vs. Temperature Figure 4. VCCOFF vs. Temperature 9.0 125 1200 1100 8.5 100 kHz 133 kHz 1000 ICC1, (µA) VCCMIN, (V) 25 TEMPERATURE (°C) 8.0 900 65 kHz 800 700 7.5 600 7.0 −25 0 25 50 75 100 500 −25 125 TEMPERATURE (°C) 0 25 50 75 100 TEMPERATURE (°C) Figure 5. VCCMIN vs. Temperature Figure 6. ICC1 (@ VCC=11V) vs. Temperature http://onsemi.com 5 125 NCP1217 TYPICAL CHARACTERISTICS (continued) 2.80 150 2.60 133 kHz 133 kHz 130 2.40 100 kHz FOSC, (kHz) ICC2, (mA) 2.20 110 2.00 1.80 65 kHz 100 kHz 90 1.60 1.40 65 kHz 70 1.20 1.00 −25 0 25 50 75 100 50 −25 125 0 25 50 75 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 7. ICC2 vs. Temperature Figure 8. Switching Frequency vs. Temperature 5.90 125 400 5.80 ICC3, (µA) VCClatch, (V) 350 5.70 5.60 300 5.50 250 5.40 5.30 −25 0 25 50 75 100 200 −25 125 100 Figure 10. ICC3 vs. Temperature 125 1.10 CURRENT SENSE LIMIT, (V) DRIVER RESISTANCE, () 75 Figure 9. VCClatch vs. Temperature Source 15 Sink 5 0 −25 50 TEMPERATURE (°C) 25 10 25 TEMPERATURE (°C) 30 20 0 0 25 50 75 100 1.05 1.00 0.95 0.90 −25 125 TEMPERATURE (°C) 0 25 50 75 100 TEMPERATURE (°C) Figure 11. Drive Sink and Source Resistance vs. Temperature Figure 12. Current Sense Limit vs. Temperature http://onsemi.com 6 125 NCP1217 TYPICAL CHARACTERISTICS (continued) 1.20 80 78 DUTY CYCLE, (%) Vskip, (V) 1.15 1.10 1.05 76 74 72 1.00 −25 0 25 50 75 100 70 −25 125 0 TEMPERATURE (°C) 25 50 75 100 125 TEMPERATURE (°C) Figure 13. Vskip vs. Temperature Figure 14. Max Duty−Cycle vs. Temperature 8.0 3.10 3.05 7.0 2.95 IC1, (mA) Vramp, (V) 3.00 2.90 2.85 2.80 6.0 5.0 4.0 2.75 2.70 −25 0 25 50 75 100 3.0 −25 125 0 25 50 75 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 15. Vramp vs. Temperature Figure 16. High Voltage Current Source (@ Vcc=10V) vs. Temperature http://onsemi.com 7 125 NCP1217 APPLICATION INFORMATION Introduction The NCP1217 implements a standard current mode architecture where the switch−off event is dictated by the peak current setpoint. This component represents the ideal candidate where low part−count is the key parameter, particularly in low−cost AC/DC adapters, TV power supplies, etc. Due to its high−performance High−Voltage technology, the NCP1217 incorporates all the necessary components normally needed in UC384X based supplies: timing components, feedback devices, low−pass filter and start−up device but also enhances the original component by offering: 1) an externally triggerable latch−off 2) ramp compensation and finally, 3) short−circuit protection. Due to its high−voltage current source, ON Semiconductor’s NCP1217 does not need an external start−up resistance but supplies the start−up current directly from the high−voltage rail. On the other hand, more and more applications are requiring low no−load standby power, e.g. for AC/DC adapters, VCRs, etc. UC384X series have a lot of difficulty to reduce the switching losses at low power levels. NCP1217 elegantly solves this problem by skipping unwanted switching cycles at a user−adjustable power level. By ensuring that skip cycles take place at low peak current, the device ensures quiet, noise−free operation: Current−Mode Operation: As the UC384X series, the NCP1217 features a well−known current mode control architecture which provides superior input audio− susceptibility compared to traditional voltage−mode controllers. Primary current pulse−by−pulse checking together with a fast over current comparator offers greater security in the event of a difficult fault condition, e.g. a saturating transformer. Ramp Compensation: By inserting a resistor between the current−sense (CS) pin and the actual sense resistor, it becomes possible to inject a given amount of ramp compensation since the internal saw tooth clock is routed to the CS pin. Subharmonic oscillations in Continuous Conduction Mode (CCM) can thus be compensated via a single resistor. Adjustable Skip Cycle Level: By offering the ability to tailor the level at which the skip cycle takes place, the designer can make sure that the skip operation only occurs at low peak current. This point guarantees a noise−free operation with cheap transformers. Skip cycle offers a proven mean to reduce the standby power in no or light loads situations. Wide Switching−Frequency Offer: Three different options are available: 65 kHz–100 kHz–133 kHz. Depending on the application, the designer can pick up the right device to help reducing magnetics or improve the EMI signature before reaching the 150 kHz starting point. Over Current Protection (OCP): By continuously monitoring the FB line activity, NCP1217 enters burst mode as soon as the power supply undergoes an overload. The device enters a safe low power operation, which prevents from any lethal thermal runaway. As soon as the default disappears, the power supply resumes operation. Unlike other controllers, overload detection is performed independently of any auxiliary winding level. In presence of a bad coupling between both power and auxiliary windings, the short circuit detection can be severely affected. The DSS naturally shields you against these troubles. Over Voltage Protection (OVP): If pin1 is brought to a level higher than the internal 3.2 V reference voltage, the controller is permanently shut down until the user cycles the VCC OFF and ON again. This allows the building of efficient and low−cost over voltage protection circuits. Wide Duty−Cycle Operation: Wide mains operation requires a large duty−cycle excursion. The NCP1217 can go up to 74% typically. Low Standby−Power: If SMPS naturally exhibit a good efficiency at nominal load, they begin to be less efficient when the output power demand diminishes. By skipping unneeded switching cycles, the NCP1217 drastically reduces the power wasted during light load conditions. In no−load conditions, the NPC1217 allows the total standby power to easily reach next International Energy Agency (IEA) recommendations. No Acoustic Noise While Operating: Instead of skipping cycles at high peak currents, the NCP1217 waits until the peak current demand falls below a user−adjustable 1/3 of the maximum limit. As a result, cycle skipping can take place without having a singing transformer … You can thus select cheap magnetic components free of noise problems. External MOSFET Connection: By leaving the external MOSFET external to the IC, you can select avalanche proof devices, which in certain cases (e.g. low output powers), let you work without an active clamping network. Also, by controlling the MOSFET gate signal flow, you have an option to slow down the device commutation, therefore reducing the amount of ElectroMagnetic Interference (EMI). SPICE Model: A dedicated model to run transient cycle−by−cycle simulations is available but also an averaged version to help you closing the loop. Ready−to−use templates can be downloaded in OrCAD’s Pspice and INTUSOFT’s IsSpice from ON Semiconductor web site, NCP1217 related section. http://onsemi.com 8 NCP1217 Start−Up Sequence 12.8 V), the current source turns off and no longer wastes any power. At this time, the VCC capacitor only supplies the controller and the auxiliary supply is supposed to take over before VCC collapses below VCCmin. Figure 17 shows the internal arrangement of this structure. When the power supply is first powered from the mains outlet, the internal current source (typically 7.0 mA) is biased and charges up the VCC capacitor. When the voltage on this VCC capacitor reaches the VCCON level (typically 8 12.8 V/5.6 V + − HV 6 mA or 0 6 CVCC Aux 4 Figure 17. The Current Source Brings VCC Above 12.8 V and then Turns Off level, preventing a bias current to circulate in the optocoupler LED. As a result, the auxiliary voltage also decreases because it also operates in Flyback and thus duplicates the output voltage, providing the leakage inductance between windings is kept low. To account for this situation and properly protect the power supply, NCP1217 hosts a dedicated overload detection circuitry. Once activated, this circuitry imposes to deliver pulses in a burst manner with a low duty−cycle. The system auto−recovers when the fault condition disappears. During the start−up phase, the peak current is pushed to the maximum until the output voltage reaches its target and the feedback loop takes over. The auxiliary voltage takes place after a few switching cycles and self−supplies the IC. In presence of a short circuit on the output, the auxiliary voltage will go down until it crosses the undervoltage lockout level of typically 7.6 V. When this happens, NCP1217 immediately stops the switching pulses and unbiases all unnecessary logical blocks. The overall consumption drops, while keeping the gate grounded, and the VCC slowly falls down. As soon as VCC reaches typically 5.6 V, the start−up source turns−on again and a new start−up sequence occurs, bringing VCC toward 12.8 V as an attempt to restart. If the default has gone, then the power supply normally restarts. If not, a new protective burst is initiated, shielding the SMPS from any runaway. Figure 19 portrays the typical operating signals in short circuit. Once the power supply has started, the VCC shall be constrained below 16 V, which is the maximum rating on pin 6. Figure 18 portrays a typical start−up sequence with a VCC regulated at 12.5 V. 13.5 12.5 REGULATION 12.8 V 11.5 10.5 9.5 3.00 M 8.00 M 13.0 M 18.0 M 23.0 M t, TIME (sec) Figure 18. A Typical Start−Up Sequence for the NCP1217 Overload Operation In applications where the output current is purposely not controlled (e.g. wall adapters delivering raw DC level), it is interesting to implement a true short−circuit protection. A short−circuit actually forces the output voltage to be at a low http://onsemi.com 9 NCP1217 VCCON = 12.8 V VCCmin = 7.6 V VCC VCClatch = 5.6 V DRIVING PULSES Figure 19. Typical Waveforms in Short Circuit Conditions Calculating the VCC Capacitor The The VCC capacitor can be calculated knowing the IC consumption as soon as VCC reaches 12.8 V. Suppose that a NCP1217P065 is used and drives a MOSFET with a 30 nC total gate charge (Qg). The total average current is thus made of ICC1 (750 A) plus the driver current, Fsw * Qg 1.95 mA. The total current is therefore 2.7 mA. The V available to fully start−up the circuit (e.g. never reach the 8.2 V VCCmin during power on) is 13.7−8.2 5.5 V best case or 4.9 V worse case (11.9−7.0) . We have a capacitor that then needs to supply the NCP1217 with 2.7 mA during a given time until the auxiliary supply takes over. Suppose that this time was measured at around theoretical power transfer is therefore: 1 · Lp · Ip2 · Fsw 4.1 W. If this IC enters skip cycle 2 mode with a bunch length of 10 ms over a recurrent period of 100 ms, then the total power transfer is: 4.1 * 0.1 410 mW. To better understand how this skip cycle mode takes place, a look at the operation mode versus the FB level immediately gives the necessary insight. FB 4.2 V, FB Pin Open 3.2 V, Upper Dynamic Range 15 ms. CVCC is calculated using the equation C t · i or V C 8.3 F. Select a 22 F/25 V and this will fit. NORMAL CURRENT MODE OPERATION Skipping Cycle Mode SKIP CYCLE OPERATION IP(min) = 333 mV/RSENSE The NCP1217 automatically skips switching cycles when the output power demand drops below a given level. This is accomplished by monitoring the FB pin. In normal operation, pin 2 imposes a peak current accordingly to the load value. If the load demand decreases, the internal loop asks for less peak current. When this setpoint reaches a determined level (Vpin 1), the IC prevents the current from decreasing further down and starts to blank the output pulses: the IC enters the so−called skip cycle mode, also named controlled burst operation. The power transfer now depends upon the width of the pulse bunches (Figure 21). Suppose we have the following component values: Lp, primary inductance = 350 H Fsw, switching frequency = 65 kHz Ip skip = 600 mA (or 333 mV/Rsense) 1V Time Figure 20. When FB is above the skip cycle threshold (1.0 V by default), the peak current cannot exceed 1.0 V/Rsense. When the IC enters the skip cycle mode, the peak current cannot go below Vpin1/3.3. The user still has the flexibility to alter this 1.0 V by either shunting pin 1 to ground through a resistor or raising it through a resistor up to the desired level. In this later case, care must be taken to keep sufficient margin between this pin 1 adjustment level and the latch−off level. Grounding pin 1 permanently invalidates the skip cycle operation. http://onsemi.com 10 NCP1217 Power P1 Power P2 Power P3 Figure 21. Output Pulses at Various Power Levels (X = 5.0 s/div) P1 P2 P3 MAX PEAK CURRENT 300 M SKIP CYCLE CURRENT LIMIT 200 M 100 M 0 315.40 U 882.70 U 1.450 M 2.017 M 2.585 M Figure 22. The Skip Cycle Takes Place at Low Peak Currents which Guarantees Noise−Free Operation Sufficient margin shall be kept between normal pin1 level and the latch−off point in order to avoid false triggering. Ramp Compensation Continuous Conduction Mode (CCM) with a duty−cycle greater than 50%. To lower the current loop gain, one usually injects between 50 and 100% of the inductor down−slope. Figure 23 depicts how internally the ramp is generated. Ramp compensation is a known mean to cure subharmonic oscillations. These oscillations take place at half the switching frequency and occur only during http://onsemi.com 11 NCP1217 Latching Off the NCP1217 Duty Cycle Typ = 74% Total latched shutdown can easily be implemented through a simple PNP bipolar transistor as depicted by Figure 24. When OFF, Q1 is transparent to the operation. When forward biased, the transistor pulls the ADJ pin toward VCC and permanently latches−off the IC as soon Vadj goes above the latching level (typical 3.1 V). Figure 24 shows how to wire the bipolar transistor to activate the latch−off. A typical candidate for Q1 could be an MMBT3906 from ON Semiconductor. 2.9 V 0V 19 k Rcomp + − L.E.B. CS Rsense VCC From Setpoint Figure 23. Inserting a Resistor in Series with the Current Sense Information Brings Ramp Compensation Off Q1 In the NCP1217, the ramp features a swing of 2.9 V with a duty cycle max at 74%. Over a 65 kHz frequency, for instance, it corresponds to a 254 mV/s ramp. In our FLYBACK design, let’s suppose that our primary inductance Lp is 350 H, delivering 12 V with a Np:Ns ratio of 1:0.1. The OFF time primary current slope is thus given by: (Vout Vf) · Lp Np Ns Rlimit 371 mAs or 37 mVs when projected over an Rsense of 0.1 , for instance. If we select 75% of the downslope as the required amount of ramp compensation, then we shall inject 27 mV/s. Our internal compensation being of 254 mV/s, the divider ratio (divratio) between Rcomp and the 19 k is 0.106. A few lines of algebra to determine Rcomp: 1 8 2 7 3 6 4 5 Figure 24. A Simple Bipolar Transistor Totally Disables the IC 19 k · divratio 2.26 k. (1−divratio) VCC The start−up current source keeps the device latched until reset occurs. VCCON = 12.8 V VCCmin = 7.6 V VCCLATCH = 5.6 V CVCC Reset level Time Drv Driver Pulses Latched−off Time Adj Default adj level Fault brings adj above latching level Time Figure 25. When Vadj is Pulled Above 3.1 V, NCP1217 Permanently Latches−Off the Output Pulses http://onsemi.com 12 NCP1217 output pulses are disabled as long as FB is pulled below pin 1. As soon as FB is relaxed, the IC resumes its operation. Figure 27 depicts the application example. In normal operation, the Adj pin level is kept at a fixed level, the default one or lower. As soon as some external signal pulls this Adj pin level above 3.1 V typical, the output pulses are permanently disabled. Care must be taken to limit the injected current into pin 1 to less than 2.0 mA, e.g. through a series resistor of 5.6 k with a 10 V VCC. The start−up switch is activated every time VCC reaches 5.6 V and maintains a VCC voltage ramping up and down between 5.6 V and 12.8 V. Reset occurs when VCC falls below 5.6 V, e.g. when the user cycle the SMPS down. Figure 26 illustrates the operation. Adding a zener diode from Q1 base to ground makes a cheap OVP, protecting the supply from any lethal open−loop operation. If a thermistor (NTC) is added in parallel with the zener−diode, overtemperature protection is also ensured. ON/OFF Q1 1 8 2 7 3 6 4 5 Figure 27. Another Way of Shutting Down the IC Without a Definitive Latch−Off State Vaux Protecting the Controller Against Negative Spikes T OVP 1 8 2 7 3 6 4 5 As with any controller built upon a CMOS technology, it is the designer’s duty to avoid the presence of negative spikes on sensitive pins. Negative signals have the bad habit to forward bias the controller substrate and induce erratic behaviors. Sometimes, the injection can be so strong that internal parasitic SCRs are triggered, engendering irremediable damages to the IC if a low impedance path is offered between VCC and GND. If the current sense pin is often the seat of such spurious signals, the high−voltage pin can also be the source of problems in certain circumstances. During the turn−off sequence, e.g. when the user unplugs the power supply, the controller is still fed by its VCC capacitor and keeps activating the MOSFET ON and OFF with a peak current limited by Rsense. Unfortunately, if the quality coefficient Q of the resonating network formed by Lp and Cbulk is low (e.g. the MOSFET Rdson + Rsense are small), conditions are met to make the circuit resonate and thus negatively bias the controller. Since we are talking about ms pulses, the amount of injected charge (Q = I * t) immediately latches the controller that brutally discharges its VCC capacitor. If this VCC capacitor is of sufficient value, its stored energy damages the controller. Figure 28 depicts a typical negative shot occurring on the HV pin where the brutal VCC discharge testifies for latch−up. 16 V CVCC Laux Figure 26. A Thermistor and a Zener Diode Offer Both OVP and Overtemperature Latched−Off Protection Non−Latching Shutdown In some cases, it might be desirable to shut off the part temporarily and authorize its restart once the default has disappeared. This option can easily be accomplished through a single NPN bipolar transistor wired between FB and ground. By pulling FB below the Adj pin 1 level, the http://onsemi.com 13 NCP1217 Vcc 5 V/DIV Vlatch 1 V/DIV Time 10 ms/DIV Figure 28. A Negative Spike Takes Place on the Bulk Capacitor at the Switch−Off Sequence Another option (Figure 30) consists in wiring a diode from VCC to the bulk capacitor to force VCC to reach VCCON sooner and thus stops the switching activity before the bulk capacitor gets deeply discharged. For security reasons, two diodes can be connected in series. Simple and inexpensive cures exist to prevent from internal parasitic SCR activation. One of them consists in inserting a resistor in series with the high−voltage pin to keep the negative current to the lowest when the bulk becomes negative (Figure 29). Please note that the negative spike is clamped to (−2*Vf) thanks to the diode bridge. Also, the power dissipation of this resistor is extremely small since it only heats up during the startup sequence. 3 Rbulk 4.7 k + Cbulk 1 8 2 7 3 6 4 5 + 2 Cbulk 1 + CVCC Figure 29. A simple resistor in series avoids any latch−up in the controller . . . 1 8 2 7 3 6 4 5 3 D3 1N4007 1 + CVCC Figure 30. . . . or one diode forces VCC to reach VCCON sooner. http://onsemi.com 14 NCP1217 ORDERING INFORMATION Device Version Marking Package Shipping NCP1217P065 65 kHz P1217P065 PDIP−7 50 Units/Rail 2500 Units/Reel NCP1217D065 65 kHz 17D06 SO−8 NCP1217P100 100 kHz P1217P100 PDIP−7 50 Units/Rail NCP1217D100 100 kHz 17D10 SO−8 2500 Units/Reel NCP1217P133 133 kHz P1217P133 PDIP−7 50 Units/Rail NCP1217D133 133 kHz 17D13 SO−8 2500 Units/Reel http://onsemi.com 15 NCP1217 PACKAGE DIMENSIONS SO−8 D SUFFIX CASE 751−07 ISSUE AA NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. −X− A 8 5 0.25 (0.010) S B 1 M Y M 4 K −Y− G C N X 45 SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X S http://onsemi.com 16 J DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0 8 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 8 0.010 0.020 0.228 0.244 NCP1217 PACKAGE DIMENSIONS PDIP−7 P SUFFIX CASE 626B−01 ISSUE A J 8 5 M B 1 L NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 5. DIMENSIONS A AND B ARE DATUMS. 4 DIM A B C D F G H J K L M N F A NOTE 2 C −T− N SEATING PLANE H D K G 0.13 (0.005) M T A M B M http://onsemi.com 17 MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC −−− 10 ° 0.76 1.01 NCP1217 The product described herein (NCP1217), may be covered by the following U.S. patent: US 6,385,060. There may be other patents pending. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 http://onsemi.com 18 For additional information, please contact your local Sales Representative. NCP1217/D