ONSEMI NCP802SAN1T1

NCP802
Highly Integrated Lithium
Battery Protection Circuit
for One Cell Battery Packs
The NCP802 resides in a lithium battery pack where the battery cell
continuously powers it. This circuit senses cell voltage, charge
current, and discharge current, and correspondingly controls the state
of two, N−channel MOSFET switches. These switches reside in series
with the negative terminal of the cell and the negative terminal of the
battery pack. During a fault condition, the NCP802 open circuits the
pack by turning off one of these MOSFET switches, which
disconnects the current path. Internal delay circuitry minimizes
external component count.
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MARKING
DIAGRAMS
SOT23−6
SN SUFFIX
CASE 1262
6
1
Features
XXxx
• Highly Accurate Overvoltage Detector
•
•
•
•
•
•
•
25 mV at Room Temperature
30 mV from −5 to 55°C
Fault Detection Thresholds
Overvoltage Threshold:
SN1/SAN1 = 4.35 V, SAN5 = 4.275 V, SAN6 = 4.28 V
Undervoltage Threshold:
SN1/SAN1 = 2.4 V, SAN5/6 = 2.3 V
Discharge Current Threshold:
SN1/SAN1/SAN6 = 0.2 V, SAN5 = 0.1 V
Charge Current Threshold: 0.1 V
Internal Output Delays
Overvoltage Output Delay:
SN1/SAN1/SAN6 = 250 ms, SAN5 = 1 ms
Undervoltage Output Delay: 20 ms
Discharge Current Output Delay:
SN1/SAN1/SAN6 = 12 ms, SAN5 = 6 ms
Charge Current Output Delay:
SN1/SAN1/SAN6 = 16 ms, SAN5 = 8 ms
Absolute Maximum Rating of 28 V for the Charger Input
Low Quiescent Current
Normal Operating Current: 3.0 A
Standby Current when Cells are Discharged: 0.1 A
Zero Volt Charging
Available in a Low Profile Surface Mount Package
Pb−Free Package is Available*
XX
xx
SON−6
SAN SUFFIX
CASE 494
6
1
XX = Specific Device Code
xx = Date Code
PIN CONNECTIONS
DO 1
6
Gnd
P− 2
5
Vcell
CO 3
4
DS
SOT23−6
(Top View)
DO
1
6
P−
Vcell
2
5
CO
Gnd
3
4
DS
SON−6
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 20 of this data sheet.
*For additional information on our Pb−Free
strategy and soldering details, please download
the ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
 Semiconductor Components Industries, LLC, 2004
September, 2004 − Rev. 10
1
Publication Order Number:
NCP802/D
NCP802
Vcell
Gnd
NCP802
DO
CO
P−
Figure 1. Typical One Cell Lithium Ion Battery Pack
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2
NCP802
4 DS
5 Vcell
Counter
Oscillator
Logic
Circuit
Level
Shift
VD1
Short
Detector
Delay
VD4
Logic
Circuit
VD2
VD3
6
1
Gnd
3
DO
2
CO
P−
Figure 2. Detailed Block Diagram
PIN FUNCTION DESCRIPTION
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Pin #
SOT23−6
Pin #
SON−6
Symbol
1
1
DO
This output connects to the gate of the discharge MOSFET allowing it to enable or disable
battery pack discharging.
2
6
P−
This is the charger negative input pin. It connects to the excess current detectors and serves as
the common node for the CO pin during turn−off.
3
5
CO
This output connects to the gate of the charge MOSFET switch allowing it to enable or disable
battery pack charging.
4
4
DS
This is the delay time reduction pin.
5
2
Vcell
This input connects to the positive terminal of the cell for voltage monitoring and provides
operating bias for the integrated circuit.
6
3
Gnd
This is the ground pin of the IC.
Description
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3
NCP802
CONNECT
CHARGER
CONNECT
LOAD
CONNECT
CHARGER
CONNECT
LOAD
EXCESS
DISCONNECT
CHARGE
CHARGER +
CURRENT CONNECT LOAD
VDET1
VCELL
t
VDD
−P
VDET3
Gnd
VDET4
t
tDET1
tDET1
tDET4
VDD
CO
tREL1
tREL1
tREL4
P−
t
CHARGE
CURRENT
CHARGE/
DISCHARGE
CURRENT
0
t
DISCHARGE
CURRENT
Figure 3. Overvoltage/Excess Charge Current Timing Chart
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4
NCP802
CONNECT
LOAD
CONNECT
CHARGER
CONNECT
LOAD
EXCESS
DISCHARGE
CONNECT CURRENT SHORT
CHARGER
OPEN
OPEN
VCELL
VDET2
t
VDD
Vshort
−P VDET3
Gnd
VDET4
t
tDET2
tDET2
tDET3
tshort
VDD
tREL2
DO
tREL2
tREL3
tREL3
Gnd
t
CHARGE
CURRENT
CHARGE/
DISCHARGE
CURRENT
0
t
DISCHARGE
CURRENT
Figure 4. Undervoltage/Excess Discharge Current Timing Chart
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5
NCP802
MAXIMUM RATINGS
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Rating
Symbol
Value
Unit
Supply Voltage (Pin 5 to Pin 6)
VDD
−0.3 to 12
V
Input Voltage
P− Pin Voltage (Pin 5 to Pin 2)
DS Pin Voltage (Pin 4 to Pin 6)
VP−
VDS
VDD + 0.3 to VDD − 28
−0.3 to 12
V
V
Output Voltage
CO Pin Voltage (Pin 3 to Pin 2)
DO Pin Voltage (Pin 1 to Pin 6)
VCO
VDO
VDD + 0.3 to VDD − 28
−0.3 to 12
V
V
Power Dissipation
PD
150
mW
Operating Ambient Temperature Range
TA
−40 to 85
°C
Storage Temperature
Tstg
−55 to 125
°C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
ATTRIBUTES
Characteristics
ESD Protection
Human Body Model (HBM)
Machine Model (MM)
Value
(C = 100 pF, R = 1.5 k)
(C = 200 pF, R = 0 )
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
≤1 kV
≤150 V
Level 1
≤150 mA
Latch−up Current Maximum Rating per JEDEC standard JESD78
1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
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6
NCP802
ELECTRICAL CHARACTERISTICS
(TA = 25°C, for min/max values TA is the operating junction temperature that applies, unless otherwise noted.)
Symbol
Characteristic
Min
Typ
Max
Unit
Note 2
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VOLTAGE SENSING
Cell Charging Cutoff (Pin 5 to Pin 6)
Overvoltage Threshold, VDD Increasing
(R1 = 330 )
TA = 25°C
TA = −5°C to 55°C
TA = 25°C
TA = −5°C to 55°C
TA = 25°C
TA = −5°C to 55°C
VDET1
SN1/SAN1T1
SN1/SAN1T1
SAN5T1
SAN5T1
SAN6T1
SAN6T1
Overvoltage Delay Time
(VDD = 3.6 V to 4.4 V)
4.325
4.32
4.25
4.245
4.255
4.25
4.35
4.35
4.275
4.275
4.28
4.28
4.375
4.38
4.30
4.305
4.305
4.31
0.175
0.7
0.250
01.0
0.325
1.3
11
16
21
2.34
2.24
2.4
2.3
2.46
2.36
tDET1
SN1/SAN1T1/SAN6T1
SAN5T1
Overvoltage Release Time
(VDD = 4.0 V, VP− = 0 V to 1.0 V)
tREL1
Cell Discharging Cutoff (Pin 5 to Pin 6)
Undervoltage Threshold, VDD Decreasing
VDET2
SN1/SAN1T1
SAN5T1/SAN6T1
V
V
V
V
V
V
A
A
A
s
A
ms
B
V
C
Undervoltage Time
(VDD = 3.6 V to 2.2 V)
tDET2
14
20
26
ms
C
Undervoltage Release Delay Time
(VDD = 3.0 V, VP− = 3.0 V to 0 V)
tREL2
0.7
1.2
1.7
ms
D
V
K
0.180
0.080
0.200
0.100
0.220
0.120
ms
K
8.0
4.0
12
6.0
16
8.0
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CURRENT SENSING
Excess Discharge Current Threshold, VP− Increasing
SN1T1/SAN1T1/SAN6T1
SAN5T1
VDET3
Excess Discharge Current Delay Time
(VDD = 3.0 V, VP− = 0 V to 1.0 V)
tDET3
SN1T1/SAN1T1/SAN6T1
SAN5T1
Excess Discharge Current Release Time
(VDD = 3.0 V, VP− = 3.0 V to 0 V)
tREL3
0.7
1.2
1.7
ms
K
Excess Charge Current Threshold, VP− Decreasing
VDET4
−0.13
−0.1
−0.07
V
E
Excess Charge Current Delay Time
(VDD = 3.0 V, VP− = 0 V to −1.0 V)
tDET4
ms
E
11
5.0
16
8.0
21
11
tREL4
0.7
1.2
1.7
ms
E
Short Protection Voltage
(VDD = 3.0 V)
VSHORT
VDD −1.4
VDD −1.1
VDD −0.8
V
K
Short Protection Delay Time
(VDD = 3.0 V, VP− = 0 V to 3.0 V)
tSHORT
250
400
600
s
K
Reset Resistance
(VDD = 3.6 V, VP− = 1.0 V)
RSHORT
15
30
45
k
K
SN1T1/SAN1T1/SAN6T1
SAN5T1
Excess Charge Current Release Time
(VDD = 3.0 V, VP− = −1.0 V to 0 V)
2. Indicates test circuits shown on pages 16 and 17.
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7
NCP802
ELECTRICAL CHARACTERISTICS
(TA = 25°C, for min/max values TA is the operating junction temperature that applies, unless otherwise noted.)
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Symbol
Min
Typ
Max
Unit
Note 3
Charge Gate Drive Output Low (Pin 3 to Pin 2) (VDD = 4.5 V, Io = 50 A)
Vol1
−
0.4
0.5
V
G
Charge Gate Drive Output High (Pin 5 to Pin 3) (VDD = 3.9 V, Io = −50 A)
Voh1
3.4
3.7
−
V
H
Discharge Gate Drive Output Low (Pin 1 to Pin 6)
(VDD = 2.0 V, Io = 50 A)
Vol2
−
0.2
0.5
V
I
Discharge Gate Drive Output High (Pin 5 to Pin 1)
(VDD = 3.9 V, Io = −50 A)
Voh2
3.4
3.7
−
V
J
DS Pin High Input Voltage
VIH
VDD
−0.5
−
VDD
+0.3
V
F
DS Pin Middle Input Voltage (VDD = 3.6 to 4.4 V)
VIM
1.05
−
VDD
−1.1
V
F
DS Pin Pull−down Resistance (VDD = 3.6 V)
RDS
0.5
1.3
2.5
M
F
−
−
3.0
−
6.0
0.1
µA
µA
Characteristic
OUTPUTS
DELAY SHORTENING (DS PIN)
TOTAL DEVICE
Supply Current
Operating (VDD = 3.9 V, VP− = 0 V)
Standby (VDD = 2.0 V)
Icell
Operating Voltage
VDD
1.5
−
5.0
V
−
Minimum Operating Cell Voltage for Zero Volt Charging
(Pin 5 to Pin 2) (VDD − Gnd = 0 V)
VST
−
−
1.5
V
M
3. Indicates test circuits shown on pages 16 and 17.
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8
L
OVERVOLTAGE DELAY TIME, tDET1 (s)
4.37
4.36
4.35
4.34
4.33
4.32
4.31
4.30
−50
50
0
100
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
−50
0
50
100
Figure 6. Overvoltage Delay Time vs.
Temperature
20
15
10
5
−40
−20
0
20
40
60
80
100
UNDERVOLTAGE THRESHOLD, VDET2 (V)
Figure 5. Overvoltage Threshold vs.
Temperature
25
2.43
2.42
2.41
2.40
2.39
2.38
2.37
2.36
−50
50
0
100
TA, AMBIENT TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
Figure 7. Overvoltage Release Time vs.
Temperature
Figure 8. Undervoltage Threshold vs.
Temperature
35
30
25
20
15
10
5
0
−50
0.40
TA, AMBIENT TEMPERATURE (°C)
30
0
−60
0.45
TA, AMBIENT TEMPERATURE (°C)
UNDERVOLTAGE RELEASE TIME, tREL2 (ms)
UNDERVOLTAGE DELAY TIME tDET2 (ms)
OVERVOLTAGE RELEASE TIME, tREL1 (ms)
OVERVOLTAGE THRESHOLD, VDET1 (V)
NCP802
0
50
100
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
−60
−40
−20
0
20
40
60
80
TA, AMBIENT TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
Figure 9. Undervoltage Delay Time vs.
Temperature
Figure 10. Undervoltage Release Time vs.
Temperature
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9
100
0.210
EXCESS DISCHARGE CURRENT
DELAY TIME, tDET3 (ms)
0.200
0.195
0.190
−60
−40
−20
0
20
40
60
80
16
14
12
10
8
6
4
2
0
−60
100
−40
−20
0
20
40
60
80
TA, AMBIENT TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
Figure 11. Excess Discharge Current
Threshold vs. Temperature
Figure 12. Excess Discharge Current Delay
Time vs. Temperature
100
50
RESET RESISTANCE, RSHORT (kΩ)
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
−60
−40
−20
0
20
40
60
80
40
VDD = 3.6 V
30
20
10
0
−60
100
−40
−20
0
20
40
60
80
TA, AMBIENT TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
Figure 13. Excess Discharge Current Release
Time vs. Temperature
Figure 14. Reset Resistance vs. Temperature
−0.110
−0.105
−0.100
−0.095
−0.090
−50
0
50
100
TA, AMBIENT TEMPERATURE (°C)
Figure 15. Excess Charge Current Threshold
vs. Temperature
EXCESS CHARGE CURRENT DELAY TIME, tREL4 (ms)
EXCESS CHARGE CURRENT THRESHOLD VDET4 (V)
18
0.205
EXCESS DISCHARGE CURRENT RELEASE
DELAY TIME, tREL2 (ms)
EXCESS DISCHARGE CURRENT THRESHOLD, VDET3 (V)
NCP802
100
30
25
20
15
10
5
0
−60
−40
−20
0
20
40
60
80
100
TA, AMBIENT TEMPERATURE (°C)
Figure 16. Excess Charge Current Delay Time
vs. Temperature
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10
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
−40
−20
0
20
40
60
80
100
2.10
2.05
VDD = 3.0 V
2.00
1.95
1.90
1.85
1.80
−50
0
50
Figure 17. Excess Charge Current Release
Time vs. Temperature
Figure 18. Short Protection Threshold vs.
Temperature
600
500
400
300
200
100
0
50
100
100
3
2.5
2
VDD = 3.0 V
1.5
1
0.5
0
−50
0
50
100
TA, AMBIENT TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
Figure 19. Short Protection Delay Time vs.
Temperature
Figure 20. DS Pin High Input Minimum Voltage
vs. Temperature
2.5
3
2.5
2
1.5
VDD = 3.6 V to 4.4 V
1
0.5
0
−50
2.15
TA, AMBIENT TEMPERATURE (°C)
700
0
−50
2.20
TA, AMBIENT TEMPERATURE (°C)
DS PIN HIGH MINIMUM VOLTAGE, VIH (V)
0
−60
SHORT PROTECTION VOLTAGE, VSHORT (V)
1.8
DS PIN PULL−DOWN RESISTANCE
DS PIN MIDDLE INPUT MINIMUM VOLTAGE, VIM (V)
SHORT PROTECTION DELAY TIME, tSHORT (s)
EXCESS CHARGE CURRENT RELEASE
TIME, tREL4 (ms)
NCP802
0
50
2
VDD = 3.6 V
1.5
1
0.5
0
−50
100
0
50
TA, AMBIENT TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
Figure 21. DS Pin Middle Input Minimum
Voltage vs. Temperature
Figure 22. DS Pin Pull−Down Resistance vs.
Temperature
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100
NCP802
3.9
CO PCH DRIVER OUTPUT, Voh1 (V)
CO NCH DRIVER OUTPUT, Vol1 (V)
0.5
0.4
0.3
0.2
0.1
0
−60
−40
−20
0
20
40
60
80
3.6
0
50
TA, AMBIENT TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
Figure 23. CO NCH Driver Output vs.
Temperature
Figure 24. CO PCH Driver Output vs.
Temperature
100
3.9
DO PCH DRIVER OUTPUT, Voh2 (V)
DO NCH DRIVER OUTPUT, Vol2 (V)
3.7
3.5
−50
100
0.4
0.3
0.2
0.1
0
−60
−40
−20
0
20
40
60
80
100
3.8
3.7
3.6
3.5
−50
0
50
TA, AMBIENT TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
Figure 25. DO NCH Driver Output vs.
Temperature
Figure 26. DO PCH Driver Output vs.
Temperature
100
0.1
STANDBY CURRENT Icell (A)
6
OPERATING CURRENT Icell (A)
3.8
5
4
3
2
1
0
−50
0
50
100
0.08
0.06
0.04
0.02
0
−50
0
50
TA, AMBIENT TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
Figure 27. Operating Current vs. Temperature
Figure 28. Standby Current vs. Temperature
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12
100
OVERVOLTAGE RELEASE TIME, tREL1 (s)
0.30
0.25
0.20
0.15
0.10
0.05
0.00
4.0
5.0
4.5
6.0
5.5
16
14
12
10
8
6
4
2
0
3.0
3.5
4.0
4.5
Figure 29. Overvoltage Delay Time vs.
Operating Voltage
Figure 30. Overvoltage Release Time vs.
Operating Voltage
UNDERVOLTAGE RELEASE TIME, tREL2 (ms)
VDD, OPERATING VOLTAGE (V)
22
20
18
16
14
12
10
8
6
4
2
0
1.0
1.5
2.0
2.5
1.4
1.2
1
0.8
0.6
0.4
0.2
0
2.0
2.5
3.0
3.5
4.0
VDD, OPERATING VOLTAGE (V)
VDD, OPERATING VOLTAGE (V)
Figure 31. Undervoltage Delay Time vs.
Operating Voltage
Figure 32. Undervoltage Release Time vs.
Operating Voltage
14
12
10
8
6
4
2
0
2.0
18
VDD, OPERATING VOLTAGE (V)
2.5
3.0
3.5
4.0
4.5
EXCESS DISCHARGE CURRENT RELEASE
DELAY TIME tREL2 (ms)
EXCESS DISCHARGE CURRENT DELAY
TIME tDET3 (ms)
UNDERVOLTAGE DELAY TIME, tDET2 (ms)
OVERVOLTAGE DELAY TIME, tDET1 (s)
NCP802
1.4
1.2
1
0.8
0.6
0.4
0.2
0
2.0
2.5
3.0
3.5
4.0
VDD, OPERATING VOLTAGE (V)
VDD, OPERATING VOLTAGE (V)
Figure 33. Excess Discharge Current Delay
Time vs. Operating Voltage
Figure 34. Excess Discharge Current Release
Time vs. Operating Voltage
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4.5
4.5
EXCESS CHARGE CURRENT RELEASE
TIME, tREL4 (ms)
18
16
14
12
10
8
6
4
2
0
2.0
2.5
3.0
3.5
4.0
4.5
1.2
1
0.8
0.6
0.4
0.2
0
2.0
2.5
3.5
3.0
4.0
VDD, OPERATING VOLTAGE (V)
Figure 35. Excess Charge Current Delay Time
vs. Operating Voltage
Figure 36. Excess Charge Current Release
Time vs. Operating Voltage
4.5
2.427
700
600
500
400
300
200
100
2.426
2.425
2.424
2.423
Undervoltage
Release
Threshold
2.422
2.421
2.420
2.419
Undervoltage
Threshold
2.418
2.417
2.416
0
2
2.5
3
3.5
0
4.5
4
100 200 300 400 500 600 700 800 900 1000
VDD, OPERATING VOLTAGE (V)
R1 (Ω)
Figure 37. Short Protection Delay Time vs.
Operating Voltage
Figure 38. Undervoltage Thresholds vs. R1
2.5
4.293
4.292
Overvoltage
Threshold
4.291
Overvoltage
Release
Threshold
4.29
4.289
CHARGER VOLTAGE TO RELEASE
FROM UNDERVOLTAGE (V)
4.294
OVERVOLTAGE THRESHOLD (V)
1.4
VDD, OPERATING VOLTAGE (V)
UNDERVOLTAGE THRESHOLD (V)
SHORT PROTECTION DELAY TIME, tSHORT (s)
EXCESS CHARGE CURRENT DELAY
TIME, tREL4 (ms)
NCP802
2
VDD = 4.25 V
1.5
1
0.5
0
4.288
0
100 200 300 400 500 600 700 800 900 1000
0
50
100
150
200
250
R1 (Ω)
R2 (kΩ)
Figure 39. Overvoltage Thresholds vs. R1
Figure 40. Charger Voltage to Release from
Undervoltage vs. R2
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300
MINIMUM OPERATING VOLTAGE FOR 0 V
CHARGING VST (V)
NCP802
2
1.8
1.6
VDD − GND = 0
1.4
1.2
1
0.8
0.6
0.4
0.2
0
−50
50
0
100
TA, AMBIENT TEMPERATURE (°C)
Figure 41. Minimum Operating Voltage for 0 V
Charging vs. Temperature
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15
NCP802
A
E
VCELL
V
P−
VCELL
CO
P−
CO
V
GND
GND
B
F
VCELL
VCELL
DS
P−
CO
P−
DO
A
V
GND
GND
G
C
VCELL
V
P−
VCELL
DO
P−
GND
CO
A
V
GND
D
H
VCELL
P−
VCELL
DO
P−
GND
GND
Figure 42. Test Circuits
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16
CO
A
V
NCP802
I
K
VCELL
P−
VCELL
DO
A
P−
DO
A
V
V
GND
GND
J
L
VCELL
VCELL
A
DO
A
P−
V
P−
GND
GND
M
VCELL
V
V
DO
P−
CO
GND
Figure 43. Test Circuits
Overvoltage Detection
reset from an overvoltage fault as long as a charger is
connected to the battery. Rather, the excess−discharge
current detector (VD3) signals the IC to reset from an
overvoltage condition by detecting a load while in an
overvoltage condition. When the P− pin voltage becomes
equal to or greater than than the excess discharge−current
detector threshold (VDET3) during an overvoltage fault, the
NCP802 senses the voltage drop across the charge
MOSFET’s body diode induced by the load current. It then
resets from the overvoltage state.
There are internal, fixed delay times for both the detection
and release from an overvoltage condition. If the fault or
reset conditions are shorter than their respective delay times,
the NCP802 ignores that condition and stays in its previous
state.
The overvoltage detector (VD1) monitors the VCELL pin
voltage. When the VCELL voltage crosses the overvoltage
detector threshold (VDET1) from a low value to a value
higher than VDET1, VD1 detects an over−charging
condition. The NCP802 then turns off an external, charge
control, N−channel, MOSFET by driving the CO pin to its
low level. A level shifter, incorporated in a buffer driver for
the CO pin, drives the low level of the CO pin to the P− pin
voltage, which is connected to the source of the charge
control MOSFET by a resistor. The high level of the CO pin
is driven to the VCELL voltage with a CMOS buffer.
To reset the CO pin to its high level, the voltage at the
VCELL pin must decrease to a level lower than VDET1. The
overvoltage detector does not reset after the battery voltage
falls below some hysteresis voltage. The NCP802 will not
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17
NCP802
Undervoltage Detection
short circuit detector has activated; removing the cause of
that activation turns the discharge MOSFET back on. This
occurs because RSHORT pulls the P− pin, voltage level
down to the GND pin, voltage level. The NCP802 internally
disconnects RSHORT during a normal, fault−free, state. The
NCP802 only connects RSHORT if it has detected an excess
discharge−current or short circuit fault. In other words, VD3
is automatically released from excess discharge−current and
short circuit faults when the user removes the load.
The output delay time of excess discharge−current
detection is set shorter than the delay time for undervoltage
detection. Therefore, if VCELL voltage drops below
VDET2 during an excess discharge−current or short circuit
fault, the NCP802 detects the current fault first. This
prevents large discharge current faults from activating the
undervoltage detector and putting the NCP802 into standby
mode. Standby mode requires the charger to reset the
NCP802, while excess discharge−current and short circuit
faults only require that the fault be removed.
The undervoltage detector (VD2) monitors the VCELL
pin voltage. When the VCELL voltage crosses the
undervoltage threshold (VDET2) from a high value to a
value lower than VDET2, VD2 senses an undervoltage
condition, and an external, discharge control, N−channel
MOSFET turns off by driving the DO pin to its low level.
The low level of DO is set to GND and the high level to
VCELL.
To reset the DO pin to its high level, one must connect a
charger to the battery pack. While the VCELL voltage
remains under VDET2, charge−current can flow through the
parasitic diode of the external discharge control MOSFET.
Once the VCELL voltage rises above VDET2, the NCP802
drives DO high. Connecting a charger to the battery pack
drives the DO level high instantaneously when the VCELL
voltage is higher than VDET2. VD2 has no hysteresis.
After VD2 detects an undervoltage condition, the
NCP802 enters a low supply current, standby mode.
Maximum standby current equals 0.1 A at VCELL equal
to 2.0 V. An internal pull−up disables all the device functions
and thus drastically lowers quiescent current. When the
charger connects to the battery, it pulls small levels of
current from the P− pin. This overcomes the internal pull−up
and allows the NCP802 to reset.
There are internal, fixed delay times for both the detection
and release from an undervoltage condition. If the fault or
reset conditions are shorter than their respective delay times,
the NCP802 ignores that condition and stays in its previous
state.
Excess Charge−Current Detection
When the battery pack is chargeable and discharge is also
possible, VD4 senses the P− pin voltage. For example, if the
user connects the battery to an inappropriate charger, excess
current can flow. Then, the P− voltage drops below the
excess charge−current threshold (VDET4). Next, the output
of CO becomes low. This prevents excess current flow into
the circuit by turning off the external MOSFET.
The output delay of the excess charge−current detector is
internally fixed. If the fault condition is within the delay time
window, the detector will not sense it and the MOSFET will
not change state. VD4 can be released by disconnecting a
charger and applying a load.
Excess Discharge−Current/Short Circuit Detection
The excess discharge−current detector (VD3) and the
short circuit detector can function when the control
MOSFET’s are on. When the P− pin voltage is below the
short circuit detection voltage (VSHORT) and above the
excess discharge−current threshold (VDET3), VD3
operates. When the P− pin voltage rises higher than
VSHORT, the NCP802 enables the short circuit detector.
When either detector activates, the NCP802 turns off an
external, discharge control, N−channel, MOSFET by
driving the DO pin to its low level.
The output delay time for the excess discharge−current
detector is internally fixed. If the P− pin, voltage level
recovers from a level between VSHORT and VDET3 within
the delay time, the discharge MOSFET stays in its high state.
Output delay time for release from excess discharge−current
detection is typically 1.2 ms. When the short circuit detector
activates, DO transitions to its low state after a delay time of
approximately 400 s.
There is an integrated pull−down resistor (RSHORT)
connected between the P− and GND pins. After VD3 or the
Delay Shortening Function
The output delay time of over−charge, over−discharge,
excess discharge−current, excess charge−current, and the
release from those detecting modes can be made shorter than
the pre−set value by forcing the VCELL voltage to the DS
pin. When one forces the specified middle range voltage to
the DS pin, the output delay circuit becomes disabled.
Therefore, under this condition, when over−charge or excess
charge current is detected, output level can be checked
without waiting for the delay.
A 1.3 M pull−down resistor is connected between DS
pin and GND internally. For normal operation, the DS pin
should be at no connection state.
Zero Battery Voltage Charging
If the charger voltage is equal or higher than the zero−volt
charge, minimum voltage (VST), the NCP802 drives the CO
pin high. Therefore, it allows charging for batteries as low
as zero volts.
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18
NCP802
+
R1
330 VCELL
DS
C1
0.1 µF
NCP802
GND
DO
P−
CO
R2
1 k
−
Figure 44. Typical Application Circuit
Technical Notes
R1 and C1 will stabilize a supply voltage to the NCP802. A recommended R1 value is less than 1.0 k A larger value of R1
leads to higher detection voltages. There may also be voltage detector errors from shoot through current into the NCP802.
R1 and R2 can also help current limit the circuit against reverse charge or a charger with excess charging voltage applied to
the NCP802 battery pack. Smaller R1 and R2 values may cause excessive power consumption over the specified power
dissipation rating. Therefore, the total value of R1 R2 should be equal to or more than 1.0 k However, if one uses a very
large value of R2, it might not be possible to release from undervoltage by connecting a charger. The recommended R2 value
is equal to or less than 30 k.
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19
NCP802
ORDERING INFORMATION
Device
NCP802SN1T1
NCP802SAN1T1
NCP802SAN1T1G
Package
Marking Code
Shipping†
SOT23−6
KN
3000 Tape & Reel
SON−6
KN
3000 Tape & Reel
SON−6
(Pb−Free)
KN
3000 Tape & Reel
NCP802SAN5T1
SON−6
K7
3000 Tape & Reel
NCP802SAN6T1
SON−6
KD
3000 Tape & Reel
SON−6
(Pb−Free)
KD
3000 Tape & Reel
NCP802SAN6T1G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
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20
NCP802
PACKAGE DIMENSIONS
SOT23−6
SN SUFFIX
PLASTIC PACKAGE
CASE 1262−01
ISSUE A
E
0.20
PIN 1
IDENTIFIER
M
C B
0.05
M
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSION D DOES NOT INCLUDE FLASH OR
PROTRUSIONS. FLASH OR PROTRUSIONS
SHALL NOT EXCEED 0.23 PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. DIMENSIONS D AND E1 ARE TO BE DETERMINED
AT DATUM PLANE H.
C
S
B
S
5
A
E1
b
4
B
A
M
A1
A
0.10
3
C A
2
6
e
A
e1
D
1
ÉÉÉÉÉ
ÇÇÇÇ
ÉÉÉÉÉ
ÇÇÇÇ
H
L
c
c1
b
b1
SECTION A−A
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21
DIM
A
A1
b
b1
c
c1
D
E
E1
e
e1
L
MILLIMETERS
MIN
MAX
0.90
1.45
0.00
0.15
0.35
0.50
0.35
0.45
0.09
0.20
0.09
0.15
2.80
3.00
2.60
3.00
1.50
1.75
0.95
1.90
0.25
0
0.55
10 NCP802
PACKAGE DIMENSIONS
SON−6
SAN SUFFIX
PLASTIC PACKAGE
CASE 494−01
ISSUE 0
A
6
5
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
4
K
1
1
B L
4
2
E
3
C
J
D 6 PL
0.10 (0.004)
−T− SEATING PLANE
0.15 (0.010)
M
T X Y
G
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22
DIM
A
B
C
D
E
G
J
K
L
MILLIMETERS
MIN
MAX
1.40
1.80
2.40
2.80
−−−
0.90
0.10
0.30
1.24
1.44
0.50 BSC
0.08
0.18
0.30 BSC
2.85
3.15
INCHES
MIN
MAX
0.055
0.071
0.094
0.110
−−−
0.035
0.004
0.012
0.049
0.057
0.020 BSC
0.003
0.007
0.012 BSC
0.112
0.124
NCP802
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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For additional information, please contact your
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NCP802/D