NM25C04L 4096-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface (SPI TM ) Synchronous Bus) General Description The NM25C04L is a 4096-bit CMOS EEPROM with an SPI compatible serial interface. The NM25C04L is designed for data storage in applications requiring both non-volatile memory and in-system data updates. This EEPROM is well suited for applications using the 68HC11 series of microcontrollers that support the SPI interface for high speed communication with peripheral devices via a serial bus to reduce pin count. The NM25C04L is implemented in National Semiconductor’s single poly, double metal CMOS process that provides superior endurance and data retention. The serial data transmission of this device requires four signal lines to control the device operation: Chip Select (CS), Clock (SCK), Data In (SI), and Data Out (SO). All programming cycles are completely self-timed and do not require an erase before WRITE. BLOCK WRITE protection is provided by programming the STATUS REGISTER with one of four levels of write protection. Additionally, separate program enable and program disable instructions are provided for data protection. Hardware data protection is provided by the WP pin to protect against accidental data changes. The HOLD pin allows the serial communication to be suspended without resetting the serial sequence. Features Y Y Y Y Y Y Y Y Y Y 4096 bits organized as 512 bytes Multiple chips on the same 3-wire bus with separate chip select lines Self-timed programming cycle Simultaneous programming of 1 to 4 bytes at a time Status register can be polled during programming to monitor RDY/BUSY Write Protect (WP) pin and write disable instruction for both hardware and software write protection Block write protect feature to protect against accidental writes Endurance: 106 data changes Data retention greater than 40 years Packages available: 8-pin DIP or 8-pin SO Block Diagram TL/D/11729 – 1 SPITM is a trademark of Motorola Incorporated. C1995 National Semiconductor Corporation TL/D/11729 RRD-B30M65/Printed in U. S. A. NM25C04L 4096-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus) November 1993 Connection Diagram Pin Names Dual-In-Line Package (N) and SO Package (M8) TL/D/11729–2 Top View CS Chip Select Input SO Serial Data Output WP Write Protect VSS Ground SI Serial Data Input SCK Serial Clock Input HOLD Suspends Serial Input VCC Power Supply Ordering Information Commercial Temperature Range (0§ C to a 70§ C) Extended Temperature Range (b40§ C to a 85§ C) Order Number Order Number NM25C04LN NM25C04LM8 NM25C04LEN NM25C04LEM8 2 Absolute Maximum Ratings (Note 1) Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Ambient Operating Temperature NM25C04L NM25C04LE Ambient Storage Temperature Power Supply (VCC) Read Mode All Other Modes All Input or Output Voltages with Respect to Ground Lead Temperature (Soldering, 10 sec.) ESD Rating b 65§ C to a 150§ C a 6.5V to b 0.3V b 0§ C to a 70§ C b 40§ C to a 85§ C 2.0V to 5.5V 2.5V to 5.5V a 300§ C 2000V DC and AC Electrical Characteristics 4.5V s VCC s 5.5V (unless otherwise specified) Symbol ICC Parameter Operating Current Part Number NM25C04L Conditions Min CS e VIL NM25C04LE ICCSB Standby Current NM25C04L CS e VCC NM25C04LE IIL Input Leakage IOL Output Leakage NM25C04L Max Units 3 mA 3 mA 150 mA 150 mA 1 mA VIN e 0V to VCC b1 VOUT e 0V to VCC b1 1 mA b1 a1 mA V NM25C04LE VIL Input Low Voltage b 0.3 0.3 * VCC VIH Input High Voltage 0.7 * VCC VCC a 0.3 V VOL Output Low Voltage 0.2* VCC V 0.2* VCC V VOH Output High Voltage fOP SCK Frequency 1 1 MHz MHz tRI Input Rise Time 2.0 ms tFI Input Fall Time 2.0 ms tCLH Clock High Time NM25C04L IOL e 10mA NM25C04LE IOH e 10 mA NM25C04L NM25C04LE NM25C04L Note 2 NM25C04LE tCLL Clock Low Time NM25C04L Note 2 NM25C04LE tCSH Min CS High Time NMC25C04L Note 3 NM25C04LE tCSS tDIS CS Setup Time Data Setup Time 0.8 * VCC V 500 ns 500 ns 500 ns 500 ns 500 ns 500 ns NM25C04L 500 ns NM25C04LE 500 ns NM25C04L 100 ns NM25C04LE 100 ns 3 DC and AC Electrical Characteristics 4.5V s VCC s 5.5V (unless otherwise specified) (Continued) Symbol tHDS tCSN Parameter Part Number HOLD Setup Time CS Hold Time Conditions Min Max Units NM25C04L 200 ns NM25C04LE 200 ns NM25C04L 500 ns NM25C04LE 500 ns tDIN Data Hold Time 100 ns tHDN HOLD Hold Time 200 ns tPD Output Delay NM25C04L CL e 200 pF NM25C04LE tLZ tDF HOLD to Output Low Z Output Disable Time NM25C04L 500 ns 500 ns NM25C04L tWP HOLD to Output High Z CL e 200 pF 500 ns 500 ns NM25C04L 500 ns NM25C04LE 500 ns 10 ms Write Cycle Time 1 – 4 Bytes Capacitance (Note 4) AC Test Conditions TA e 25§ C, f e 1 MHz Symbol ns ns NM25C04LE NM25C04LE tHZ 500 500 Test Typ Max Units COUT Output Capacitance 3 8 pF CIN Input Capacitance 2 6 pF Output Load IOL e 10 mA, IOH e 10 mA Input Pulse Levels 0.3V and 1.8V Timing Measurement Reference Level Input 0.4V and 1.6V Output 0.8V and 1.6V Note 1: Stress above those listed under ‘‘Absolute Maximum Ratings’’ may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: The SCK frequency specification specifies a minimum clock period of 1000 ns; therefore, in an SCK clock cycle tCLH a tCLL must be greater than or equal to 1000 ns. For example, if tCLL e 410 ns, then the minimum tCLH e 550 ns in order to meet the SCK freqency specification. Note 3: CS must be brought high for a minimum of 500 ns (tCSH) between consecutive instruction cycles. Note 4: This parameter is periodically sampled and not 100% tested. 4 Synchronous Data Timing TL/D/11729 – 3 FIGURE 1. Timing Diagram Note: When connected to the SPI port of a 68HC11 microcontroller, the NM25C04L accepts only a clock phase of 1 and a clock parity of 0. Clock Phase 1: CS is held LOW during all serial communications and is held HIGH only between instructions. Clock Polarity 0: Clock data IN on negative clock edge and clock data OUT on positive clock edge. SPI Serial Interface TL/D/11729 – 4 FIGURE 2 5 Functional Description brought low while the SCK pin is high. The device must remain selected during this sequence. To resume serial communication HOLD is brought high while the SCK pin is high. Pins SI, SCK, and SO are at a high impedance state during HOLD. See Figure 4 . MASTER: The device that generates the serial clock is designated as the master. The NM25C04L can never function as a master. SLAVE: The NM25C04L always operates as a slave as the serial clock pin is always an input. TRANSMITTER/RECEIVER: The NM25C04L has separate pins for data transmission (SO) and reception (SI). MSB: The Most Significant Bit is the first bit transmitted and received. CHIP SELECT: The chip is selected when pin CS is low. When the chip is not selected, data will not be accepted from pin SI, and the output pin SO is in high impedance. SERIAL OP-CODE: The first byte transmitted after the chip is selected with CS going low contains the op-code that defines the operation to be performed. In the READ and WRITE instructions the op-code also contains address bit A8. PROTOCOL: When connected to the SPI port of a 68HC11 microcontroller, the NM25C04L accepts only a clock phase of 1 and a clock polarity of 0. The SPI protocol for this device defines the bytes transmitted on the SI and SO data lines for proper chip operation. See Figure 3 . TL/D/11729 – 6 FIGURE 4. HOLD Timing INVALID OP-CODE: After an invalid code is received, no data is shifted into the NM25C04L, and the SO data output pin remains high impedance until a new CS falling edge reinitializes the serial communication. See Figure 5 . TL/D/11729 – 7 FIGURE 5 TABLE 1 TL/D/11729–5 FIGURE 3 Phase 1: CS is held LOW during all serial communications and is held HIGH only between instructions. Polarity 0: Clock data IN on negative SCK edge and clock data OUT on positive SCK edge. HOLD: The HOLD pin is used in conjunction with the CS to select the device. Once the device is selected and a serial sequence is underway, HOLD may be forced low to suspend further serial communication with the device without resetting the serial sequence. Note that HOLD must be Instruction Name Instruction Format WREN 0000 X110 Operation Set Write Enable Latch WRDI 0000 X100 Reset Write Enable Latch RDSR 0000 X101 Read Status Register WRSR 0000 X001 Write Status Register READ 0000 A011 Read Data from Memory Array WRITE 0000 A010 Write Data to Memory Array Note: ‘‘A’’ represents MSB address bit A8. 6 READ SEQUENCE: (One or More Bytes) Reading the memory via the serial SPI link requires the following sequence. The CS line is pulled low to select the device. The READ op-code (which includes A8) is transmitted on the SI line followed by the byte address (A7 – A0) to be read. After this is done, data on the SI line becomes don’t care. The data (D7–D0) at the address specified is then shifted out on the SO line. If only one byte is to be read, the CS line can be pulled back to the high level. It is possible to continue the READ sequence as the byte address is automatically incremented and data will continue to be shifted out. When the highest address is reached (1FF), the address counter rolls over to lowest address (000) allowing the entire memory to be read in one continuous READ cycle. See Figure 6 . TL/D/11729 – 9 FIGURE 7 WRITE ENABLE (WREN): When VCC is applied to the chip, it ‘‘powers up’’ in the write disable state. Therefore, all programming modes must be preceded by a WRITE ENABLE (WREN) instruction. Additionally the WP pin must be held high during a WRITE ENABLE instruction. At the completion of a WRITE or WRSR cycle the device is automatically returned to the write disable state. Note that a WRITE DISABLE (WRDI) instruction or forcing the WP pin low will also return the device to the write disable state. See Figure 8 . TL/D/11729 – 8 FIGURE 6 READ STATUS REGISTER (RDSR): The Read Status Register (RDSR) instruction provides access to the status register which is used to interrogate the READY/BUSY and WRITE ENABLE status of the chip. Two non-volatile status register bits are used to select one of four levels of BLOCK WRITE PROTECTION. The status register format is shown in Table 2. TL/D/11729 – 10 FIGURE 8 WRITE DISABLE (WRDI): To protect against accidental data disturbance the WRITE DISABLE (WRDI) instruction disables all programming modes. The WRITE DISABLE instruction is independent of the status of the WP pin. See Figure 9 . TABLE 2. Status Register Format Bit 7 1 Bit 6 1 Bit 5 1 Bit 4 1 Bit 3 BP1 Bit 2 BP0 Bit 1 WEN Bit 0 RDY Status register Bit 0 e 0 (RDY) indicates that the device is READY; Bit 0 e 1 indicates that a program cycle is in progress. Bit 1 e 0 (WEN) indicates that the device is not WRITE ENABLED; Bit 1 e 1 indicates that the device is WRITE ENABLED. Non-volatile status register Bits 2 and 3 (BP0 and BP1) indicate the level of BLOCK WRITE PROTECTION selected. The block write protection levels and corresponding status register control bits are shown in Table 3. Note that if a RDSR instruction is executed during a programming cycle only the RDY bit is valid. All other bits are 1s. See Figure 7 . TL/D/11729 – 11 FIGURE 9 TABLE 3. Block Write Protection Levels Level Status Register Bits Array Addresses Protected BP1 BP0 0 0 0 None 1 0 1 180–1FF 2 1 0 100–1FF 3 1 1 000–1FF 7 REGISTER (RDSR) instruction. Bit 0 e 1 indicates that the WRITE cycle is still in progress and Bit 0 e 0 indicates that the WRITE cycle has ended. During the WRITE programming cycle (Bit 0 e 1) only the READ STATUS REGISTER instruction is enabled. The NM25C04L is capable of a four byte PAGE WRITE operation. After receipt of each byte of data the two low order address bits are internally incremented by one. The seven high order bits of the address will remain constant. If the master should transmit more than four bytes of data, the address counter will ‘‘roll over’’, and the previously loaded data will be reloaded. At the completion of a WRITE cycle the device is automatically returned to the write disable state. If the WP pin is forced low or the device is not WRITE enabled, the device will ignore the WRITE instruction and return to the standby state when CS is forced high. A new CS falling edge is required to re-initialize the serial communication. See Figure 11 . WRITE SEQUENCE: To program the device the WRITE PROTECT (WP) pin must be held high and two separate instructions must be executed. The chip must first be write enabled via the WRITE ENABLE instruction and then a serial WRITE instruction must be executed. Moreover, the address of the memory location(s) to be programmed must be outside the protected address field selected by the Block Write Protection Level. See Table 3. A serial WRITE command requires the following sequence. The CS line is pulled low to select the device, then the WRITE op-code (which includes A8) is transmitted on the SI line followed by the byte address (A7–A0) and the corresponding data (D7–D0) to be programmed. Programming will start after the CS pin is forced back to a high level. Note that the LOW to HIGH transition of the CS pin must occur during the SCK low time immediately after clocking in the D0 data bit. See Figure 10 . The READY/BUSY status of the device can be determined by executing a READ STATUS TL/D/11729 – 13 FIGURE 10. Start WRITE Condition TL/D/11729 – 12 FIGURE 11 8 and BP0 then two additional don’t care bits. Programming will start after the CS pin is forced back to a high level. As in the WRITE instruction the LOW to HIGH transition of the CS pin must occur during the SCK low time immediately after clocking in the last don’t care bit. See Figure 13 . The READY/BUSY status of the device can be determined by executing a READ STATUS REGISTER (RDSR) instruction. Bit 0 e 1 indicates that the WRSR cycle is still in progress and Bit 0 e 0 indicates that the WRSR cycle has ended. At the completion of a WRSR cycle the device is automatically returned to the write disable state. WRITE STATUS REGISTER (WRSR): The WRITE STATUS REGISTER (WRSR) instruction is used to program the non-volatile status register Bits 2 and 3 (BP0 and BP1). As in the WRITE mode the WRITE PROTECT (WP) pin must be held high and two separate instructions must be executed. The chip must first be write enabled via the WRITE ENABLE instruction and then a serial WRSR instruction must be executed. The serial WRSR command requires the following sequence. The CS line is pulled low to select the device and then the WRSR op-code is transmitted on the SI line followed by the data to be programmed (see Figure 12 ). Note that the first four bits are don’t care bits followed by BP1 TL/D/11729 – 14 FIGURE 12 TL/D/11729 – 15 FIGURE 13. Start WRSR Condition 9 10 Physical Dimensions inches (millimeters) Molded Small Out-Line Package (M8) Order Number NM25C04LM8 NS Package Number M08A 11 NM25C04L 4096-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus) Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number NM25C04LN NS Package Number N08E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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