NT6868A
Keyboard Controller
Features
n Mask optional for built-in RC oscillator with an
external resistor or external ceramic resonator applied
n Watch-dog timer
n Built-in power-on reset
n Built-in low voltage reset
n CMOS technology for low power consumption
n Available in 40 pin DIP package and 40 pad CHIP
FORM
n
n
n
n
n
Built-in 6502 8-bit CPU
2 MHz CPU operation frequency
4K bytes of ROM
128 bytes of SRAM
One 8-bit programmable base timer with
1 - 256 µsec interval
n 29 programmable bi-directional I/O pins
n 3 LED direct sink pins with internal serial resistors
General Description
NT6868A is a single chip micro-controller for keyboard
applications. It incorporates a 6502 8-bit CPU core, 4K
bytes of ROM, and 128 bytes of RAM used as working
RAM and stack area. It also includes 29 programmable
bi-directional I/O pins and one 8-bit pre-loadable base
Pin Configuration
Pad Configuration
GND
1
NC
2
DATA
3
4
38
5
36
6
35
34
CLK
P30
P31
P32
RESET
P00
11
P01
12
13
P04
37
7
8
9
10
P02
P03
40
39
14
15
OSCI
R/OSCO
VDD
LED2
LED1
P
1
6
P
1
5
P
1
4
P
1
3
P
1
2
P
1
1
P
1
0
P
0
7
P
0
6
26
25
24
23
22
21
20
19
18
17
16
P05
15
P04
LED0
P20
27
14
P03
P21
28
13
P02
29
12
P01
30
P24
P23
P22
P23
30
11
P00
29
28
P22
P21
P24
31
10
RESET
27
P20
P17
P25
32
9
P34
P26
33
8
P33
7
P32
6
P31
32
31
26
P05
16
25
P16
P06
P07
P10
17
24
23
P15
P11
20
18
19
P
1
7
P27
P26
P25
33
NT6868A
P33
P34
timer. Additionally, it includes a built-in low voltage
reset, a 4MHz RC oscillator that requires only a resistor
externally applied or a 4MHz ceramic resonator, and a
watch-dog timer that prevents system standstill.
22
21
P14
P13
P12
P27
34
LED0
35
LED1
36
1
NT6868AH
37
38
39
40
1
L
E
D
2
V
R
/
O
S
C
O
O
S
C
I
G
N
D
D
D
2
3
4
5
N
C
D
A
T
A
C
L
K
P
3
0
V2.1
NT6868A
Block Diagram
CLK
TIMING GENERATOR
(RC OSC/CERAMIC RESONATOR:
4MHz)
4K BYTES
ROM
DATA
LED0
LED1
LED2
128 BYTES
SRAM + STACK
6502
CPU
I/O PORTS
P10 - P17
WATCH DOG
TIMER
INT. CONTROLLER
P00 - P07
P20 - P27
RESET
POWER-ON RESET/
LOW VOLTAGE RESET
VDD
BASE TIMER
P30 - P34
GND
Pin and Pad Descriptions
Pin No.
Pad No.
Designation
I/O
Description
1
1
GND
P
Ground pin
2
2
NC
-
No connection, recommended to connect VDD or floating
3
3
DATA
I/O
I/O, 10KΩ pull-up resistor for communication
4
4
CLK
I/O
I/O, 10KΩ pull-up resistor for communication
5 - 9,
11 - 34
5 - 9,
11 - 34
P30 - P34,
P00 - P27
I/O
Bi-directional I/O pins
10
10
RESET
I
RESET signal input pin with internal pull up resistor; Active low
35 - 37
35 - 37
LED0 LED2
O
LED direct sink pins
38
38
VDD
P
Power supply
39
39
R/OSCO
I
47KΩ resistor connected for RC OSC or 4MHz ceramic resonator
connected
40
40
OSCI
-
No connection for RC OSC, connected for 4MHz ceramic
resonator
* Under the constraint of the maximum frequency variation, (∆F/F)max, ≤ ±1%, code 3 (ceramic resonator option) must be
selected and pin 39 and pin 40 are connected to a ceramic resonator. If (∆F/F)max, ≤ ±10%, code 1 (RC OSC option) is
recommended to be selected and pin39 connects a 47KΩ resistor with, ≤ ±1% accuracy to VDD and pin 40 is floating.
2
NT6868A
Functional Description
6502 CPU
6502 is an 8-bit CPU. Refer to 6502 data sheet for details.
7
0
0000
ACCUMULATOR A
SRAM
7
0
007F
INDEX REGISTER X
STACK PTR
UNUSED
00C0
7
SYSTEM REGISTERS
0
00CF
INDEX REGISTER Y
15
0
UNUSED
PROGRAM COUNTER PC
7
0
7
S
F000
STACK POINTER SP
S
0
V
B
D
I
Z
C
USER ROM
STATUS REGISTER P
FFFA
NMI-L
CARRY
FFFB
ZERO
NMI VECTOR
NMI-H
INTERRUPT MASK
FFFC
RST-L
DECIMAL MODE
FFFD
BREAK
FFFE
OVERFOLW
RST-H
IRQ-L
IRQ VECTOR
FFFF
IRQ-H
SIGN
Figure 1. 6502 CPU Registers and Status Flags
3
Figure 2. NT6868A Memory Map
NT6868A
System Reserved Registers
Address
Register
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
$00C0
BT
BT7
BT6
BT5
BT4
BT3
BT2
BT1
BT0
W
$00C1
TCON
-
-
-
-
-
-
-
ENBT
W
$00C2
CLRIRQX
-
-
-
-
-
-
-
CLRIRQTMR
W
$00C3
PORT0
PD07
PD06
PD05
PD04
PD03
PD02
PD01
PD00
RW
$00C4
PORT1
PD17
PD16
PD15
PD14
PD13
PD12
PD11
PD10
RW
$00C5
PORT2
PD27
PD26
PD25
PD24
PD23
PD22
PD21
PD20
RW
$00C6
PORT3
-
-
-
PD34
PD33
PD32
PD31
PD30
RW
$00C7
CLK
-
-
-
-
-
-
-
CLK
RW
$00C8
DATA
-
-
-
-
-
-
-
DATA
RW
$00C9
LED
-
-
-
-
-
LED2
LED1
LED0
W
$00CA
CLRWDT
0
1
0
1
0
1
0
1
W
$00CB
X
X
X
X
X
X
X
X
X
X
$00CC
X
X
X
X
X
X
X
X
X
X
$00CD
X
X
X
X
X
X
X
X
X
X
$00CE
X
X
X
X
X
X
X
X
X
X
$00CF
X
X
X
X
X
X
X
X
X
X
- : no effect
X : access not allowed
4K X 8 ROM
Power-On Reset
The built-in ROM program code, executed by the 6502
CPU, has a capacity of 4K X 8 bits and is addressed
from F000H to FFFFH.
Built-in power-on reset circuit can generate a 150ms
pulse to reset the entire chip. The beginning of the
150ms pulse occurs at 60% of VDD when powered on.
128 X 8 SRAM
The built-in SRAM is used for general purpose data
memory and for the stack area. SRAM is addressed from
0000H to 007FH. User can allocate stack area in the
SRAM by setting stack pointer register (S). Because the
6502C default stack pointer is 01FFH, it must be
mapped to 007FH. Mapping from 01XX to 00XX is done
internally by setting the S register to 7FH via software
programming.
power
VDD
60%
The start of 150ms pulse
t
For example :
LDX
TXS
#$7F
4
NT6868A
Timing Generation
The following table provides the relationship between
external resistor and RC OSC frequency. (for reference
only)
This block generates the system timing and control
signal supplied to CPU and on-chip peripherals. There
are two types of system clock sources: built-in RC
oscillator or external ceramic resonator. Both of them are
mask optional and generate a 4MHz system clock. They
also generates 2MHz for CPU, and 1MHz for base timer.
The following shows the relationship of code type
number and oscillation type.
Oscillator Type
External Resistor
(KΩ )
RC OSC Frequency (MHz)
39
4.7
43
4.44
47
4
56
3.68
Code Number
RC OSC
1
Ceramic Resonator
3
Base Timer
The base timer is an 8-bit counter with a 1MHz clock source. The base timer can be enabled/disabled by CPU. After reset,
the base timer is disabled and cleared. The base timer can be preset by writing BT7 - BT0 to the BT register at any time.
When enabled, the base timer starts counting from the preset value. When the value reaches FFH, it generates a timer
interrupt if the timer interrupt is enabled. When it reaches the maximum value of FFH, the base timer will wrap around and
begin counting at 00H. The timer interval can be programmed from 1 - 256 µsec. The base timer can be enabled by writing
a '0' to ' ENBT ' in the TCON (Timer Control) register. The ENBT is a level trigger.
Base timer structure:
8-Bit timer
1µs
BT7
BT6
BT5
BT4
BT2
BT2
BT1
TMRINT
BT0
BT pre-load data:
Addr.
Bit
7
6
5
4
3
2
1
0
$00C0
BT
BT7
BT6
BT5
BT4
BT3
BT2
BT1
BT0
(W)
TCON
-
-
-
-
-
-
-
ENBT
(W)
Timer Control Regisrer:
$00C1
INT. Controller
When BASE TIMER overflow occurs, it will set the IRQTMR flag. The IRQTMR flag cannot be directly accessed by
software. Once set by an interrupt source, it remains High unless cleared by writing '1' to the corresponding bit in
CLRIRQX ($00C2H). This register is cleared to '0' on initialization by system reset.
When an interrupt occurs, CPU jumps to $FFFEH & $FFFFH to execute the interrupt service routine. When BASE TIMER
interrupt occurs and enters the interrupt service routine, the IRQTMR flag must be cleared by software.
Interrupt Control Register:
Addr.
Bit
7
6
5
4
3
2
1
0
$00C2
CLRIRQX
-
-
-
-
-
-
-
CLRIRQTMR
5
(W)
NT6868A
I/O Ports
The NT6868A has 31 pins dedicated to input and output. These pins are grouped into 6 ports, as follows:
PORT 0 (P00 - P07):
Port 0 is an 8-bit bi-directional CMOS I/O port that is internally pulled High by PMOS. Each pin of port 0 can be bit
programmed as an input or output pin under the software control. When programmed as output, data is latched to the port
data register and output to the pin. Port 0 pins with ''1'' written to them are pulled high by the internal PMOS pull-ups, and
are used as inputs in that state. These input signals can then be read. The port output is High after reset.
PORT 1 ( P10 - P17 ) : Functions the same as PORT 0.
PORT 2 ( P20 - P27) : Functions the same as PORT 0.
PORT 3 ( P30 - P34) : Functions the same as PORT 0.
CLK & DATA
: These two pins have the same structure as I/O ports, except for the 10KΩ internal pull-ups.
PORT Registers:
Addr.
Bit
7
6
5
4
3
2
1
0
$00C3
PORT0
PD07
PD06
PD05
PD04
PD03
PD02
PD01
PD00
(RW)
$00C4
PORT1
PD17
PD16
PD15
PD14
PD13
PD12
PD11
PD10
(RW)
$00C5
PORT2
PD27
PD26
PD25
PD24
PD23
PD22
PD21
PD20
(RW)
$00C6
PORT3
-
-
-
PD34
PD33
PD32
PD31
PD30
(RW)
$00C7
CLK
-
-
-
-
-
-
-
CLK
(RW)
$00C8
DATA
-
-
-
-
-
-
-
DATA
(RW)
VDD
Latch
Weak PMOS
WREN
L
IO
Q
DB
D
SD
RST
RDENB
IO Port Structure
6
NT6868A
LED Port
There are 3 LED direct sink pins which require no external serial resistors. The address is mapped to address $00C9.
Addr.
Bit
7
6
5
4
3
2
1
0
$00C9
LED
-
-
-
-
-
LED2
LED1
LED0
VDD
LED [ 0 ]
WREN
(W)
WREN
L
L
LED [ 1:2 ]
Q
Q
DB
DB
D
D
SD
RST
SD
RST
LED0 Port Structure
LED1, LED2 Port Structures
Watch-Dog Timer
NT6868A implements a watch-dog timer, which protects programs against system standstill. The clock of the watch-dog
timer is derived from the on-chip RC oscillator. The watch-dog timer interval is about 0.175 of a second. The timer must be
cleared within every 0.175 second during normal operation; otherwise, it will overflow and cause a system reset. The
watch-dog timer is cleared and enabled after a system reset. It cannot be disabled by software. The user can clear the
watch-dog timer by writing #55H to CLRWDT ($00CAH) register.
For example:
LDA
STA
#$55
$00CA
Addr.
Bit
7
6
5
4
3
2
1
0
$00CA
CLRWDT
0
1
0
1
0
1
0
1
(W)
Low Voltage Reset (LVR) Circuit
The NT6868A will check on the voltage level of power supply. When the voltage level of power supply is below a threshold
of 3.0V (Typical), the LVRC will issue a reset output to the chip until the power voltage level is above the threshold voltage
of 3.0V (Typical) again. As soon as the power voltage arises to 3.0V (Typical), the entire chip will be reset for about
150ms.
RESET
NT6868A can also be externally reset via RESET pin. A reset is initiated when the signal at the RESET pin is held Low
for at least 10 system clock. As soon as RESET signal goes high, the NT6868A begins to be reset for about 150ms. The
following shows the definition of RESET input low pulse width.
V DD
V DD
20%V DD
20%V DD
Trstb
7
NT6868A
Absolute Maximum Ratings*
*Comments
DC Supply Voltage . . . . . . . . . . . . . . . . . -0.3V to +7.0V
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
Input/Output Voltage . . . . . . . .GND -0.2V to VDD + 0.2V
Operating Ambient Temperature . . . . . . . .0°C to +70°C
Storage Temperature . . . . . . . . . . . . . .-55°C to +125°C
Operating Voltage (VDD) . . . . . . .. . . . . . . .+4.5V to 5.5V
DC Electrical Characteristics (VDD = 5V, GND = 0V, TA = 25°C, FOSC = 4MHz, unless otherwise specified)
Symbol
Parameter
ICC
Power Supply Current
VIH
Input High Voltage
VIL
Input Low Voltage
Min.
Typ.
Max.
Unit
20
mA
2
Conditions
No load
V
0.8
V
VOH1
Output High Voltage (Port 0, 1, 2,
3)
2.4
V
IOH = -100µA
VOH2
Output High Voltage (CLK, DATA)
2.4
V
IOH = -400µA
VOL1
Output Low Voltage (PORT 0, 1, 2)
0.4
V
IOL = 4mA
VOL2
Output Low Voltage (PORT 3)
0.4
V
IOL = 5mA
VOL3
Output Low Voltage (CLK, DATA)
0.4
V
IOL = 10mA
∆F/F
Initial Frequency Variation 1
+/-10
%
For RC OSC option
only; By Lots
∆F/F
Frequency Variation 2
+/-1
%
For ceramic resonator
option only; By Lots
ILED
LED Sink Current (LED 0, 1, 2)
17
mA
VLVR
Low Voltage Reset Threshold
TPOR
Power-on Reset Time
120
TRSTB
RESET Input Low Pulse Width
2.5
RPH
10
14
3.0
150
V
180
ms
µs
220
RESET Pull High Resistor
8
VOL = 3.2V
KΩ
10 system clocks
NT6868A
Application Circuit For Windows 98 Keyboard (for reference only)
VDD
4.7 - 10mf
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
P30
P31
VDD
VDD
GND
Scroll Lock
LED0
Num Lock
LED1
Caps Lock
LED2
0.1mf
RESET
Optional
NT6868A
DATA
KBD DATA
CLK
P20
P21
P22
P23
P24
P25
P26
P27
R0
S0
R1
Pause
KBD CLOCK
VDD
R/OSCO
47K (System clock can be decreased
by increasing the resistance)
R2
R3
Power
R4
R5
(R)
Ctrl
Sleep
R6
R7
Wake
Up
(L)
Ctrl
F5
!
1
@
2
A
Esc
Z
K131
~
,
Caps
Lock
S
(K45)
Macro
X
K132
F1
E
F3
D
F4
C
K133
F2
#
3
S4
R
T
F
G
V
B
%
5
$
4
S5
U
Y
J
H
M
N
^
6
&
7
S6
I
}
]
K
F6
<
,
K56
+
=
*
8
S7
O
F7
L
>
.
APP
F8
(
9
S8
P
{
[
:
;
|
\(K42)
?
/
-
)
0
S9
Scroll
Lock
S10
K14
S11
S1
Q
S2
W
S3
Tab
(L)
Alt
Back
Space
|
\(K29)
7
Home
4
1
End
8
5
2
S12
9
6
S13
PgUp
S14
+
S15
Wake
Up
"
'
(R)
Alt
F11
Enter
Space
Num
Lock
0
Ins
/
3
.
PgDn
Del
*
F12
-
Print
Screen
F9
F10
Delete
Power
Insert
Sleep
Page
Up
Page
Down
Home
End
(R)
S16
S17
K107
(L)
Enter
(R)
Shift
Shift
WINL
Kor_L
WINR
9
Kor_R
NT6868A
Application Circuit For Windows 2000 Standard Code
47K
S0
P15
S1
P30
S2
P31
S3
P00
S4
P01
S5
P02
S6
P03
S7
P04
S8
P13
S9
P14
S10
P12
S11
P10
S12
P07
S13
P06
S14
P05
S15
P11
S16
P16
S17
P17
S18
P32
R0
P20
R1
P21
R2
P22
R3
P23
R4
P24
R_OSC
Scroll Lock
LED 0
.1uF
Num Lock
LED 1
Caps Lock
LED 2
NT6868A/C
VDD
VDD
10uF
GND
GND
DATA
DATA
CLOCK
CLOCK
R5
P25
R6
P26
R7
P27
RESET
10
0.1uF
10
NT6868A
Key Matrix definition for Windows 2000 Standard Code
Power
Pause
126
Sleep
163
R-Ctrl
64
164
L-Ctrl
Wake Up
58
165
F5
116
S0
Q
Tab
17
A
16
W
31
Caps Lock
18
F3
114
R
20
F
21
Y
23
J
22
}
28
K
F7
25
27
40
13
"
41
;
Scroll Lock
|
42
'
55
L-Alt
125
7
9
8
12
S5
S6
(
9
_
/
S4
*
10
S7
)
11
-
R-Alt
60
8
119
?
\
4
F8
162
S3
&
=
App
.
5
+
56
S2
$
6
(K56)
,
54
:
[
7
>
39
{
26
53
L
118
P
117
3
^
51
<
4
5
N
52
F6
38
]
O
36
2
%
6
S1
#
113
50
M
3
F2
B
49
H
37
I
24
35
1
@
112
133
V
2
F1
(K133)
48
G
34
U
C
115
1
132
!
~
`
(K132)
47
F4
33
T
131
X
45
D
(K131)
46
(K45)
32
E
Z
110
S
30
19
Esc
0
S8
Print
124 Screen
62
S9
(K14)
Back Space
14
15
29
7
91
F11
|
\ (101)
4
(Home)
92
(
122
93
43
F12
F9
123
120
F10
121
S10
1
)
Enter
Space
(End)
Num Lock
61
Delete
90
84
76
Power
163
S11
8
96
(
5
)
97
2
(Num)
98
(
0
)
99
/
(Ins)
95
Insert
(Num)
89
75
Sleep
164
S12
9
101 (Page Up)
6
102 (
3
)
103 (Page Dn)
.
104
(Del)
*
100
(Num)
105
Page Up
(Num)
Page Down
85
86
S13
+
106
(Num)
(K107)
107
Wake Up
Enter
108
L-Shift
165
(Num)
R-Shift
44
57
83
Home
Media
180 Next
End
79
80
81
Media Play
Media Mute
Volume +
S14
Media
Previous
181
182
WWW
Search
188
WWW
Home
189
Media Stop
183
184
185
S15
L-Win
Volume 186
Kor_L
134
160
WWW
Forward
191
Media
Select
195
WWW Mail
187
R-Win
WWW Stop
161
192
Calculator
My
Computer
197
196
WWW
Refresh
193
WWW Back
190
WWW
Bookmark
194
S16
Kor_R
135
S17
S18
R7
R6
R5
R4
R3
R2
R1
R0
11
NT6868A
Bonding Diagram
P
1
7
P
1
6
P
1
5
P
1
4
P
1
3
P
1
2
P
1
1
P
1
0
P
0
7
P
0
6
26
25
24
23
22
21
20
19
18
17
16
P05
15
P04
P20
27
NT6868AH
14
P03
P21
28
Y
13
P02
P22
29
12
P01
P23
30
11
P00
RESET
(0, 0)
1752.6µm
X
P24
31
10
P25
32
9
P34
P26
33
8
P33
7
P32
6
P31
P27
34
LED0
35
LED1
36
37
38
39
40
1
L
E
D
2
V
R
/
O
S
C
O
O
S
C
I
G
N
D
D
D
2
3
4
5
N
C
D
A
T
A
C
L
K
P
3
0
1930.4µm
*Substrate Connect to VDD or Keep Floating
Pad No.
Designation
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
GND
NC
DATA
CLK
P30
P31
P32
P33
P34
RESET
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
X
-74.4
55.6
185.6
445.6
575.6
812.9
818.1
818.1
818.1
818.1
818.1
818.1
818.1
818.1
818.1
818.1
426.1
296.1
166.1
36.1
Y
-712.1
-727.5
-727.5
-727.5
-727.5
-728.1
-460.6
-330.6
-200.6
-70.6
59.4
189.4
319.4
449.4
579.4
721.9
727.5
727.5
727.5
727.5
12
unit: µm
Pad No.
Designation
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P12
P13
P14
P15
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
LED0
LED1
LED2
VDD
R/OSCO
OSCI
X
-93.9
-223.9
-353.9
-483.9
-613.9
-756.4
-818.2
-818.2
-818.2
-818.2
-818.2
-818.2
-818.2
-818.2
-818.2
-818.2
-594.4
-464.4
-334.4
-204.4
Y
727.5
727.5
727.5
727.5
727.5
727.5
519.3
389.3
259.3
129.3
-0.7
-130.7
-260.7
-390.7
-520.7
-666.8
-661.6
-661.6
-661.6
-661.6
NT6868A
Ordering Information
Part No.
NT6868AH
NT6868A
Package
CHIP FORM
40L DIP
Code Type No.
Oscillation Type
1
Built-in RC OSC
3
Ceramic Resonator
Function
Package Type
Windows 95 keyboard
DIP
NT6868A-0011
COB
NT6868AH-0046
DIP
NT6868A-10100
COB
NT6868AH-10088
Windows 98 keyboard
Order Information
13
NT6868A
Package Information
DIP 40L Outline Dimensions
unit: inches/mm
D
21
E1
40
1
20
E
A1
A2
Base Plane
Seating Plane
L
A
C
S
B
B1
α
e1
Symbol
Dimensions in inches
Dimensions in mm
A
0.210 Max.
5.33 Max.
A1
0.010 Min.
0.25 Min.
A2
0.155±0.010
3.94±0.25
B
0.018 +0.004
-0.002
0.46 +0.10
-0.05
B1
0.050 +0.004
-0.002
1.27 +0.10
-0.05
C
0.010 +0.004
-0.002
0.25 +0.10
-0.05
D
2.055 Typ. (2.075 Max.)
52.20 Typ. (52.71 Max.)
E
0.600±0.010
15.24±0.25
E1
0.550 Typ. (0.562 Max.)
13.97 Typ. (14.27 Max.)
e1
0.100±0.010
2.54±0.25
L
0.130±0.010
3.30±0.25
α
0° ~ 15°
0° ~ 15°
eA
0.655±0.035
16.64±0.89
S
0.093 Max.
2.36 Max.
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E1 does not include resin fins.
3. Dimension S includes end flash.
14
eA