INFINEON PEB2265

ICs for Communications
Two Channel Codec Filter with IOM®-2 Interface
(IOM®-2 – SICOFI®-2)
PEB 2265 Version 1.1
Preliminary Data Sheet 1997-07-01
T2265-XV11-P1-7600
PEB 2265
Revision History:
Current Version: 1997-07-01
Previous Version:
Page
Page
(in previous (in current
Version)
Version)
Subjects (major changes since last revision)
Edition 1997-07-01
HL TS,
Balanstraße 73,
81541 München
© Siemens AG 1997.
All Rights Reserved.
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Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express
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failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.
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PEB 2265
Table of Contents
Page
1
1.1
1.2
1.3
1.3.1
1.3.2
1.3.3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Pin Configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Pin Definition and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Common Pins for all Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Specific Pins for Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Specific Pins for Channel 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2
2.1
2.1.1
2.1.2
2.1.3
2.1.4
2.2
2.3
2.3.1
2.3.2
2.3.3
2.3.4
IOM®-2 – SICOFI®-2 Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
IOM®-2 – SICOFI®-2 Signal Flow Graph (for either channel) . . . . . . . . . .12
Transmit Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Receive Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Test Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
IOM®-2 – SICOFI®-2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
IOM®-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
IOM®-2 Interface Timing for 16 voice channels (per 8 kHz frame) . . . . . .15
IOM®-2 Interface Timing (DCL = 4096 kHz, MODE = 1, per 8 kHz frame) 15
IOM®-2 Interface Timing (DCL = 2048 kHz, MODE = 0) . . . . . . . . . . . . . .16
IOM®-2 Time-Slot Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3
3.1
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.4
3.5
3.5.1
3.5.2
3.5.3
3.5.4
3.6
Programming the IOM®-2 – SICOFI®-2 . . . . . . . . . . . . . . . . . . . . . . . . . .18
Types of Monitor Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
IOM®-2 – SICOFI®-2 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
SOP - Write Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
XOP - Write Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
COP - Write Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
SOP - Read Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
XOP - Read Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
COP - Read Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Example for a Mixed Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
SOP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
CR1 Configuration Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
CR2 Configuration Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
CR3 Configuration Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
CR4 Configuration Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
COP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
XOP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
XR1 Extended Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
XR2 Extended Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
XR3 Extended Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
XR4 Extended Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
SLIC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Semiconductor Group
3
1997-07-01
PEB 2265
Table of Contents
Page
3.7
3.8
3.8.1
3.8.2
3.8.3
3.9
3.9.1
3.9.2
3.9.3
3.9.4
3.9.5
3.9.6
IOM®-2 Interface Command/Indication Byte . . . . . . . . . . . . . . . . . . . . . . .38
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
RESET (Basic setting mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Programmable Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Impedance Matching Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Transhybrid Balancing (TH) Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Filters for Frequency Response Correction . . . . . . . . . . . . . . . . . . . . . . . .43
Amplification/Attenuation -Filters AX1, AX2, AR1, AR2 . . . . . . . . . . . . . .44
Amplification/Attenuation Receive (AR1, AR2)-Filter . . . . . . . . . . . . . . . .44
Amplification/Attenuation Transmit (AX1, AX2)-Filter . . . . . . . . . . . . . . . .44
4
4.1
QSICOS Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
QSICOS Supports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
5
5.1
5.1.1
5.1.2
5.2
5.2.1
5.2.2
5.2.3
5.3
5.4
5.5
5.6
5.7
5.8
5.8.1
5.8.2
5.9
5.10
Transmission Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Receive: reference frequency 1 kHz, input signal level 0 dBm0 . . . . . . . .48
Transmit: reference frequency 1 kHz, input signal level 0 dBm0 . . . . . . .48
Group Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Group Delay absolute values: Input signal level 0 dBm0 . . . . . . . . . . . . .49
Group Delay Distortion transmit: Input signal level 0 dBm0 . . . . . . . . . . .49
Group Delay Distortion receive: Input signal level 0dBm0 . . . . . . . . . . . .50
Out-of-Band Signals at Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Out-of-Band Signals at Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Out of Band Idle Channel Noise at Analog Output . . . . . . . . . . . . . . . . . .52
Overload Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Gain Tracking (receive or transmit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Total Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Total Distortion Measured with Sine Wave . . . . . . . . . . . . . . . . . . . . . . . .53
Total Distortion Measured with Noise According to CCITT . . . . . . . . . . . .54
Single Frequency Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Transhybrid Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
6
6.1
6.2
6.3
6.4
6.5
6.6
6.6.1
6.6.2
Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Analog Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
RESET Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
IOM®-2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
4 MHz Operation Mode (Mode = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2 MHz Operation Mode (Mode = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Semiconductor Group
4
1997-07-01
PEB 2265
Table of Contents
Page
6.7
6.7.1
6.7.2
6.8
6.8.1
IOM®-2 Command/Indication Interface Timing . . . . . . . . . . . . . . . . . . . . .61
4 MHz Operation Mode (Mode = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
2 MHz Operation Mode (Mode = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Detector Select Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
7
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.2
7.2.1
7.2.2
7.3
Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
IOM®-2 Interface Monitor Transfer Protocol . . . . . . . . . . . . . . . . . . . . . . .64
Monitor Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Monitor Handshake Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
State Diagram of the IOM®-2 – SICOFI®-2 Monitor Transmitter . . . . . . . .66
State Diagram of the IOM®-2 – SICOFI®-2 Monitor Receiver . . . . . . . . . .67
Monitor Channel Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Address Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Identification Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
IOM®-2 Interface Programming Procedure . . . . . . . . . . . . . . . . . . . . . . . .69
8
8.1
8.1.1
8.1.2
8.2
8.3
Test Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
The TAP-Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Level Metering Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Programming the IOM®-2 – SICOFI®-2 Tone Generators . . . . . . . . . . . .76
9
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
IOM®, IOM ®-1, IOM®-2, SICOFI®, SICOFI®-2, SICOFI®-4, SICOFI®-4µµC, SLICOFI®, ARCOFI®, ARCOFI®-BA,
ARCOFI®-SP, EPIC®-1, EPIC®-S, ELIC®, IPAT®-2, ITAC®, ISAC®-S, ISAC®-S TE, ISAC®-P, ISAC®-P TE, IDEC®,
SICAT®, OCTAT®-P, QUAT®-S are registered trademarks of Siemens AG.
MUSAC™-A, FALC™54, IWE™, SARE™, UTPT™, ASM™, ASP™ are trademarks of Siemens AG.
Purchase of Siemens I2C components conveys a license under the Philips’ I2C patent to use the components in
the I2C-system provided the system conforms to the I2C specifications defined by Philips. Copyright Philips 1983.
Semiconductor Group
5
1997-07-01
PEB 2265
Overview
1
Overview
The two Channel Codec Filter PEB 2265 IOM-2 – SICOFI-2 is the logic continuation of
a well-established family of Siemens Codec-Filter-ICs.
The IOM-2 – SICOFI-2 is a fully integrated PCM codec and filter fabricated in low power
1 µm CMOS technology for applications in digital communication systems. Based on an
advanced digital filter concept, the PEB 2265 provides excellent transmission
performance and high flexibility. The new filter concept (second generation) lends to a
maximum of independence between the different filter blocks. Each filter block can be
seen like an one to one representative of the corresponding network element.
Only very few external components are needed, to complete the functionality of the
IOM-2 – SICOFI-2. The internal level accuracy is based on a very accurate bandgap
reference. The frequency behavior is mainly determined by digital filters, which do not
have any fluctuations. As a result of the new ADC and DAC concepts linearity is only
limited by second order parasitic effects. Although the device works with only one single
5-V supply there is a very good dynamic range available.
Semiconductor Group
6
1997-07-01
Two Channel Codec Filter with IOM®-2 Interface
IOM®-2 – SICOFI®-2
1.1
PEB 2265
Features
• Single chip CODEC and FILTER to handle two
CO- or PABX-channels
• Specification according to relevant CCITT, EIA and
LSSGR recommendations
• Digital signal processing technique
• Programmable interface optimized to current feed
SLICs and transformer solutions
P-MQFP-64-1-2
• Four pin serial IOM-2 Interface
• Single power supply 5 V
• Advanced low power 1µm analog CMOS technology
• Standard 64-pin P-MQFP-64 package
• High performance Analog to Digital Conversion
• High performance Digital to Analog Conversion
• Programmable digital filters to adapt the transmission behavior especially for
– AC impedance matching
– transhybrid balancing
– frequency response
– gain
• Advanced test capabilities
– all digital pins can be tested within a boundary scan scheme (IEEE 1149.1)
– five digital loops
– four analog loops
– two programmable tone generators per channel
• Comprehensive development platform available
– software for automatic filter coefficient calculation – QSICOS
– Hardware development board – STUT 2465
Type
Ordering Code
Package
PEB 2265 H V1.1
on request
P-MQFP-64-1-2
Semiconductor Group
7
1997-07-01
PEB 2265
Overview
1.2
Pin Configuration (top view)
N.C.
N.U.I.
N.U.I.
N.U.I.
N.U.IO.
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
16
33
N.U.IO.
34
15
N.C.
35
14
N.C.
36
13
N.C.
37
12
N.C.
38
11
39
10
40
IOM2-SICOFI-2
N.C.
9
8
N.C.
42
7
N.C.
43
6
44
5
45
4
N.C.
N.C.
46
3
N.C.
47
2
N.C.
41
48
1
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
N.U.IO.
N.U.IO.
N.U.I.
N.U.I.
N.U.I.
Figure 1
Semiconductor Group
8
1997-07-01
PEB 2265
Overview
1.3
Pin Definition and Functions
1.3.1
Common Pins for all Channels
Table 1
Pin No.
Symbol
Input (I)
Function
Output (O)
23
VDDD
I
+ 5 V supply for the digital circuitry1)
58
GNDD
I
Ground Digital, not internally connected to GNDA
1, 2 or GNDA (pin 6 and pin 11). All digital signals
are referred to this pin
40
VDDA12
I
+ 5 V Analog supply voltage for channel 1 and 21)
9
VDDA
I
+ 5 V Analog supply voltage1)
6,11
GNDA
I
Ground Analog, not internally connected to GNDD
or GNDA1,2
27
FSC
I
IOM-2: Frame synchronization clock, 8 kHz
26
DCL
I
IOM-2: Data clock, 2048 kHz or 4096 kHz
depending on MODE
25
DU
O
IOM-2: Data upstream, open drain output
24
DD
I
IOM-2: Data downstream, input
22
RESET
I
Reset input - forces the device to the default mode,
active high
57
MODE
I
IOM-2: Mode Selection
60
TSS0
I
IOM-2: Time slot selection pin 0
59
TSS1
I
IOM-2: Time slot selection pin 1
56
TCK
I
Boundary scan: Test Clock
55
TMS
I
Boundary scan: Test Mode Select
54
TDI
I
Boundary scan: Test Data Input
53
TDO
O
Boundary scan: Test Data Output
28
LGKM0
O
Loop/Ground Key Multiplexing output 0 for
channel 1, 2
41
VH12
I/O
Reference voltage for channel 1 and 2, has to be
connected via a 220 nF cap. to ground
I
None Usable Input, tie directly to Digital Ground
18,19,20 N.U.I.
61,62,63
Semiconductor Group
9
1997-07-01
PEB 2265
Overview
Table 1
(cont’d)
Pin No.
Symbol
Input (I)
Function
Output (O)
1,16
17,64
N.U.IO.
I/O
2,3,4,5,7 N.C.
8,10,12
13,14,15
21
1)
None Usable Input/Output, tie via a
Pull-Down-Resistor to Digital Ground
not connected
A 100 nF cap. should be used for blocking these pin.
1.3.2
Specific Pins for Channel 1
Table 2
Pin No. Symbol
Input (I)
Output (O)
Function
38
GNDA1
I
Ground Analog for channel 1, not internally
connected to GNDD or GNDA2 or GNDA (pin 6 and
pin 11)
39
VIN1
I
Analog voice (voltage) input for channel 1
37
VOUT1
O
Analog voice (voltage) output for channel 1
31
SI1_0
I
Signaling indication input pin 0 for channel 1
30
SI1_1
I
Signaling indication input pin 1 for channel 1
29
SI1_2
I
Signaling indication input pin 2 for channel 1
36
SO1_0
O
Signaling command output pin 0 for channel 1
35
SO1_1
O
Signaling command output pin 1 for channel 1
34
SO1_2
O
Signaling command output pin 2 for channel 1
33
SB1_0
I/O
Bi-directional signal. Command indication pin 0 for
channel 1
32
SB1_1
I/O
Bi-directional signal. Command indication pin 1 for
channel 1
Semiconductor Group
10
1997-07-01
PEB 2265
Overview
1.3.3
Specific Pins for Channel 2
Table 3
Pin No. Symbol
Input (I)
Output (O)
Function
43
GNDA2
I
Ground Analog for channel 2, not internally
connected to GNDD or GNDA1 or GNDA (pin 6 and
pin 11)
42
VIN2
I
Analog voice (voltage) input for channel 2
44
VOUT2
O
Analog voice (voltage) output for channel 2
50
SI2_0
I
Signaling indication input pin 0 for channel 2
51
SI2_1
I
Signaling indication input pin 1 for channel 2
52
SI2_2
I
Signaling indication input pin 2 for channel 2
45
SO2_0
O
Signaling command output pin 0 for channel 2
46
SO2_1
O
Signaling command output pin 1 for channel 2
47
SO2_2
O
Signaling command output pin 2 for channel 2
48
SB2_0
I/O
Bi-directional signal. command indication pin 0 for
channel 2
49
SB2_1
I/O
Bi-directional signal. command indication pin 1 for
channel 2
Semiconductor Group
11
1997-07-01
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IOM®-2 – SICOFI®-2 Principles
2
IOM®-2 – SICOFI®-2 Principles
The change from 2 µm to 1 µm CMOS process requires new concepts in the realization
of the analog functions. High performance (in the terms of gain, speed, stability …) 1 µm
CMOS devices can not withstand more than 5.5 V of supply voltage. On that account the
negative supply voltage VSS of the previous SICOFIs will be omitted. This is a benefit for
the user but it makes a very high demand on the analog circuitry.
ADC and DAC are changed to Sigma-Delta-concepts to fulfill the stringent requirements
on the dynamic parameters.
Using 1 µm CMOS does not only lend to problems – it is the only acceptable solution in
terms of area and power consumption for the integration of more then two SICOFI
channels on a single chip.
It is rather pointless to implement 2 codec-filter-channels on one chip with pure analog
circuitry. The use of a DSP-concept (the SICOFI and the SICOFI-2-approach) for this
function seems to be a must for an adequate two channel architecture.
2.1
IOM®-2 – SICOFI®-2 Signal Flow Graph (for either channel)
Figure 2
Semiconductor Group
12
1997-07-01
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IOM®-2 – SICOFI®-2 Principles
2.1.1
Transmit Path
The analog input signal has to be DC-free connected by an external capacitor because
there is an internal virtual reference ground potential. After passing a simple antialiasing
prefilter (PREFI) the voice signal is converted to a 1-bit digital data stream in the
Sigma-Delta-converter. The first downsampling steps are done in fast running digital
hardware filters. The following steps are implemented in the micro-code which has to be
executed by the central Digital Signal Processor. This DSP-machine is able to handle
the workload for all two channels. At the end the fully processed signal (flexibly
programmed in many parameters) is transferred to the IOM-2 interface in a
PCM-compressed signal representation.
2.1.2
Receive Path
The digital input signal is received via the IOM-2 interface. Expansion,
PCM-law-pass-filtering, gain correction and frequency response correction are the next
steps which are done by the DSP-machine. The upsampling interpolation steps are
again processed by fast hardware structures to reduce the DSP-workload. The
upsampled 1-bit data stream is then converted to an analog equivalent which is
smoothed by a POST-Filter (POFI). As the signal VOUT is also referenced to an internal
virtual ground potential, an external capacitor is required for DC-decoupling.
2.1.3
Loops
There are two loops implemented. The first is to generate the AC-input impedance (IM)
and the second is to perform a proper hybrid balancing (TH). A simple extra path IM2
(from the transmit to the receive path) supports the impedance matching function.
2.1.4
Test Features
There are four analog and five digital test loops implemented in the IOM-2 – SICOFI-2.
For special tests it is possible to “Cut Off” the receive and the transmit path at two
different points.
Semiconductor Group
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1997-07-01
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IOM®-2 – SICOFI®-2 Principles
Analog out
DAC
Analog in
ADC
Command
Indication
Signaling
DSP
IOM2-Interface
IOM2-Bus
HW-Filter
IOM®-2 – SICOFI®-2 Block Diagram
HW-Filter
2.2
DAC
Analog out
ADC
Analog in
Signaling
Command
Indication
iom3.wmf
Figure 3
The IOM-2 – SICOFI-2 bridges the gap between analog and digital voice signal
transmission in modern telecommunication systems. High performance oversampling
Analog-to-Digital Converters (ADC) and Digital-to-Analog Converters (DAC) provide the
required conversion accuracy. Analog antialiasing prefilters (PREFI) and smoothing
postfilters (POFI) are included. The connection between the ADC and the DAC (with
high sampling rate) and the DSP, is done by specific Hardware Filters, for filtering like
interpolation and decimation. The dedicated Digital Signal Processor (DSP) handles all
the algorithms necessary e.g. for PCM bandpass filtering, sample rate conversion and
PCM companding. The IOM-2 Interface handles digital voice transmission,
IOM-2 – SICOFI-2 feature control and transparent access to the IOM-2 – SICOFI-2
command and indication pins. To program the filters, precalculated sets of coefficients
are downloaded from the system to the on chip coefficient ram (CRAM).
2.3
IOM®-2 Interface
The IOM-2 Interface consists of two data lines and two clock lines. DU (data upstream)
carries data from the IOM-2 – SICOFI-2 to a master device. This master device performs
the interface between the PCM-backplane, the µController and up to
24 IOM-2 – SICOFI-2's. DD (data downstream) carries data from the master device to
the IOM-2-SICOF-2. A frame synchronization clock signal (8 kHz, FSC) as well as a data
clock signal (2048 kHz or 4096 kHz DCL) has to be supplied to the IOM-2 – SICOFI-2.
The IOM-2 – SICOFI-2 handles data as described in the IOM-2 specification for analog
devices.
Semiconductor Group
14
1997-07-01
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IOM®-2 – SICOFI®-2 Principles
2.3.1
IOM®-2 Interface Timing for 16 voice channels (per 8 kHz frame)
Figure 4
2.3.2
IOM®-2 Interface Timing (DCL = 4096 kHz, MODE = 1, per 8 kHz frame)
Figure 5
Semiconductor Group
15
1997-07-01
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IOM®-2 – SICOFI®-2 Principles
2.3.3
IOM®-2 Interface Timing (DCL = 2048 kHz, MODE = 0)
Figure 6
2.3.4
IOM®-2 Time Slot Selection
The two channels (1 and 2) of the IOM-2 – SICOFI-2 can be assigned to 4 time slots by
pin-strapping the pins TSS0 and TSS1 (TS0, TS2, TS4, TS6). The IOM-2 operating
mode is selected by the MODE pin.
Table 4
TSS1
TSS0
MODE
IOM®-2 Operating Mode
0
0
1
Time slot 0; DCL= 4096 kHz
0
1
1
Time slot 2; DCL= 4096 kHz
1
0
1
Time slot 4; DCL= 4096 kHz
1
1
1
Time slot 6; DCL= 4096 kHz
0
0
0
Time slot 0; DCL= 2048 kHz
0
1
0
Time slot 2; DCL= 2048 kHz
1
0
0
Time slot 4; DCL= 2048 kHz
1
1
0
Time slot 6; DCL= 2048 kHz
Semiconductor Group
16
1997-07-01
PEB 2265
IOM®-2 – SICOFI®-2 Principles
Each IOM time slot contains 2 voice channels (A and B). Those two voice channels
share a common IOM-Monitor-byte as well as a common C/I-byte. The AD-bit in the
Monitor command defines which of the two voice channels should be affected
(programmed). (For more information on IOM-2 specific Monitor Channel Data Structure
see appendix, page 64).
Figure 7
Table 5
TSS1 = 0,
TSS0 = 0
IOM®-2 – SICOFI®-2 TS
Channels
TSS1 = 0,
TSS0 = 1
Voice
TS
Channel
TSS1 = 1,
TSS0 = 0
Voice
TS
Channel
TSS1 = 1,
TSS0 = 1
Voice
TS
Channel
Voice
Channel
1
TS0 A
TS2 A
TS4 A
TS6 A
2
TS0 B
TS2 B
TS4 B
TS6 B
Semiconductor Group
17
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Programming the IOM®-2 – SICOFI®-2
Programming the IOM®-2 – SICOFI®-2
3
With the appropriate commands, the IOM-2 – SICOFI-2 can be programmed and
verified very flexibly via the IOM-2 Interface monitor channel.
Data transfer to the IOM-2 – SICOFI-2 starts with a SICOFI-specific address byte (81H).
With the second byte one of 3 different types of commands (SOP, XOP and COP) is
selected. Each of those can be used as a write or read command. Due to the extended
IOM-2 – SICOFI-2 feature control facilities, SOP, COP and XOP commands contain
additional information (e.g. number of subsequent bytes) for programming (write) and
verifying (read) the IOM-2 – SICOFI-2 status.
A write command is followed by up to 8 bytes of data. The IOM-2 – SICOFI-2 responds
to a read command with its IOM-2 specific address and the requested information, that
is up to 8 bytes of data (see programming Procedure, page 18).
Attention: Each byte on the monitor channel, has to be sent twice at least, according to
the IOM-2 Monitor handshake procedure (For more information on IOM-2 specific
Monitor Channel Data Structure see appendix, page 64).
3.1
Types of Monitor Bytes
The 8-bit Monitor Bytes have to be interpreted as either commands or status information
stored in Configuration Registers or the Coefficient RAM. There are three different types
of IOM-2 – SICOFI-2 commands which are selected by bit 3 and 4 as shown below.
SOP
Bit
XOP
Bit
STATUS OPERATION:
7
6
5
Bit
4
3
1
0
EXTENDED OPERATIO:
7
6
5
X
COP
IOM-2 – SICOFI-2 status
setting/monitoring
6
5
1
0
C/I channel configuration/evaluation
4
3
1
1
COEFFICIENT OPERATION:
7
2
2
1
0
filter coefficient setting/monitoring
4
3
2
1
0
0
Semiconductor Group
18
1997-07-01
PEB 2265
Programming the IOM®-2 – SICOFI®-2
Storage of Programming Information:
4 configuration registers per channel: CR1, CR2, CR3, CR4 accessed by SOP
commands
4 common configuration registers:
XR1, XR2, XR3 and XR4 accessed by XOP
commands (the contents are valid for two voice
channels i.e. 1 IOM-2 time slot)
1 coefficient RAM per channel:
CRAM accessed by COP commands
3.2
IOM®-2 – SICOFI®-2 Commands
3.2.1
SOP - Write Commands
DD
7 6 5 4 3 2 1 0 Bit
Address
1 0 0 0 0 0 0 1
SOP-Write 1 Byte
0
CR1
Idle
Data
Idle
7 6 5 4 3 2 1 0 Bit
Address
1 0 0 0 0 0 0 1
0
7 6 5 4 3 2 1 0
Idle
CR2
Data
Idle
CR1
Data
Idle
7 6 5 4 3 2 1 0 Bit
Address
1 0 0 0 0 0 0 1
SOP-Write 3 Bytes
7 6 5 4 3 2 1 0
Idle
CR3
Data
Idle
CR2
Data
Idle
CR1
Data
Idle
19
0
DU
Idle
1 0 0 1 1
Semiconductor Group
0
DU
Idle
1 0 0 1 0
DD
DU
Idle
1 0 0 0 1
DD
SOP-Write 2 Bytes
7 6 5 4 3 2 1 0
1997-07-01
PEB 2265
Programming the IOM®-2 – SICOFI®-2
DD
7 6 5 4 3 2 1 0 Bit
Address
1 0 0 0 0 0 0 1
SOP-Write 4 Bytes
3.2.2
0
7 6 5 4 3 2 1 0 DU
Idle
1 0 1 0 0
Idle
CR4
Data
Idle
CR3
Data
Idle
CR2
Data
Idle
CR1
Data
Idle
XOP - Write Commands
DD
7 6 5 4 3 2 1 0 Bit
Address
1 0 0 0 0 0 0 1
XOP-Write 2 Bytes
0
7 6 5 4 3 2 1 0
Idle
1 1 0 1 0
Idle
XR2
Data
Idle
XR1
Data
Idle
DD
7 6 5 4 3 2 1 0 Bit
Address
1 0 0 0 0 0 0 1
XOP-Write 3 Bytes
7 6 5 4 3 2 1 0
Idle
XR3
Data
Idle
XR2
Data
Idle
XR1
Data
Idle
20
DU
Idle
1 1 0 1 0
Semiconductor Group
0
DU
1997-07-01
PEB 2265
Programming the IOM®-2 – SICOFI®-2
3.2.3
COP - Write Commands
DD
7 6 5 4 3 2 1 0 Bit
Address
1 0 0 0 0 0 0 1
COP-Write 4 Bytes
0
7 6 5 4 3 2 1 0
Idle
0 1
Idle
Coeff. 4
Data
Idle
Coeff. 3
Data
Idle
Coeff. 2
Data
Idle
Coeff. 1
Data
Idle
DD
7 6 5 4 3 2 1 0 Bit
Address
1 0 0 0 0 0 0 1
COP-Write 8 Bytes
7 6 5 4 3 2 1 0
Idle
Coeff. 8
Data
Idle
Coeff. 7
Data
Idle
Coeff. 6
Data
Idle
Coeff. 5
Data
Idle
Coeff. 4
Data
Idle
Coeff. 3
Data
Idle
Coeff. 2
Data
Idle
Coeff. 1
Data
Idle
21
DU
Idle
0 0
Semiconductor Group
0
DU
1997-07-01
PEB 2265
Programming the IOM®-2 – SICOFI®-2
3.2.4
SOP - Read Commands
DD
7 6 5 4 3 2 1 0 Bit
Address
1 0 0 0 0 0 0 1
SOP-Read 1 Byte
1
1 0 0 0 1
Idle
7 6 5 4 3 2 1 0 Bit
Address
1 0 0 0 0 0 0 1
1 0 0 1 0
Idle
Idle
Idle
Idle
Data
CR1
1 0 0 1 1
Idle
7 6 5 4 3 2 1 0
DU
Idle
Idle
1 0 0 0 0 0 0 1 Address
Idle
Data
CR3
Idle
Data
CR2
Idle
Data
CR1
DD
7 6 5 4 3 2 1 0 Bit
Address
1 0 0 0 0 0 0 1
1 0 1 0 0
Idle
Semiconductor Group
DU
CR2
1 0 0 0 0 0 0 1
1
7 6 5 4 3 2 1 0
Data
Address
SOP-Read 4 Bytes
CR1
Idle
7 6 5 4 3 2 1 0 Bit
1
Idle
1 0 0 0 0 0 0 1 Address
DD
SOP-Read 3 Bytes
Idle
Data
DD
1
DU
1 0 0 0 0 0 0 1 Address
Idle
SOP-Read 2 Bytes
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
DU
Idle
Idle
1 0 0 0 0 0 0 1 Address
Idle
Data
CR4
Idle
Data
CR3
Idle
Data
CR2
Idle
Data
CR1
22
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Programming the IOM®-2 – SICOFI®-2
3.2.5
XOP - Read Commands
DD
7 6 5 4 3 2 1 0 Bit
Address
1 0 0 0 0 0 0 1
XOP-Read 1 Byte
1
1 1 0 0 1
Idle
7 6 5 4 3 2 1 0 Bit
Address
1 0 0 0 0 0 0 1
1 1 0 1 0
Idle
7 6 5 4 3 2 1 0 DU
Idle
Idle
Data
XR2
Idle
Data
XR1
Address
1 0 0 0 0 0 0 1
1 1 0 1 1
Idle
Semiconductor Group
XR1
Idle
7 6 5 4 3 2 1 0 Bit
1
Idle
1 0 0 0 0 0 0 1 Address
DD
XOP-Read 3 Bytes
Idle
Data
DD
1
DU
1 0 0 0 0 0 0 1 Address
Idle
XOP-Read 2 Bytes
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
DU
Idle
Idle
1 0 0 0 0 0 0 1 Address
Idle
Data
XR3
Idle
Data
XR2
Idle
Data
XR1
23
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Programming the IOM®-2 – SICOFI®-2
3.2.6
COP - Read Commands
DD
7 6 5 4 3 2 1 0 Bit
Address
1 0 0 0 0 0 0 1
COP-Read 4 bytes
1
0 1
Idle
Data
Coeff.4
Idle
Data
Coeff.3
Idle
Data
Coeff.2
Idle
Data
Coeff.1
7 6 5 4 3 2 1 0 Bit
Address
1 0 0 0 0 0 0 1
0 0
7 6 5 4 3 2 1 0
DU
Idle
Idle
Idle
Semiconductor Group
Idle
1 0 0 0 0 0 0 1 Address
DD
1
DU
Idle
Idle
COP-Read 8 Bytes
7 6 5 4 3 2 1 0
1 0 0 0 0 0 0 1 Address
Idle
Data
Coeff.8
Idle
Data
Coeff.7
Idle
Data
Coeff.6
Idle
Data
Coeff.5
Idle
Data
Coeff.4
Idle
Data
Coeff.3
Idle
Data
Coeff.2
Idle
Data
Coeff.1
24
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Programming the IOM®-2 – SICOFI®-2
3.2.7
Example for a Mixed Command
DD
7 6 5 4 3 2 1 0 Bit
Address
1 0 0 0 0 0 0 1
SOP-Write 4 Bytes
Idle
CR4
Data
Idle
CR3
Data
Idle
CR2
Data
Idle
CR1
Data
Idle
1 1 0 1 0
Idle
XR2
Data
Idle
XR1
Data
Idle
0 1
Idle
Coeff. 4
Data
Idle
Coeff. 3
Data
Idle
Coeff. 2
Data
Idle
Coeff. 1
Data
Idle
1 0 0 1 1
Idle
COP-Write 4 Bytes
SOP-Read 3 Bytes
0
0
1
Idle
Address
COP-Read 4 Bytes
1 0 0 0 0 0 0 1 Address
Idle
Data
CR3
Idle
Data
CR2
Idle
Data
CR1
1 0 0 0 0 0 0 1
Idle
1
0 1
Idle
Idle
Address
XOP-Read 1 Byte
1 0 0 0 0 0 0 1 Address
Idle
Data
Coeff.4
Idle
Data
Coeff.3
Idle
Data
Coeff.2
Idle
Data
Coeff.1
1 0 0 0 0 0 0 1
Idle
1
1 1 0 0 1
Idle
Idle
1 0 0 0 0 0 0 1 Address
Idle
Semiconductor Group
DU
Idle
1 0 1 0 0
XOP-Write 2 Bytes
0
7 6 5 4 3 2 1 0
Data
25
XR1
1997-07-01
PEB 2265
Programming the IOM®-2 – SICOFI®-2
3.3
SOP Command
To modify or evaluate the IOM-2 – SICOFI-2IOM-2 – SICOFI-2 status, the contents of
up to four configuration registers CR1, CR2, CR3 and CR4 may be transferred to or from
the IOM-2 – SICOFI-2. This is started by a SOP-Command (status operation command).
Bit
7
6
5
4
3
2
1
0
AD
RW
PWRUP
1
0
LSEL2
LSEL1
LSEL0
AD
Address Information
AD = 0
IOM-2 – SICOFI-2 channel 1 is addressed with
this cmd.
AD = 1
IOM-2 – SICOFI-2 channel 2 is addressed with
this cmd.
RW
Read/Write Information: Enables reading from the IOM-2 – SICOFI-2
or writing information to the IOM-2 – SICOFI-2
RW = 0
Write to IOM-2 – SICOFI-2
RW = 1
Read from IOM-2 – SICOFI-2
PWRUP
Power Up / Power Down
PWRUP = 1
sets the assigned channel (see bit AD) of
IOM-2 – SICOFI-2 to power-up (operating mode)
PWRUP = 0
resets the assigned channel of
IOM-2 – SICOFI-2 to power-down (standby mode)
LSEL
Length select information (see also programming procedure)
This field identifies the number of subsequent data bytes
LSEL = 000
0 bytes of data are following
LSEL = 001
1 byte of data is following (CR1)
LSEL = 010
2 bytes of data are following (CR2, CR1)
LSEL = 011
3 bytes of data are following (CR3, CR2, CR1)
LSEL = 100
4 bytes of data are following (CR4, CR3, CR2, CR1)
All other codes are reserved for future use!
It is possible to program each configuration register separately, just by putting only one
byte into the FIFO of the upstream master device (e.g. EPIC), and aborting after
transmission of one (or n) byte.
Semiconductor Group
26
1997-07-01
PEB 2265
Programming the IOM®-2 – SICOFI®-2
3.3.1
CR1 Configuration Register 1
Configuration register CR1 defines the basic IOM-2 – SICOFI-2 settings, which are:
enabling/disabling the programmable digital filters and tone generators.
Bit
TH
IM/R1
FRX
FRR
AX
AR
ETG2
ETG1
1)
7
6
5
4
3
2
1
0
TH
IM/R1
FRX
FRR
AX
AR
ETG2
ETG1
Enable TH- (Trans Hybrid Balancing) Filter
TH = 0:
TH-filter disabled
TH = 1:
TH-filter enabled
Enable IM-(Impedance Matching) Filter and R1-Filter
IM/R1 = 0:
IM-filter and R1-filter disabled
IM/R1 = 1:
IM-filter and R1-filter enabled
Enable FRX (Frequency Response Transmit)-Filter
FRX = 0:
FRX-filter disabled
FRX = 1:
FRX-filter enabled
Enable FRR (Frequency Response Receive)-Filter
FRR = 0:
FRR-filter disabled
FRR = 1:
FRR-filter enabled
Enable AX-(Amplification/Attenuation Transmit) Filter
AX = 0:
AX-filter disabled
AX = 1:
AX-filter enabled
Enable AR-(Amplification/Attenuation Receive) Filter
AR = 0:
AR-filter disabled
AR = 1:
AR-filter enabled
Enable programmable tone generator 21)
ETG2 = 0:
programmable tone generator 2 is disabled
ETG2 = 1:
programmable tone generator 2 is enabled
Enable programmable tone generator 1
ETG1 = 0:
programmable tone generator 1 is disabled
ETG1 = 1:
programmable tone generator 1 is enabled
Tone generator 2 is not available if Level Metering Function is enabled!
Semiconductor Group
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Programming the IOM®-2 – SICOFI®-2
3.3.2
Bit
CR2 Configuration Register 2
7
6
TH-Sel
TH-Sel
5
4
3
2
1
0
LM
LMR
LAW
LIN
PTG2
PTG1
2 bit field to select one of two programmed TH-filter coefficient sets
TH-Sel = 0 0: TH-filter coefficient set 1 is selected
TH-Sel = 0 1: TH-filter coefficient set 2 is selected
LM
LMR
LAW
LIN
PTG2
PTG1
1)
2)
Level Metering function1)
LM = 0:
level metering function is disabled
LM = 1:
level metering function is enabled
Result of Level Metering function (this bit can not be written)
LMR = 0:
level detected was lower than the reference
LMR = 1:
level detected was higher than the reference
PCM - law selection
LAW = 0:
A-Law is selected
LAW = 1:
µ-Law (µ255 PCM) is selected
Linear mode selection
LIN = 0:
PCM-mode is selected
LIN = 1:
linear mode is selected2)
User programmed frequency or fixed frequency is selected
PTG2 = 0:
fixed frequency for tone generator 2 is selected (1 kHz)
PTG2 = 1:
programmed frequency for tone generator 2 is selected
User programmed frequency or fixed frequency is selected
PTG1 = 0:
fixed frequency for tone generator 1 is selected (1 kHz)
PTG1 = 1:
programmed frequency for tone generator 1 is selected
Explanation of the level metering function:
A signal fed to A/µ-Law compression via AX- and HPX-filters (from a digital loop, or externally via VIN), is
rectified, and the power is measured. If the power exceeds a certain value, loaded to XR4, bit LMR is set to
‘1’. The power of the incoming signal can be adjusted by AX-filters.
During Linear operation only one 16 bit voice channel, is available per time slot. Depending on the address bit
(AD) the voice-data of channel 1 or 2 is transmitted. The other voice channel is not available during this time.
Semiconductor Group
28
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Programming the IOM®-2 – SICOFI®-2
3.3.3
Bit
CR3 Configuration Register 3
7
6
5
COT/R
COT/R
IDR
4
3
0
IDR
2
1
0
Version
Selection of Cut Off Transmit/Receive Paths
0 0 0:
Normal Operation
0 0 1:
COT_16K
Cut Off Transmit Path at 16 kHz
(input of TH-Filter)
0 1 0:
COT_PCM
Cut Off Transmit Path at 8 kHz
(input of compression)
(output is zero for µ-law and linear mode,
1 LSB for A-law)
1 0 1:
COR_PFI
Cut Off Receive Path at 4 MHz
(POFI-output)
1 1 0:
COR_64K
Cut Off Receive Path at 64 kHz
(IM-filter input)
Initialize Data RAM
IDR = 0:
Normal operation is selected
IDR = 1:
Contents of Data RAM is set to 0
(used for production test purposes)
Version
The Version number shows the actual design version of
IOM-2-SICOFI-2 (100 for PEB 2265 V1.1)
Semiconductor Group
29
1997-07-01
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Programming the IOM®-2 – SICOFI®-2
Figure 8
CUT OFF‘s’ and Loops
Semiconductor Group
30
1997-07-01
PEB 2265
Programming the IOM®-2 – SICOFI®-2
3.3.4
Bit
CR4 Configuration Register 4
7
6
5
4
Test-Loops
Test-Loops
AGR
D-HPX
2
1
0
AGX
AGR
D-HPX
D-HPR
4 bit field for selection of Analog and Digital Loop Backs
0 0 0 0:
AGX
3
no loop back is selected (normal operation)
0 0 0 1:
ALB-PFI
analog loop back via PREFI-POFI is selected
0 0 1 1:
ALB-4M
analog loop back via 4 MHz is selected
0 1 0 0:
ALB-PCM analog loop back via 8 kHz (PCM) is selected
0 1 0 1:
ALB-8K
1 0 0 0:
DLB-ANA digital loop back via analog port is selected
1 0 0 1:
DLB-4M
1 1 0 0:
DLB-128K digital loop back via 128 kHz is selected
1 1 0 1:
DLB-64K
1 1 1 1:
DLB-PCM digital loop back via PCM-registers is
selected
analog loop back via 8 kHz (linear) is
selected
digital loop back via 4 MHz is selected
digital loop back via 64 kHz is selected
Analog gain in transmit direction
AGX = 0:
analog gain is disabled
AGX = 1:
analog gain is enabled (6,02dB amplification)
Analog gain in receive direction
AGR = 0:
analog gain is disabled
AGR = 1:
analog gain is enabled (6,02dB attenuation)
Disable highpass in transmit direction
D-HPX = 0: transmit high pass is enabled
D-HPX = 1: transmit high pass is disabled 1)
D-HPR
Disable highpass in receive direction
D-HPR = 0: receive high pass is enabled
D-HPR = 1: receive high pass is disabled 2)
1)
2)
In this case the transmit-path signal is attenuated 0.06 dB
In this case the receive-path signal is attenuated 0.12 dB
Semiconductor Group
31
1997-07-01
PEB 2265
Programming the IOM®-2 – SICOFI®-2
3.4
COP Command
With a COP Command coefficients for the programmable filters can be written to the
IOM-2 – SICOFI-2 Coefficient RAM or read from the Coefficient RAM via the IOM-2
interface for verification
Bit
7
6
5
4
3
2
1
0
AD
RW
RST
0
CODE3
CODE2
CODE1
CODE0
AD
Address
AD = 0
AD = 1
IOM-2 – SICOFI-2 channel 1 is addressed
IOM-2 – SICOFI-2 channel 2 is addressed
RW
Read/Write
RW = 0
Subsequent data is written to the IOM-2 – SICOFI-2
RW = 1
Read data from IOM-2 – SICOFI-2
RST
Reset
RST = 1
CODE
Reset IOM-2 – SICOFI-2
(same as RESET-Pin, valid for all two channels)
includes number of following bytes and filter-address
0
0
0
0 TH-Filter coefficients (part 1)
(followed by 8 bytes of data)
0
0
0
1 TH-Filter coefficients (part 2)
(followed by 8 bytes of data)
0
0
1
0 TH-Filter coefficients (part3)
(followed by 8 bytes of data)
0
1
0
0 IM-Filter coefficients (part1)
(followed by 8 bytes of data)
0
1
0
1 IM-Filter coefficients (part2)
(followed by 8 bytes of data)
0
1
1
0 FRX-Filter coefficients
(followed by 8 bytes of data)
0
1
1
1 FRR-Filter coefficients
(followed by 8 bytes of data)
1
0
0
0 AX-Filter coefficients
(followed by 4 bytes of data)
1
0
0
1 AR-Filter coefficients
(followed by 4 bytes of data)
1
1
0
0 TG1-Filter coefficients
(followed by 4 bytes of data)
1
1
0
1 TG2-Filter coefficients
(followed by 4 bytes of data)
Semiconductor Group
32
1997-07-01
PEB 2265
Programming the IOM®-2 – SICOFI®-2
How to Program the Filter Coefficients
TH-Filter:
Two sets of TH-filter coefficients can be loaded to the IOM-2 –
SICOFI-2.Each of the two sets can be selected for any of the two
IOM-2 – SICOFI-2 channels, by setting the value of TH-SEL in
configuration register CR2. Coefficient set 1 is loaded to the
IOM-2-SICOFI-2 via channel 1, set 2 is loaded via channel 2.
AX, AR, IM, FRX,
FRR-Filter:
An individual coefficient set is available for each of the two channels
Tone-Generators: An individual coefficient set is available for each of the two channels
An independent set of coefficients is available for all the two channels, for all the filters
and Tone-Generators.
Two sets of TH-filter coefficients can be loaded to the IOM-2 – SICOFI-2. Each of the
two sets can be selected for any of the two IOM-2 – SICOFI-2 channels, by setting the
value of TH-SEL in configuration register CR2. Coefficients set #1 is loaded to the
IOM-2-SICOFI-2 via channel 1, set #2 is loaded via channel 2 and so on.
Note: After RESET coefficient set #1 is used for all of the two channels, as all bits in
configuration register CR2 are set to ‘0'.
PEB 2265, IOM2-SICOFI® 2
channel 1
IM part1 Filter
IM part2 Filter
FRX-Filter
FRR-Filter
AX-Filter
AR-Filter
TG1, TG2
general registers
chan. 1 chan. 2
TH part1 TH part1
TH part2 TH part2
channel registers
channel 2
IM part1 Filter
IM part2 Filter
FRX-Filter
FRR-Filter
AX-Filter
AR-Filter
TG1, TG2
Figure 9
Semiconductor Group
33
1997-07-01
PEB 2265
Programming the IOM®-2 – SICOFI®-2
3.5
XOP Command
With the XOP command, the IOM-2 – SICOFI-2 C/I channel in the selected time slot1) is
configured and evaluated.
Bit
7
6
5
4
3
2
1
0
0
RW
0
1
1
LSEL2
LSEL1
LSEL0
RW
Read / Write Information: Enables reading from the IOM-2 – SICOFI-2
or writing information to the IOM-2 – SICOFI-2
RW = 0
Write to IOM-2 – SICOFI-2
RW = 1
Read from IOM-2 – SICOFI-2
LSEL
Length select information, for setting the number of subsequent
data bytes
LSEL = 000 0 bytes of data are following
LSEL = 001 1 byte of data is following (XR1)
LSEL = 010 2 bytes of data are following (XR2, XR1)
LSEL = 011 3 bytes of data are following (XR3, XR2, XR1)
LSEL = 100 4 bytes of data are following (XR4, XR3, XR2, XR1)
XR1 Extended Register2)
3.5.1
Bit
1)
7
6
5
4
3
2
1
0
SB2_1
SB2_0
SI2_01)
SI2_01)
SB1_1
SB1_0
SI1_01)
SI1_01)
Bits SI1_0 and SI2_0 have special meaning depending on contents of XR2 (see page 35).
SB2_1
SB2_0
SI2_0
SB1_1
SB1_0
SI1_0
1)
2)
status of pin SB2_1 is transferred to the upstream master device
status of pin SB2_0 is transferred to the upstream master device
status of pin SI2_0 is transferred to the upstream master device
status of pin SB1_1 is transferred to the upstream master device
status of pin SB1_0 is transferred to the upstream master device
status of pin SI1 _0 is transferred to the upstream master device
IOM-2 time slot TS0, TS2, TS4 or TS6, by pin-strapping the pins TSS0 and TSS1
Register XR1 can only be read.
Semiconductor Group
34
1997-07-01
PEB 2265
Programming the IOM®-2 – SICOFI®-2
3.5.2
XR2 Extended Register 2
Register XR2 configures the data-upstream command/indication channel.
Bit
7
6
5
4
3
N
2
1
0
T
Upstream Update Interval N
To restrict the rate of upstream C/I-bit changes, deglitching (persistence checking) of the
status information from the SLIC may be applied. New status information will be
transmitted upstream, after it has been stable for N milliseconds. N is programmable in
the range of 1 to 15 ms in steps of 1 ms, with N = 0 the deglitching is disabled.
Field N
Update Interval Time
0
0
0
0
Deglitching is disabled
0
0
0
1
Upstream transmission after 1 ms
0
0
1
0
Upstream transmission after 2 ms
.
.
.
.
.
.
.
.
.
.
1
1
1
0
Upstream transmission after 14 ms
1
1
1
1
Upstream transmission after 15 ms
Detector Select Sampling Interval T
SLICs with multiplexed loop- and ground-key-status, which have a single status output
pin for carrying the loop- and ground-keystatus information, need a special detector
select input.
Field T
Time Interval T between Detector selected High States
0
0
0
0
Detector select output LGKM0 is program. To 0 permanently
0
0
0
1
Time interval T is 1 ms
0
0
1
0
Time interval T is 2 ms
.
.
.
.
.
.
.
.
.
.
1
1
1
0
Time interval T is 14 ms
1
1
1
1
Detector select output LGKM0 is program. to 1 permanently
LGKM0 is detector select output for channel 1 and 2.
Semiconductor Group
35
1997-07-01
PEB 2265
Programming the IOM®-2 – SICOFI®-2
SLICs with Multiplexed Loop / Ground Key Detect
IOM2-SICOFI-2 (channel 1 and 2)
XR1
0
1
2
3
SI1_0
Loop/GND Key
input from SLIC
SB1_0
SB1_1
SLIC #1
SLIC detector
select control
T
Data
Upstream
LGKM0
programmable T
4
5
6
7
SI2_0
Loop/GND Key
input from SLIC
SB2_0
SB2_1
SLIC #2
Figure 10
IOM-2 – SICOFI-2 pin LGKM0 is a detector select output. This command output pin are
normally set to logical ‘0’, such that the SLIC outputs loop status, which is passed to
XR1-bits 0 and 4 via indication pins SI1_0 and SI2_0.
Every T milliseconds, the detector select output change to logical ‘1’ for a time of 125 µs
(period FSC). During this time the ground key status is read from the SLIC and
transferred upstream using XR1 - bits 1 and 5 via indication pins SIx_0 and SIy_0.
The time interval T is programmable from 1 ms to 14 ms in 1ms steps. It is possible to
program the output to be permanently logical ‘0’ or ‘1’.
Semiconductor Group
36
1997-07-01
PEB 2265
Programming the IOM®-2 – SICOFI®-2
3.5.3
XR3 Extended Register 3
This register controls the direction of the programmable C/I pins.
Bit
7
6
PSB2_1 PSB2_0
5
4
0
0
3
2
PSB1_1 PSB1_0
1
0
0
0
PSB2_1
Programmable bi-directional C/I pin SB2_1 is programmed
PSB2_1 = 0: pin SB2_1 is indication input
PSB2_1 = 1: pin SB2_1 is command output
PSB2_0
Programmable bi-directional C/I pin SB2_0 is programmed
PSB2_0 = 0: pin SB2_0 is indication input
PSB2_0 = 1: pin SB2_0 is command output
PSB1_1
Programmable bi-directional C/I pin SB1_1 is programmed
PSB1_1 = 0: pin SB1_1 is indication input
PSB1_1 = 1: pin SB1_1 is command output
PSB1_0
Programmable bi-directional C/I pin SB1_0 is programmed
PSB1_0 = 0: pin SB1_0 is indication input
PSB1_0 = 1: pin SB1_0 is command output
3.5.4
XR4 Extended Register 4
This register holds the offset value for the level metering function. It is only available via
the first used time slot.
Bit
3.6
7
6
5
4
3
2
1
0
OF7
OF6
OF5
OF4
OF3
OF2
OF1
OF0
SLIC Interface
The signaling connection between IOM-2 – SICOFI-2 and a SLIC is performed by the
IOM-2 – SICOFI-2 command/indication pins. Data received from the downstream C/I
byte are inverted and transferred to command output pins (SB, SO). Data on input pins
(SI, SB) are inverted and transferred to the upstream C/I-byte.
Semiconductor Group
37
1997-07-01
PEB 2265
Programming the IOM®-2 – SICOFI®-2
3.7
IOM®-2 Interface Command/Indication Byte
The IOM-2 – SICOFI-2 offers a 8 pin parallel command/indication SLIC interface per
channel.
Indication Input Pins
Command Output Pins
Program. Command/Indication Pins
SIx_0, SIx_1 SIx_2
SOx_0, SOx_1, SOx_2
SBx_0, SBx_1 (with x: 1 … 4)
Data present at SIx_0, SIx_1, SIx_2 and SBx_0, SBx_1 (if programmed as input) are
sampled, inverted and transferred upstream. Data received downstream from
IOM-2-interface are latched, inverted and fed to SOx_0, SOx_1, SOx_2 and SBx_0,
SBx_1 (if output).
Data-Downstream C/I Channel Byte Format (receive)
The IOM-2 channel contains 6 bits (for two voice channels) in both directions for analog
devices like the IOM-2 – SICOFI-2. As the IOM-2 – SICOFI-2 has up to five command
output pins per channel (depending on XR3) it is not possible to send commands to all
pins at a time. So C/I-channel bit 5 is used as an address bit to select the channel for the
command data on C/I-channel bits 4 … 0.
General Case:
Bit
5
4
3
2
1
0
AD
SBx_1
SBx_0
SOx_2
SOx_1
SOx_0
Example for IOM-2 – SICOFI-2 channels 1 and 2 (IOM-2 time slot 0):
Bit
1)
5
4
3
2
1
0
1
SB1_11)
SB1_01)
SO1_2
SO1_1
SO1_0
If SBx_y is programmed as command output.
Bit
5
4
3
2
1
0
0
SB2_11)
SB2_01)
SO2_2
SO2_1
SO2_0
Semiconductor Group
38
1997-07-01
PEB 2265
Programming the IOM®-2 – SICOFI®-2
Data Upstream C/I Channel Byte Format (transmit)
As the C/I-channel holds only 6 bits for two voice channels and the IOM-2 – SICOFI-2
has up to five indication pins per voice channel, only pins SI1_1 and SI1_2 for voice
channel 1, and pins SI2_1 and SI2_2 for voice channel 2 are fed directly to the
C/I-channel. Any change at one of the other indication pins (SIx_0, SBx_0 and SBx_1)
will generate an interrupt per channel, which is transmitted upstream immediately
(C/I-channel bits 2 and 5). Data on those pins is fed to register XR1 and can be evaluated
with a XOP-read command.
R
R
IOM -2 - SICOFI -2 (2 Channels, 1 Time-Slot)
C/I3
INT2
SI2_2
SI2_1
"0"
"0"
on
on
e
ang
Ch
hange
e
ang
Ch
SI1_1
C/I2
C/I1
C/I0
INT1
SI1_2
SI1_1
SI1_0
hange
C/I4
SI1_2
SB1_0
hange
C/I5
SB1_1
"0" on C
SI2_1
"0" on C
SI2_2
"0" on C
SI2_0
hange
SB2_0
"0" on C
SB2_1
XR1(7)
XR1(6)
XR1(5,4)
XR1(3)
XR1(2)
XR1(1,0)
SB2_1
SB2_0
SI2_0
SB1_1
SB1_0
SI1_0
Channel 2
Channel 1
If an interrupt occurs in one channel, changes in the neighboring channel will also generate an interrupt.
ITD09991
Figure 11
Semiconductor Group
39
1997-07-01
Semiconductor Group
40
2
2
Change 2
1
1
2
2
Data on Signaling Pins has to be stable for at least 2 samples, to be transferred DU or to trigger an interrupt.
During active interrupt data on pins transferred via Register is not sampled.
After clearing the interrupt, change 2 is detected, which generates a new interrupt.
Change 1 1
1
ITD09992
Data Transferred in Register
DD Read-Register Signal
Interrupt Transferred on C/I
Pin Transferred Via Register
Data on C/I-Channel
Pin Transferred Directly Via C/I
Sampling of Pins
(value between is ignored)
Deglitching Time
PEB 2265
Programming the IOM®-2 – SICOFI®-2
Figure 12
Data Flow
1997-07-01
PEB 2265
Programming the IOM®-2 – SICOFI®-2
3.8
Operating Modes
Figure 13
3.8.1
RESET (Basic setting mode)
Upon initial application of VDD or resetting pin RESET to ‘1’ during operation, or by
software-reset (see COP command), the IOM-2 – SICOFI-2 enters a basic setting
mode. Basic setting means, that the IOM-2 – SICOFI-2 configuration registers CR1q …
CR4 and XR1 … XR3 are initialized to ‘0’ for all channels.
All programmable filters are disabled, A-law is chosen, all programmable
command/indication pins are inputs. The two tone generators as well as any testmodes
are disabled. There is no persistence checking. Receive signaling registers are cleared.
DU-pin is in high impedance state, the analog outputs and the signaling outputs are
forced to ground.
Semiconductor Group
41
1997-07-01
PEB 2265
Programming the IOM®-2 – SICOFI®-2
Table 6
CR1 … CR4
00H
XR1 … XR4
00H
Coefficient RAM
Not defined
Command Stack
Cleared
DD-input
Ignored
DU-output
High impedance
VOUT1,2
GNDA1,2
SBx_y
Input
SOx_y
GNDD
If any voltage is applied to any input-pin before initial application of VDD, the
IOM-2 – SICOFI-2 may not enter the basic setting mode. In this case it is necessary to
reset the IOM-2 – SICOFI-2 or to initialize the IOM-2 – SICOFI-2 configuration registers
to ‘0’. The IOM-2 – SICOFI-2 leaves this mode automatically with the beginning of the
next 8-kHz frame (RESET-pin is released).
3.8.2
Standby Mode
After releasing the RESET-pin, (RESET-state), beginning with the next 8 kHz frame, the
IOM-2 – SICOFI-2 will enter the Standby mode. The IOM-2 – SICOFI-2 is forced to
standby mode with the PWRUP bit set to ‘0’ in the SOP command (POWERDOWN). The
two channels must be programmed separately. During standby mode the serial
IOM-2 – SICOFI-2 IOM-2 interface is ready to receive and transmit commands and data.
Received voice data on DD-pin will be ignored. IOM-2 – SICOFI-2 configuration
registers and coefficient RAM can be loaded and read back in this mode. Data
downstream C/I-channel data is fed to appropriate command pins. Data on indication
pins is transmitted data upstream.
Table 7
IOM-2 Voice Channels
‘11111111’ (idle)
VOUT1, 2
GNDA1, 2
3.8.3
Operating Mode
The operating mode for any of the two channels is entered upon recognition of a PWRUP
bit set to ‘1’ in a SOP command for the specific channel.
Semiconductor Group
42
1997-07-01
PEB 2265
Programming the IOM®-2 – SICOFI®-2
3.9
Programmable Filters
Based on an advanced digital filter concept, the PEB 2265 provides excellent
transmission performance and high flexibility. The new filter concept leads to a maximum
independence between the different filter blocks.
3.9.1
Impedance Matching Filter
• Realization by 3 different loops
– 4 MHz: Multiplication by a constant
(12 bit)
– 128 kHz: Wave Digital Filter (IIR)
(60 bit)
improves low frequency response)
– 64 kHz: FIR-Filter
(48 bit)
(for fine-tuning)
• Improved stability behavior of feedback loops
• Real part of termination impedance positive under all conditions
• Improved overflow performance for transients
• Return loss better 30 dB
3.9.2
Transhybrid Balancing (TH) Filter
• New concept:
2 loops at 16 kHz
• Flexible realization allows optimization of wide impedance range
• Consists of a fixed and a programmable part
– 2nd order Wave Digital Filter (IIR)
(106 bit)
(improves low frequency response)
– 7-TAP FIR-Filter
(84 bit)
(for fine-tuning)
• Trans-Hybrid-Loss better 30 dB (typically better 40 dB, device only)
• Adaptation to different lines by:
– Easy selection between two different downloaded coefficient sets
3.9.3
Filters for Frequency Response Correction
• For line equalization and compensation of attenuation distortion
• Improvement of Group-Delay-Distortion by using minimum phase filters
(instead of linear phase filters)
• FRR filter for correction of receive path distortion
– 5 TAP programmable FIR filter operating at 8 kHz
(60 bit)
• FRX filter for correction of transmit path distortion
– 5 TAP programmable FIR filter operating at 8 kHz
(60 bit)
• Frequency response better 0.1 dB
Semiconductor Group
43
1997-07-01
PEB 2265
Programming the IOM®-2 – SICOFI®-2
3.9.4
Amplification/Attenuation -Filters AX1, AX2, AR1, AR2
• Improved level adjustment for transmit and receive
• Two separate filters at each direction for
– Improved trans-hybrid balancing
– Optimal adjustment of digital dynamic range
– Gain adjustments independent of TH-filter
3.9.5
Amplification/Attenuation Receive (AR1, AR2)-Filter
Step size for AR-Filter
3.9.6
range 3 … − 14 dB: step size 0.02 … 0.05 dB
range − 14 … − 24 dB:step size 0.5 dB
Amplification/Attenuation Transmit (AX1, AX2)-Filter
Step size for AX-Filter
Semiconductor Group
range − 3 … 14 dB: step size 0.02 … 0.05 dB
range 14 … 24 dB: step size 0.5 dB
44
1997-07-01
PEB 2265
QSICOS Software
4
QSICOS Software
The QSICOS-software has been developed to help to obtain an optimized set of
coefficients both quickly and easily. The QSICOS program runs on any PC with at least
575 Kbytes of memory. This also requires MS-DOS Version 5.0 or higher, as well as
extended memory.
Calculation-Controlfile
RD/dB
Simulation
(PSPICE)
Country-Spec
f/Hz
Automatic K-Param Extraction
Line
Interface
K11=(Zin-Zg)/(Zin+Zg)
Line
Interface
K21=V2/Vg
QSICOS
Line
Interface
K12=2*V1/V3
K-Parameter
InterfaceFile
Software for
Filter-Coefficients-Optimization
Line
Interface
SICOFI
Coefficients
File
K22=V2/V3
Figure 14
4.1
QSICOS Supports
• Calculation of coefficients for the
– Impedance Filter (IM) for return loss calculation
– FRR and FRX-Filters for frequency response in receive and transmit path
– AR1, AR2 and AX1, AX2-Filter for level adjustment in receive and transmit path
– Trans-Hybrid Balancing Filter (TH) and
– two programmable tone generators (TG 1 and TG 2)
• Simulation of the PEB 2265 and SLIC system with fixed filter coefficients allows
simulations of tolerances which may be caused e.g. by discrete external components.
• Graphical output of transfer functions to the screen for
– Return Loss
– Frequency responses in receive and transmit path
– Transhybrid Loss
• Calculation of the PEB 2265 and SLIC system stability. The IM-Filter of the
PEB 2265 adjust the total system impedance by making a feedback loop. Because
the line is also a part of the total system, a very robust method has to used to avoid
oscillations and to ensure system stability. The input impedance of the PEB 2265 and
SLIC combination is calculated. If the real part of the system input impedance is
positive, the total system stability can be guaranteed.
Semiconductor Group
45
1997-07-01
PEB 2265
Transmission Characteristics
5
Transmission Characteristics
The proper adjustment of the programmable filters (transhybrid balancing, impedance
matching, frequency-response correction) needs a complete knowledge of the
IOM-2 – SICOFI-2’s analog environment, and it is suggested to use the
QSICOS-program for calculating the propriate coefficients. Unless otherwise stated, the
transmission characteristics are guaranteed within the test conditions.
Test Conditions
TA = 0 °C to 70 °C; VDD = 5 V ± 5 %; GNDA1 … 4 = GNDD = 0 V
RL1)) > 20 kΩ; CL < 20 pF; H(IM) = H(TH) = 0; H(R1) = H(FRX) = H(FRR) = 1;
HPR and HPX enabled;
AR2) = AR1 + AR2 =
AX3) = AX1 + AX2 =
0 to – 13 dB for sine-wave-, and
0 to – 11 dB for CCITT-noise-measurements
0 to 13 dB for sine-wave-, and
0 to 11 dB for CCITT-noise-measurements
f = 1014 Hz; 0 dBm0; A-Law or µ-Law;
AGX = 0 dB, 6.02 dB, AGR = 0 dB, − 6.02 dB;
In Transmit direction for µ-law an additional gain of 1.94 dB is implemented
automatically, in the companding block (CMP). This additional gain has to be considered
at all gain calculations, and reduces possible AX-gain.
A 0dBm044)) signal is equivalent to 1.095 [1.0906] Vrms. A +3.14 [3.17] dBm0 signal is
equivalent to 1.57 Vrms which corresponds to the overload point of 2.223 V
(A-law,[µ-law]).
When the gain in the receive path is set at 0 dB, an 1014 Hz PCM sinewave input with
a level 0dBm0 will correspond to a voltage of 1.095 Vrms at A-Law (1,0906 V µ-Law) at
the analog output.
When the gain in the transmit path is set at 0 dB, an 1014Hz sine wave signal with a
voltage of 1.095 Vrms A-Law (1.0906 V µ-Law) will correspond to a level of 0 dBm0 at
the PCM output.
1)
2)
3)
4)
RL,Cl forms the load on VOUT
Consider, in a complete System,
AR = AR1 + AR2 + FRR + R1 = 0 to − 13 dB (− 11 dB for CCITT-noise-measurement)
Consider, in a complete System,
AX = AX1 + AX2 + FRX = 0 to 13 dB (11 dB for CCITT-noise-measurement) for A-Law,
0 to 11 dB (9 dB for CCITT-noise-measurement) for µ-Law
The absolute power level in decibels referred to the PCM interface levels.
Semiconductor Group
46
1997-07-01
PEB 2265
Transmission Characteristics
Table 8
Parameter
Symbol
Limit Values
min
Gain absolute (AGX = AGR = 0)
TA = 25 °C; VDD = 5 V
TA = 0 − 70 °C; VDD = 5 V ± 5 %
typ.
Unit
max.
G
Gain absolute (AGX = 6.02 dB,
AGR = − 6.02 dB)
TA = 25 °C; VDD = 5 V
TA = 0 − 70 °C; VDD = 5 V ± 5 %
– 0.15 ±± 0.10 + 0.15
– 0.25
+ 0.25
dB
dB
– 0.15 ±± 0.10 + 0.15
– 0.25
+ 0.25
dB
dB
Harmonic distortion, 0 dBm0;
f = 1000 Hz; 2nd, 3rd order
HD
– 50
Intermodulation1)
IMD
IMD
– 46
– 56
CT
– 85
– 80
dB
– 85
5
– 67.4
17.5
– 78.0
12.0
dBm0p
dBmc
dBm0p
dBmc
R2
R3
Crosstalk 0 dBm0; f = 200 Hz to 3400 Hz
any combination of direction and channel
Idle channel noise,
Transmit, A-law, psophometric VIN = 0 V
Transmit, µ-law, C-message VIN = 0 V
Receive, A-law, psophometric idle code + 0
Receive, µ-law, C-message idle code + 0
1)
NTP
NTC
NRP
NRC
– 44
dB
dB
dB
Using equal-level, 4-tone method (EIA) at a composite level of − 13 dBm0 with frequencies in the range between
300 Hz and 3400 Hz.
Semiconductor Group
47
1997-07-01
PEB 2265
Transmission Characteristics
5.1
Frequency Response
5.1.1
Receive: reference frequency 1 kHz, input signal level 0 dBm0
ITD10002
2
Attenuation
dB
1
0.65 dB
0.125 dB
-0.125 dB
HPR is Off
0
-1
0 0.2
0.3
1
2
kHz 3 3.2 3.4
f
Figure 15
5.1.2
Transmit: reference frequency 1 kHz, input signal level 0 dBm0
ITD10001
2
Attenuation
dB
1
0.65 dB
0.125 dB
-0.125 dB
0
-1
0 0.2
0.1 0.3
1
2
kHz 3 3.2 3.4
f
Figure 16
Semiconductor Group
48
1997-07-01
PEB 2265
Transmission Characteristics
5.2
Group Delay
Maximum delays when the IOM-2 – SICOFI-2 is operating with H(TH) = H(IM) = 0 and
H(FRR) = H(FRX) = 1 including delay through A/D- and D/A converters. Specific filter
programming may cause additional group delays.
Group Delay deviations stay within the limits in the figures below.
5.2.1
Group Delay absolute values: Input signal level 0 dBm0
Table 9
Parameter
Symbol
Limit Values
min.
typ.
Unit
max.
Transmit delay
DXA
300
µs
Receive delay
DRA
250
µs
5.2.2
Reference
Group Delay Distortion transmit: Input signal level 0 dBm0
ITD09999
500
µs
∆tG 400
300
200
150
100
85
0.6
0
0
0.5
2.6 2.8
1.0
1.5
2.0
2.5
3.0 kHz 3.5
f
Figure 17
Semiconductor Group
49
1997-07-01
PEB 2265
Transmission Characteristics
5.2.3
Group Delay Distortion receive: Input signal level 0dBm01)
.
ITD09999
500
µs
∆tG 400
300
200
150
100
85
0.6
0
0
0.5
2.6 2.8
1.0
1.5
2.0
2.5
3.0 kHz 3.5
f
Figure 18
5.3
Out-of-Band Signals at Analog Input
With an 0 dBm0 out-of-band sine wave signal with frequency f (<<100 Hz or 3,4 kHz to
100 kHz) applied to the analog input, the level of any resulting frequency component at
the digital output will stay at least X dB below a 0 dBm0, 1 kHz sine wave reference
signal at the analog input.2)
1)
2)
HPR is switched on: reference point is at tGmin
HPR is switched off: reference point is at 1.5 kHz
Poles at 12 kHz ± 150 Hz and 16 kHz ± 150 Hz are be provided
Semiconductor Group
50
1997-07-01
PEB 2265
Transmission Characteristics
ITD09998
Transmit OUT of
Band Discrimination X
40
dB
35
32
30
25
20
15
10
0
0
0.06 0.1
3.4
4
4.6
6
10
18 kHz 100
f
Figure 19
4000 – F
3.4 … 4.0 kHz: X = – 14  sin π × -----------------------  – 1
 

1200 
4000 – F 7
4.0 … 4.6 kHz: X = – 18  sin π × -----------------------  – --- 
1200
9
5.4
Out-of-Band Signals at Analog Output
With a 0 dBm0 sine wave with frequency f (300 Hz to 3.99 kHz) applied to the digital
input, the level of any resulting out-of-band signal at the analog output will stay at least
X dB below a 0 dBm0, 1 kHz sine wave reference signal at the analog output.
ITD09997
Receive OUT of
Band Discrimination X
60
dB
50
57
40
35
30
28
20
15
10
0
0
0.06 0.1
3.4
4
4.6
6
8
10
10.55
16 18 kHz 100
f
Figure 20
4000 – F 
- – 1
3.4 … 4.6 kHz: X = – 14  sin π × ---------------------
1200 
Semiconductor Group
51
1997-07-01
PEB 2265
Transmission Characteristics
5.5
Out of Band Idle Channel Noise at Analog Output
R
SICOFI -4
With an idle code applied to the digital input, the level of any resulting out-of-band power
spectral density (measured with 3 kHz bandwidth) at the analog output, will be not
greater than the limit curve shown in the figure below.
ITD09996
-40
dBm0
-50
-55
-60
-70
-78
-80
-90
-100
101
10 2
10 3
10 4
kHz
f
Figure 21
5.6
Overload Compression
µ-law, transmit:
measured with sine wave f = 1014 Hz.
ITD09995
Fundamental
Output Power
10
dBm0
8
7
6
5
4
3
2
1
0.25
0
-0.25
-1
0
1
2
3
4
5
6
7
dBm0
9
Fundamental Input Power
Figure 22
Semiconductor Group
52
1997-07-01
PEB 2265
Transmission Characteristics
5.7
Gain Tracking (receive or transmit)
The gain deviations stay within the limits in the figures below
Gain Tracking:
(measured with sine wave f = 1014 Hz, reference level is 0 dBm0)
ITD09994
2
dB
∆ G 1.4
1
0.5
0.25
0
-0.25
-0.5
-1
-1.4
-2
-70
-60 -55 -50
-40
-37
-30
-20
-10
3
0 dBm0 10
Input Level
Figure 23
5.8
Total Distortion
The signal to distortion ratio exceeds the limits in the following figure.
5.8.1
Total Distortion Measured with Sine Wave
Receive or Transmit:
measured with sine wave f = 1014 Hz. (C-message
weighted for µ-law, psophometricaly weighted for A-law)
Figure 24
Semiconductor Group
53
1997-07-01
PEB 2265
Transmission Characteristics
5.8.2
Total Distortion Measured with Noise According to CCITT
Receive
Figure 25
Transmit
Figure 26
Semiconductor Group
54
1997-07-01
PEB 2265
Transmission Characteristics
5.9
Single Frequency Distortion
An input signal with its frequency swept between 0.3 to 3 kHz for the receive path, or 0
to 12 kHz for the transmit path, any generated output signal with other frequency than
the input frequency will stay 28 dB below the maximum input level of 0 dBm0.
Table 10
Receive
Transmit
Frequency
Max. Input Level
Frequency
Max. Input Level
300 Hz to 3.4 kHz
0 dBm0
0 to 12 kHz
0 dBm0
5.10
Transhybrid Loss
The quality of Transhybrid-Balancing is very sensitive to deviations in gain and group
delay - deviations inherent to the IOM-2 – SICOFI-2 A/D- and D/A-converters as well as
to all external components used on a line card (SLIC, OP’ s etc.)
Measurement of IOM-2 – SICOFI-2 transhybrid-loss: A 0 dBm0 sine wave signal and a
frequency in the range between 300 - 3400 Hz is applied to the digital input. The
resulting analog output signal at pin VOUT is directly connected to VIN, e.g. with the
IOM-2 – SICOFI-2 testmode “Digital Loop Back via Analog Port”. The programmable
filters FRR, AR, FRX, AX and IM are disabled, the balancing filter TH is enabled with
coefficients optimized for this configuration (VOUT = VIN).
The resulting echo measured at the digital output is at least X dB below the level of the
digital input signal as shown in the table below (Filter coefficients will be provided).
Table 11
Parameter
Symbol
Limit
Values
min.
typ.
Unit
Test Condition
TA = 25 °C; VDD = 5 V
TA = 25 °C; VDD = 5 V
TA = 25 °C; VDD = 5 V
TA = 25 °C; VDD = 5 V
TA = 25 °C; VDD = 5 V
Trans Hybrid Loss at 300 Hz
THL300
27
40
dB
Trans Hybrid Loss at 500 Hz
THL500
33
45
dB
Trans Hybrid Loss at 2500 Hz THL2500
29
40
dB
Trans Hybrid Loss at 3000 Hz THL3000
27
35
dB
Trans Hybrid Loss at 3400 Hz THL3400
27
35
dB
The listed values for THL correspond to a typical variation of the signal amplitude and
-delay in the analog blocks.
∆ amplitude
∆ delay
Semiconductor Group
= typ. ± 0.15 dB
= typ. ± 0.5 µs
55
1997-07-01
PEB 2265
Electrical Characteristics
6
Electrical Characteristics
6.1
Absolute Maximum Ratings
Table 12
Parameter
Symbol
min.
max.
Unit Test
Condition
VDD referred to GNDD
− 0.3
7.0
V
GNDA to GNDD
− 0.6
0.6
V
Analog input and output voltage
referred to VDD = 5 V;
referred to GNDA = 0 V
− 5.3
− 0.3
0.3
5.3
V
V
− 0.3
5.3
V
− 5.3
0.3
V
10
mA
− 60
125
°C
− 10
80
°C
1
W
All digital input voltages
referred to GNDD = 0 V;
(VDD = 5 V)
referred to VDD = 5 V;
(GNDD = 0 V)
Limit Values
DC input and output current at
any input or output pin (free from
latch -up)
Storage temperature
TSTG
Ambient temperature under bias TA
Power dissipation (package)
Semiconductor Group
PD
56
1997-07-01
PEB 2265
Electrical Characteristics
6.2
Operating Range
TA = 0 to 70 °C; VDD = 5 V ± 5 %; GNDD = 0 V; GNDA = 0 V
Table 13
Parameter
Symbol
Limit Values
min.
VDD supply current
standby
operating (2 channels)
IDD
Power supply rejection
PSRR
typ.
1.2
27
Unit
Test Condition
max.
2
40
mA
mA
of either supply/direction
30
dB
receive VDD guaranteed
receive VDD target value
14
30
dB
dB
Ripple: 0 to 150 kHz,
70 mVrms
Measured:
300 Hz to 3.4 kHz
Measured: at f:
3.4 to 150 kHz
Power dissipation standby PDS
15
20
mW
Power dissipation
operating
PDo1
75
110
mW
1 channel operating
Power dissipation
operating
PDo2
100
140
mW
2 channels operating
6.3
Digital Interface
TA = 0 to 70 °C; VDD = 5 V ± 5 %; GNDD = 0 V; GNDA = 0 V
All input-pins, with exception of the RESET-pin, have a TTL-input characteristic.
Table 14
Parameter
Symbol
Limit Values
min.
max.
0.8
Unit Test Condition
Low-input voltage
VIL
− 0.3
High-input voltage
VIH
2.0
Low-output voltage
VOL
0.45
V
IO = − 5 mA
Low-output voltage DU pin VOL
0.45
V
IO = − 7 mA,
RL = 1 kΩ
V
I0 = 5 mA
µA
− 0.3 ≤ VIN ≤ VDD
High-output voltage
VOH
Input leakage current
IIL
Semiconductor Group
V
V
4.4
±1
57
1997-07-01
PEB 2265
Electrical Characteristics
6.4
Analog Interface
TA = 0 to 70 °C; VDD = 5 V ± 5 %; GNDD = 0 V; GNDA = 0 V
Table 15
Parameter
Symbol
Analog input resistance
RI
Analog output resistance
RO
Analog output load
RL
CL
Input leakage current
IIL
Input voltage range (AC)
VIR
6.5
Limit Values
Unit Test Condition
min.
typ.
max.
160
270
480
kΩ
10
W
20
kΩ
pF
± 1.0
µA
20
± 0.1
0 ≤ VIN ≤ VDD
±±
V
2.223.
RESET Timing
To reset the IOM-2 – SICOFI-2 to basic setting mode, positive pulses applied to pin RS
have to be higher than 2.4 V (CMOS-Schmitt-Trigger Input) and longer than 3 µs.
Signals shorter than 1 µs will be ignored.
Semiconductor Group
58
1997-07-01
PEB 2265
Electrical Characteristics
6.6
IOM®-2 Interface Timing
6.6.1
4-MHz Operation Mode (Mode = 1)
t DCLh
t DCL
90%
DCL 10%
t FSC_S
t FSC
t FSC_H
FSC
t DD_S
t DD_H
DD
t dDU
t dDUhz
High
DU
Imp.
ITD03389
Figure 27
Switching Characteristics
Table 16
Parameter
Symbol
Limit Values
min.
Period DCL ‘fast’ mode 1)
typ.
max.
1/4096
tDCL
DCL duty cycle
40
Unit
kHz
60
%
125
µs
tDCLh
ns
Period FSC 1)
tFSC
FSC setup time
tFSC_S
70
FSC hold time
tFSC_H
40
ns
DD data in setup time
tDD_S
20
ns
DD data in hold time
tDD_H
50
ns
DU data out delay 2)
tdDU
1)
2)
150
320
ns
DCL = 4096 kHz: tFSC = 512 × tDCL
Depending on Pull-up resistor used in application (typical 1 kΩ), DU is a “open drain” - line
Semiconductor Group
59
1997-07-01
PEB 2265
Electrical Characteristics
6.6.2
2-MHz Operation Mode (Mode = 0)
t DCL
t DCLh
DCL
t FSC
t FSC_S
t FSC_H
FSC
t DD_S t DD_H
DD
t dDU
t dDUhz
High Imp.
DU
ITD09993
Figure 28
Switching Characteristics
Table 17
Parameter
Symbol
Limit Values
min.
Period DCL “slow” mode1)
max.
1/2048
tDCL
DCL duty cycle
1)
typ.
40
Unit
kHz
60
%
125
µs
tDCLh
ns
Period FSC
tFSC
FSC setup time
tFSC_S
70
FSC hold time
tFSC_H
40
ns
DD data in setup time
tDD_S
20
ns
DD data in hold time
tDD_H
50
ns
DU data out delay2)
tdDU
1)
2)
150
175
ns
DCL = 2048 kHz: tFSC = 256 × tDCL
Depending on pull up resistor used in application (typical 1 kΩ), DU is a “open drain” - line.
Semiconductor Group
60
1997-07-01
PEB 2265
Electrical Characteristics
6.7
IOM®-2 Command/Indication Interface Timing
6.7.1
4-MHz Operation Mode (Mode = 1)
Figure 29
Semiconductor Group
61
1997-07-01
PEB 2265
Electrical Characteristics
6.7.2
2-MHz Operation Mode (Mode = 0)
Figure 30
Switching Characteristics
Table 18
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Command out delay
tdCout
150
250
ns
Command out high impedance
tdCZ
150
250
ns
Command out active
tdCA
150
250
ns
Indication in setup time
tlin_s
50
ns
Indication in hold time
tlin_h
100
ns
Semiconductor Group
62
1997-07-01
PEB 2265
Electrical Characteristics
6.8
Detector Select Timing
Figure 31
6.8.1
Switching Characteristics
Table 19
Parameter
Symbol
Limit Values
min.
typ.
Unit
max.
Detector select high time
tLGKMh
125
µs
Detector select repeat
tLGKM
1 … 14
ms
Indication in setup time
tlin_s
50
ns
Indication in hold time
tlin_h
100
ns
Semiconductor Group
63
1997-07-01
PEB 2265
Appendix
7
Appendix
7.1
IOM®-2 Interface Monitor Transfer Protocol
7.1.1
Monitor Channel Operation
The Monitor Channel is used for the transfer of maintenance information between two
functional blocks. Using two monitor control bits (MR and MX) per direction, the data are
transferred in a complete handshake procedure. The MR and MX bits in the fourth octet
(C/I channel) of the IOM-2 frame are used for the handshake procedure of the monitor
channel.
The monitor channel transmission operates on a pseudo-asynchronous basis:
– Data transfer (bits) on the bus is synchronized to Frame Sync FSC
– Data flow (bytes) are asynchronously controlled by the handshake procedure.
For example: Data is placed onto the DD-monitor-channel by the monitor-transmitter of
the master device (DD-MX-Bit is activated i.e. set to ‘0’). This data transfer will be
repeated within each frame (125 µs rate) until it is acknowledged by the
IOM-2 – SICOFI-2 monitor-receiver by setting the DU-MR-bit to ‘0’, which is checked by
the monitor-transmitter of the master device. Thus, the data rate is not 8 kbyte/s.
Figure 32
Semiconductor Group
64
1997-07-01
PEB 2265
Appendix
7.1.2
Monitor Handshake Procedure
The monitor channel works in 3 states
– idle state:
A pair of inactive (set to ‘1’) MR- and MX-bits during two or more
consecutive frames: End of Message (EOM)
– sending state: MX-bit is activated (set to ‘0’) by the monitor-transmitter, together
with data-bytes (can be changed) on the monitor-channel
– acknowledging: MR-bit is set to active (set to ‘0’) by the monitor-receiver, together
with a data-byte remaining in the monitor-channel.
A start of transmission is initiated by a monitor-transmitter in sending out an active
MX-bit together with the first byte of data (the address of the receiver) to be transmitted
in the monitor-channel.
This state remains until the addressed monitor-receiver acknowledges the received data
by sending out an active MR-bit, which means that the data-transmission is repeated
each 125 µs frame (minimum is one repetition). During this time the monitor-transmitter
evaluates the MR-bit.
Flow control, means in the form of transmission delay, can only take place when the
transmitters MX and the receivers MR bit are in active state.
Since the receiver is able to receive the monitor data at least twice (in two consecutive
frames), it is able to check for data errors. If two different bytes are received the receiver
will wait for the receipt of two identical successive bytes (last look function).
A collision resolution mechanism (check if another device is trying to send data during
the same time) is implemented in the transmitter. This is done by looking for the inactive
(‘1’) phase of the MX-bit and making a per bit collision check on the transmitted monitor
data (check if transmitted ‘1’s are on DU/DD-line; DU/DD-line are open-drain lines).
Any abort leads to a reset of the IOM-2 – SICOFI-2 command stack, the device is ready
to receive new commands.
To obtain a maximum speed data transfer, the transmitter anticipates the falling edge of
the receivers acknowledgment.
Due to the inherent programming structure, duplex operation is not possible. It is not
allowed to send any data to the IOM-2 – SICOFI-2, while transmission is active.
Semiconductor Group
65
1997-07-01
PEB 2265
Appendix
7.1.3
State Diagram of the IOM®-2 – SICOFI®-2 Monitor Transmitter
MR + MXR
MXR
MR. MXR
Idle
MX = 1
MR. RQT
Abort
MX = 1
MR. MXR
Initial
State
MR
MR. RQT
1st Byte
MX = 0
Wait
MX = 1
EOM
MX = 1
MR
MR. RQT
MR
nth Byte ACK
MX = 1
MR
MR. RQT
Wait for ACK
MX = 0
MR. RQT
CLS/ABT
Any State
ITD02458
Figure 33
MR …
MX …
MXR …
CLS …
RQT …
ABT …
MR - bit received on DD - line
MX - bit calculated and expected on DU - line
MX - bit sampled on DU - line
Collision within the monitor data byte on DU - line
Request for transmission form internal source
Abort request/indication
.…
logical AND
logical OR
+…
Semiconductor Group
66
1997-07-01
PEB 2265
Appendix
7.1.4
State Diagram of the IOM®-2 – SICOFI®-2 Monitor Receiver
Idle
MR = 1
MX . LL
1st Byte REC
MR = 0
MX
Initial
State
MX
Abort
MR = 1
MX
ABT
MX
MX
MX
MX . LL
Byte Valid
MR = 0
MX . LL
MX
New Byte
MR = 1
MX
Any
State
Wait for LL
MR = 0
MX . LL
MX
nth Byte REC
MR = 1
MX . LL
MX . LL
Wait for LL
MR = 0
ITD02459
Figure 34
MR …
MX …
LL …
ABT …
.…
+…
MR - bit calculated and transmitted on DU - line
MX - bit received data downstream (DD - line)
Last lock of monitor byte received on DD - line
Abort indication to internal source
logical AND
logical OR
Semiconductor Group
67
1997-07-01
PEB 2265
Appendix
7.2
Monitor Channel Data Structure
The monitor channel is used for the transfer of maintenance information between two
functional blocks. By use of two monitor control bits (MR and MX) per direction, the data
are transferred in a complete handshake procedure.
7.2.1
Address Byte
Messages to and from the IOM-2 – SICOFI-2 are started with the following Monitor byte:
Bit
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
1
Thus providing information for two voice channels, the IOM-2 – SICOFI-2 is one device
on one IOM-2 time slot. Monitor data for a specific voice channel is selected by the
IOM-2 – SICOFI-2 specific command (SOP or COP).
7.2.2
Identification Command
In order to be able to unambiguously identify different devices by software, a two byte
identification command is defined for analog lines IOM-2 devices.
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Each device will then respond with its specific identification code. For the
IOM-2 – SICOFI-2 this two byte identification code is:
1
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
Each byte is transferred at least twice (in two consecutive frames).
Semiconductor Group
68
1997-07-01
PEB 2265
Appendix
7.3
IOM®-2 Interface Programming Procedure
Example for a typical IOM-2 interface programming procedure, consisting of
identification request and answer, a SOP Write command with three byte following, and
SOP Read to verify the programming.
Table 20
Frame
Data Down
Data Up
Monitor
MR/MX
Monitor
MR/MX
1
11111111
11
11111111
11
2
IDRQT. 1st byte
10
11111111
11
3
IDRQT. 1st byte
10
11111111
01
4
IDRQT. 2nd byte
11
11111111
01
5
IDRQT. 2nd byte
10
11111111
11
6
11111111
11
11111111
01
7
11111111
11
IDANS. 1st byte
10
8
11111111
01
IDANS. 1st byte
10
9
11111111
01
IDANS. 2nd byte
11
10
11111111
11
IDANS. 2nd byte
10
11
11111111
01
11111111
11
12
Address
10
11111111
11
13
Address
10
11111111
01
14
SOP Write
11
11111111
01
15
SOP Write
10
11111111
11
16
CR3
11
11111111
01
17
CR3
10
11111111
11
18
CR2
11
11111111
01
19
CR2
10
11111111
11
20
CR1
11
11111111
01
21
CR1
10
11111111
11
22
SOP Read
11
11111111
01
23
SOP Read
10
11111111
11
24
11111111
11
11111111
01
25
11111111
11
Address
10
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Appendix
Table 20
(cont’d)
Frame
Data Down
Data Up
Monitor
MR/MX
Monitor
MR/MX
26
11111111
01
Address
10
27
11111111
01
CR3
11
28
11111111
11
CR3
10
29
11111111
01
CR2
11
30
11111111
11
CR2
10
31
11111111
01
CR1
11
32
11111111
11
CR1
10
33
11111111
01
11111111
11
IDRQT … identification request (80H, 00H)
IDANS … answer to identification request (80H, 82H)
Address … IOM-2 – SICOFI-2 specific address byte (81H)
CRx …
Data for/from configuration register x.
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Test Features
8
Test Features
8.1
Boundary Scan
8.1.1
General
The IOM-2 – SICOFI-2 provides fully IEEE Std. 1149.1 compatible boundary scan
support consisting of:
–
–
–
–
a complete boundary scan (digital pins)
a test access port controller (TAP)
four dedicated pins (TCK, TMS, TDI, TDO)
a 32 bit ICODE register
All IOM-2 – SICOFI-2 digital pins expect power supply VDD D and ground GNDD are
included in the boundary scan. Depending on the pin functionality one, two or three
boundary cells are provided.
Table 21
Pin Type
Number of Boundary
Scan Cells
Usage
Input
1
Input
Output
2
Output, enable
I/O
3
Input, output, enable
When the TAP controller is in the appropriate mode, data is shifted into/out of the
boundary scan via the pins TDI/TDO controlled by the clock applied to pin TCK.
The IOM-2 – SICOFI-2 pins are included in the following sequence in the boundary
scan:
Table 22
Pin Number
Pin Name
Type
57
MODE
I
59
TSS1
I
60
TSS0
I
61
N.U.I.
I
62
N.U.I.
I
63
N.U.I.
I
64
N.U.IO.
I/O
1
N.U.IO.
I/O
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Test Features
Table 22
(cont’d)
Pin Number
Pin Name
Type
2
N.C.
O
3
N.C.
O
4
N.C.
O
13
N.C.
O
14
N.C.
O
15
N.C.
O
16
N.U.IO.
I/O
17
N.U.IO.
I/O
18
N.U.I.
I
19
N.U.I.
I
20
N.U.I.
I
21
N.C.
O
22
RESET
I
24
DD
I
25
DU
O (open drain)
26
DCL
I
27
FSC
I
28
LGKM0
O
29
SI1_2
I
30
SI1_1
I
31
SI1_0
I
32
SB1_1
I/O
33
SB1_0
I/O
34
SO1_2
O
35
SO1_1
O
36
SO1_0
O
45
SO2_0
O
46
SO2_1
O
47
SO2_2
O
48
SB2_0
I/O
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Test Features
Table 22
(cont’d)
Pin Number
Pin Name
Type
49
SB2_1
I/O
50
SI2_0
I
51
SI2_1
I
52
SI2_0
I
8.1.2
The TAP-Controller
The Test Access Port (TAP) controller implements the state machine defined in the
JTAG standard IEEE Std. 1149.1. Transitions on pin TMS (Test Mode Select) cause the
TAP controller to perform a state change. According to the standard definition five
instructions are executable:
Figure 35
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Test Features
Table 23
Code
Instruction
Function
0000
EXTEST
External testing
0001
INTEST
Internal testing
0010
SAMPLE/PRELOAD
Snap-shot testing
0011
ICODE
Reading ID code
0100
Tap_Test 1
Configuration for Level Metering
0101
Tap_Test 2
Wait for result
1000
Tap_Test 5
Serial testdata output (Level Metering Results)
0111
Tap_Test 4
Switch off Test
11xx
BYPASS
Bypass operation
EXTEST
Is used to examine the board interconnections.
INTEST
Supports internal chip testing (is the default value of the instruction
register)
SAMPLE/PRELOAD Provides a snap-shot of the pin level during normal operation, or is
used to preload the boundary scan with a test vector
ICODE
The 32 bit identification register is serially read out via TDO. It
contains a version number (4 bit), a device code (16 bit) and the
manufacture code (11 bit). The LSB is fixed to ‘1’.
For the IOM-2 – SICOFI-2 V1.1 the Code is: ‘0011 0000 0000 0001
0101 0000 1000 001 1’
TAP_TEST1
39 bit field for selecting operation
(Level Metering Offset, Loops, Tone Generator …)
TAP_TEST2
Wait for Level Metering result ready (should be > t.b.d. mS)
TAP_TEST5
Level Metering Data output (1 bit result of Level Metering per
channel)
TAP_TEST4
Level Metering Operation is switched off
BYPASS
a bit entering TDI is shifted to TDO after one TCK clock cycle
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Test Features
8.2
Level Metering Function
The Level Metering Function is a functional selftest (available per channel), which allows
selftest of the chip (digital, or digital and analogue), and also selftest of the board
(including the SLIC).
An external or internally generated sine-wave signal is fed to the receive path. After
switching a loop (internal or external via the SLIC) to the transmit-path the return level is
measured and compared to a programmable offset value. The result of this operation
(greater or smaller than offset) can be read out via the IOM-2 interface (bit LMR in
configuration register CR2).
There is a single-8-bit Offset-Register available for both two channels. This offset
register can be accessed as XR4 with a XOP-Command (Field LSEL = 100)
This register contains the 2’s complement offset value for the level metering function
Bit
7
6
5
4
3
2
1
0
OF7
OF6
OF5
OF4
OF3
OF2
OF1
OF0
Block Diagram
Offset
Config.Register
ABS
AGX
ADC
DSI
DS2
A-B
LMR
LM
Transmit Path
VIN
Sign
x
AX2*
FRX*
HPX
AX1*
CMP
PCMOUT
EXP
PCMIN
*programmable
IM1*
IM2*
TH*
TG1,2
VOUT
AGR
DAC
+
US2
R1*
US1
FRR*
AR2*
AR1*
HPR*
Receive Path
iom36.wmf
Figure 36
(For further information, an Application Note describing the calculation of the offset value
and the sensitivity, is available).
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Test Features
8.3
Programming the IOM®-2 – SICOFI®-2 Tone Generators
Two independent Tone Generators are available per channel. When one or both
tone-generators are switched on, the voice signal is switched off automatically for the
selected voice channel. To make the generated signal sufficient for DTMF, a
programmable bandpass-filter is included. The default frequency for both tone
generators is 1000 Hz.
The QSICOS-program contains a program for generating coefficients for variable
frequencies.
Byte sequences for programming both the tone generators and the bandpass-filters:
Table 24
Frequency
Command
Byte 1
Byte 2
Byte 3
Byte 4
697 Hz
0C/0D1)
0A
33
5A
2C
770 Hz
0C/0D1)
12
33
5A
C3
852 Hz
0C/0D1)
13
3C
5B
32
941 Hz
0C/0D1)
1D
1B
5C
CC
1209 Hz
0C/0D1)
32
32
52
B3
1336 Hz
0C/0D1)
EC
1D
52
22
1477 Hz
0C/0D1)
AA
AC
51
D2
800 Hz
0C/0D1)
12
D6
5A
C0
950 Hz
1)
1C
F0
5C
C0
1008 Hz
1)
0C/0D
1A
AE
57
70
2000 Hz
0C/0D1)
00
80
50
09
1)
0C/0D
0C is used for programming Tone Generator 1, in channel 1.
0D is used for programming Tone Generator 2, in channel 1.
The resulting signal amplitude can be set by transmitting the AR1 and AR2 filters. By
switching a “digital loop” the generated sine-wave signal can be fed to the transmit path.
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Package Outlines
9
Package Outlines
GPM05250
P-MQFP-64-1-2 (SMD)
(Plastic Metric Quad Flat Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”
SMD = Surface Mounted Device
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Dimensions in mm
1997-07-01