PI6C2952 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Low Voltage PLL Clock Driver Features Description ±100ps Cycle-to-Cycle Jitter The PI6C2952 is a 3.3V compatible, PLL-based clock driver device targeted for high-performance clock applications. The device features a fully integrated PLL with no external components required. With output frequencies up to 180MHz and eleven lowskew outputs, the PI6C2952 is well suited for high-performance designs. The device employs a fully differential PLL design to optimize jitter and noise rejection performance. Fully Integrated PLL Output Frequency up to 180MHz High-Impedance Disabled Outputs Compatible with PowerPC, Intel, and High-Performance RISC Microprocessors The PI6C2952 features three banks of individually configurable outputs. The banks contain 5 outputs, 4 outputs, and 2 outputs. The internal divide circuitry allows for output frequency ratios of 1:1, 2:1, 3:1, and 3:2:1. The output frequency relationship is controlled by the fsel frequency control pins. The fsel pins and other inputs are LVCMOS/LVTTL compatible inputs. Configurable Output Frequency 32-Pin LQFP Package (FB) Qb2 24 23 22 21 20 19 18 17 16 25 15 26 Qb3 27 GNDO 28 GNDO 29 Qc0 Qc1 Qa2 Qa1 13 GNDO 12 Qa0 30 11 VCCI 31 10 VCCA 32-Pin FB 9 PLL_En The PI6C2952s outputs are LVCMOS which are optimally designed to drive terminated transmission lines. For applications using seriesterminated transmission lines, each PI6C2952 output can drive two lines. This capability provides an effective fanout of 22, more than enough clocks for most clock tree designs. FBin GNDI 6 7 8 REFCLK 5 MR/OE fsela 2 3 4 fselb 32 1 fselc VCCO VCCO 14 VCO_Sel VCCO The PI6C2952 uses external feedback to the PLL. This features allows the device to be used as a zero delay buffer. Any of the eleven outputs can be used as feedback to the PLL. To optimize PLL stability and jitter performance,the VCO_Sel pin allows for the choice of two VCO ranges. For board level test, the MR/OE pin allows a user to force the outputs into high impedance. For system debug, the PI6C2952s PLL can be bypassed. When forced to a logic HIGH, the PL_LEN input routes the signal on the RefClk input around the PLL directly to the internal dividers. Because the signal is routed through the dividers, it may take several transitions of the RefClk to affect a transition on the outputs. This features allows a designer to single step the design for debug purposes. GNDO Qa3 Qa4 VCCO VCCO Qb0 Qb1 GNDO Pin Configuration 1 PS8542 06/20/01 PI6C2952 Low Voltage PLL Clock Driver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Block Diagram (Int Pull Down) PLL_En REFCLK ÷4/÷6 ÷2 VCO V Phase Detector 200-480MHz FBIn Qa0 Qa1 Qa2 LPF Qa3 VCO_Sel (Int Pull Down) fsela (Int Pull Down) Qa4 V ÷4/÷2 Qb0 Qb1 Qb2 fselb (Int Pull Down) Qb3 Qc0 V ÷2/÷4 fselc (Int Pull Down) MR/OE (Int Pull Down) Qc1 "–1" Has ÷2/÷8 "–2" Has ÷4/÷8 Function Tables fs e la Qan fs e lb Qbn fs e lc Qcn Pin Name 0 1 ÷4 ÷6 0 1 ÷4 ÷2 0 1 ÷2 ÷4 VCCA PLL Power Supply VCCO O utput Buffer Power Supply VCCI Internal Core Logic Power Supply GNDI Internal Ground GNDO O utput Buffer Ground Control Pin Logic 'O' Logic '1' VCO _Sel fVCO fVCO /2 MR/O E O utput Enable High Z PLL_En Enable PLL Disable PLL 2 D e s cription PS8542 06/20/01 PI6C2952 Low Voltage PLL Clock Driver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Absolute Maximum Ratings* Symbol Parame te rs M in. M ax. VCC Supply Voltage 0.3 4.6 VI Input Voltage 0.3 VDD + 0.3 IIN Input Current Storage Temperature Range TSTOR 40 Units V ±20 mA 125 °C *Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. DC Characteristics (TA = 0°C to 70° C, VCC = 3.3V± 5%) Symbol Conditions Characte ris tic VIH Input HIGH Voltage VIL Input LOW Voltage VOH IOH = 20mA (Note1.) Output HIGH Voltage VOL IOL = 20mA (Note1.) Output LOW Voltage IIN Note 2. Input Current M in. Typ 2.0 0.8 0.5 ±120 2.7 CPD Power Dissipation Capacitance 25 Maximum Quiescent Supply Current ICCA V 2.4 Input Capacitance Total ICC Static Current Units 3.6 CIN ICC M ax. 4.0 pF 160 PLL Supply Current 15 µΑ mA 20 Notes: 1. The PI6C2952 outputs can drive series- or parallel-terminated 50 ohms (or 50 ohms to VCC/2) transmission lines on the incident edge (see Applications Info section). 2. Inputs have pullup, pulldown resistors that affect input current. PLL Input Reference Characteristics (TA = 0°C to 70°C) Symbol Parame te rs M in. M ax. Units 3.0 ns tr, tf TCLK Input Rise/Falls fref Reference Input Frequency Note 3 Note 3 MHz frefDC Reference Input Duty Cycle 25 75 % Condition 3. Maximum and minimum input reference is limited by the VCO lock range and the feedback divider. 3 PS8542 06/20/01 PI6C2952 Low Voltage PLL Clock Driver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 AC Characteristics (TA = 0°C to 70°C, VCC = 3.3V± 5%) Symbol Characte ris tics Conditions M in. tr, tf Output Rise/Fall Time (Note 4.) IPW Output Pulse Width (Note 4.) tOS Output- to- Output Skew Excluding Qa0 (Note 4.) All Outputs All Outputs Same Frequencies Same Frequencies Different Frequencies fVCO PLL VCO Lock Range Feedback = VCO/4 Feedback = VCO/6 Feedback = VCO/8 Feedback = VCO/12 VCO_Sel = VCO_Sel = VCO_Sel = VCO_Sel = fmax Maximum Output Frequency Qc,Qb (÷2) Qa,Qb,Qc (÷4) Qa (÷6) (Note 4.) tpd REFCLK to FBIN Delay Notes 4 and 5. 0.8 to 2.0V Typ. 0.10 tCYCLE/2 750 0 0 1 1 tCYCLE/2 ±500 M ax. Units 1.0 ns tCYCLE/2 +750 200 200 200 200 480 480 480 480 200 0 200 50ohms to VCC/2 2 8 tPZL, tPZH Output Enable Time 50ohms to VCC/2 2 10 CycletoCycle Jitter (PeaktoPeak) tlock Maximum PLL Lock Time tJP MHz 180 120 80 tPLZ, tPHZ Output Disable Time tjitter ps 350 450 550 ps ns ±100 Note 5. Long term Period Jitter ps 10 ms TBD ps 4. 50 ohms to VCC/2. 5. tpd is specified for 50 MHz input ref, the window will shrink/grow proportionally from the minimum limit with shorter/longer input reference periods. The tpd does not include jitter. Applications Information Driving Transmission Lines PI6C2952 Output Buffer The PI6C2952 clock driver was designed to drive high-speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user, the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 10 ohms, the drivers can drive either parallel- or series-terminated transmission lines. RS= 43 ohms ZO= 50 ohms IN OutA 7 ohms PI6C2952 Output Buffer RS= 43 ohms ZO= 50 ohms OutB0 IN 7 ohms RS= 43 ohms ZO= 50 ohms OutB1 Figure 3. Single versus Dual Transmission Lines 4 PS8542 06/20/01 PI6C2952 Low Voltage PLL Clock Driver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 In most high performance clock networks pointtopoint distribution of signals is the method of choice. In a pointtopoint scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50ohm resistance to V CC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the PI6C2952 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 3 illustrates an output driving a single series terminated line vs two series terminated lines in parallel. When taken to its extreme the fanout of the PI6C2952 clock driver is effectively doubled due to its capability to drive multiple lines. Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 5 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. PI6C2952 Output Buffer 7ohms RS = 36 ohms The waveform plots of Figure 4 show the simulation results of an output driving a single line vs two lines. In both cases the drive capability of the PI6C2952 output buffers is more than sufficient to drive 50-ohm transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight outputtooutput skew of the PI6C2952. The output waveform in Figure 4 shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 43ohm series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: Figure 5. Optimized Dual Line Termination SPICE level output buffer models are available for engineers who want to simulate their specific interconnect schemes. In addition IV characteristics are in the process of being generated to support the other board level simulators in general use. Power Supply Filtering The PI6C2952 is a mixed analog/digital product and as such it exhibits some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. The PI6C2952 provides separate power supplies for the output buffers (VCCO) and the internal PLL (VCCA) of the device. The purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phaselocked loop. In a controlled environment such as an evaluation board this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simplest form of isolation is a power supply filter on the VCCA pin for the PI6C2952. At the load end the voltage will double, due to the near unity reflection coefficient, to 2.8V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns). trip delay (In this example: 4.0ns) 3.0 VOLTAGE (V) OutA tD = 3.8956 ZO = 50 ohms 7 ohms + 36 ohms 36 ohms = 50 ohms 50 ohms 25 ohms = 25 ohms VL = VS (Zo / Rs + Ro +Zo) = 3.0 (25/53.5) = 1.40V 2.5 ZO = 50 ohms RS = 36 ohms OutB tD = 3.9386 2.0 3.3V In 1.5 RS = 5-15 ohms 1.0 VCCA 0.5 PI6C2952 0 0.01µF 22µF VCC 2 4 6 8 TIME (ns) 10 12 14 0.01µF Figure 4. Single versus Dual Waveforms Figure 6. Power Supply Filter 5 PS8542 06/20/01 PI6C2952 Low Voltage PLL Clock Driver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 32-Pin LQFP (FB) Package 9.00 BSC .354 Square 7.00 Square .276 BSC 0.09 0.20 .004 .008 GAUGE PLANE 0.25 mm 0° 1.60 Max. .063 1.00 .004 7° 0.45 .018 0.75 .030 REF .039 0.10 Seating Plane 1.35 0.30 0.45 .012 .018 0.80 .032 BSC 1.45 0.05 .053 0.15 .057 .002 .006 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS Ordering Information Part Numbe r Package Ope rating Te mpe rature 32- LQ FP Commercial PI6C2952FB PI6C2952- 1FB PI6C2952- 2FB Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 6 PS8542 06/20/01