POTATO PO49FCT3806Q

PO49FCT3806
3.3V Dual 1:5 CMOS Invert Clock Buffered Driver
11/22/05
750MHz TTL/CMOS Potato Chip
FEATURES:
DESCRIPTION:
. Operating frequency up to 750MHz with 2pf load
. Operating frequency up to 550MHz with 5pf load
. Operating frequency up to 300MHz with 15pf load
. Operating frequency up to 150MHz with 50pf load
. Very low output pin to pin skew < 250ps
. Very low pulse skew < 100ps
. VCC = 1.65V to 3.6V
. Propagation delay < 2.6ns max with 15pf load
. Low input capacitance: 3pf typical
. Dual 1:5 invert fanout
. Available in 20pin 300mil wide SOIC package
. Available in 20pin 150mil wide QSOP package
Potato Semiconductor’s PO49FCT3806G is
designed for world top performance using
submicron CMOS technology to achieve
750MHz TTL output frequency with less than
100ps output pulse skew.
Pin Configuration
PO49FCT3806G is a 3.3V CMOS Dual 1 input to
5 outputs Invert Buffered driver to achieve
750MHz output frequency. Typical applications
are crystal oscillator, ring oscillator, clock and
signal distribution.
Logic Block Diagram
Pin Description
Pin Name
Description
INA, INB
Signal or clock Inputs
Inputs
Outputs
INA, INB
OAn, OBn
MON
Hi-Z State Output Enable Inputs (Active LOW)
L
L
H
H
Signal or clock Outputs
L
H
L
L
MON
Monitor Output
H
L
Z
H
Vcc, GND
Power, Ground
H
H
Z
L
OAn, OBn
1
Copyright © 2005, Potato Semiconductor Corporation
PO49FCT3806
3.3V Dual 1:5 CMOS Invert Clock Buffered Driver
11/22/05
750MHz TTL/CMOS Potato Chip
Maximum Ratings
Description
Max
Unit
Storage Temperature
-65 to 150
°C
Operation Temperature
-40 to 85
°C
Operation Voltage
-0.5 to +4.6
V
Input Voltage
-0.5 to Vcc+0.5
V
Output Voltage
-0.5 to Vcc+0.5
V
Note:
stresses greater than listed under
Maximum
Ratings
may
cause
permanent damage to the device. This
is a stress rating only and functional
operation of the device at these or any
other conditions above those indicated
in the operational sections of this
specification is not implied. Exposure
to absolute maximum rating conditions
for extended periods may affect
reliability specification is not implied.
DC Electrical Characteristics
Symbol
Description
VOH
Output High voltage
VOL
Test Conditions
Min
Typ
Max
Unit
Vcc=3V Vin=VIH or VIL, IOH= -12mA
2.4
3
-
V
Output Low voltage
Vcc=3V Vin=VIH or VIL, IOH=12mA
-
0.3
0.5
V
VIH
Input High voltage
Guaranteed Logic HIGH Level (Input Pin)
2
-
Vcc
V
VIL
Input Low voltage
Guaranteed Logic LOW Level (Input Pin)
-0.5
-
0.8
V
IOZH
High Impedance
Output current
Vcc = 3.6V and Vo = Vcc
-
-
1
uA
IOZL
High Impedance
Output current
Vcc = 3.6V and Vo = 0V
-
-
-1
uA
IIH
Input High current
Vcc = 3.6V and Vin = 3.6V
-
-
1
uA
IIL
Input Low current
Vcc = 3.6V and Vin = 0V
-
-
-1
uA
VIK
Clamp diode voltage
Vcc = Min. And IIN = -18mA
-
-0.7
-1.2
V
Notes:
1.
2.
3.
4.
5.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25 °C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
VoH = Vcc – 0.6V at rated current
2
Copyright © 2005, Potato Semiconductor Corporation
PO49FCT3806
3.3V Dual 1:5 CMOS Invert Clock Buffered Driver
11/22/05
750MHz TTL/CMOS Potato Chip
Power Supply Characteristics
Symbol
IccQ
Description
Quiescent Power Supply Current
Test Conditions (1)
Min
Typ
Max
Unit
Vcc=Max, Vin=Vcc or GND
-
0.1
30
uA
Notes:
1.
2.
3.
4.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25°C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
Capacitance
Parameters (1)
Description
Test Conditions
Typ
Max
Unit
Cin
Input Capacitance
Vin = 0V
3
4
pF
Cout
Output Capacitance
Vout = 0V
-
6
pF
Notes:
1 This parameter is determined by device characterization but not production tested.
Switching Characteristics
Symbol
Description
Test Conditions (1)
Max
Unit
tPLH & tPHL
Propagation Delay INA to OAn, INB to OBn
CL = 15pF
2.6
ns
tPZH or tPZL
Output Enable Time
CL = 15pF
2.5
ns
tPHZ or tPLZ
Output Disable Time
CL = 15pF
2.5
ns
Rise/Fall Time
0.8V – 2.0V
0.8
ns
tr/tf
tsk(p)
Pulse Skew (Same Package)
CL = 15pF, 125MHz
0.1
ns
tsk(o)
Output Pin to Pin Skew (Same Package)
CL = 15pF, 125MHz
0.25
ns
Output Skew (Different Package)
CL = 15pF, 125MHz
0.4
ns
tsk(pp)
fmax
Input Frequency
CL = 50pF
150
MHz
fmax
Input Frequency
CL =15pF
300
MHz
fmax
Input Frequency
CL = 5pF
550
MHz
fmax
Input Frequency
CL = 2pF
750
MHz
Notes:
1. See test circuits and waveforms.
2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested.
3. Airflow of 1m/s is recommended for frequencies above 133MHz
3
Copyright © 2005, Potato Semiconductor Corporation
PO49FCT3806
3.3V Dual 1:5 CMOS Invert Clock Buffered Driver
11/22/05
750MHz TTL/CMOS Potato Chip
Test Waveforms
Test Circuit
500 Ω
50Ω
50 Ω
500 Ω
4
Copyright © 2005, Potato Semiconductor Corporation
PO49FCT3806
3.3V Dual 1:5 CMOS Invert Clock Buffered Driver
750MHz TTL/CMOS Potato Chip
11/22/05
Packaging Mechanical Drawing: 20 pin QSOP
Packaging Mechanical Drawing: 20 pin SOIC
5
Copyright © 2005, Potato Semiconductor Corporation
PO49FCT3806
3.3V Dual 1:5 CMOS Invert Clock Buffered Driver
750MHz TTL/CMOS Potato Chip
01/05/06
Ordering Information
Ordering Code
PO49FCT3806S
PO49FCT3806Q
Package Code
S
Q
Package Description
Pb-free & Green, 20-pin SOIC
Pb-free & Green, 20-pin QSOP
6
Copyright © 2005, Potato Semiconductor Corporation