PO74HSTL85352A www.potatosemi.com LVCMOS Input to HSTL Output 1:2 Fanout Buffer 300MHz TTL/CMOS Potato Chip DESCRIPTION: FEATURES: . Patented Technology . Two HSTL differential outputs . Two single LVTTL/LVCMOS inputs . Operating frequency up to 300MHz with 15 pf load . Very low output pin to pin skew < 30ps . 3.2-ns propagation delay (max) . 2.4V to 3.6V power supply . Industrial temperature range: –40°C to 85°C . 14-pin TSSOP package Pin Configuration 1 14 VCC CLK_EN 2 13 Q0 3 12 nQ0 CLK0 4 11 nc VEE 5 10 Q1 CLK1 6 9 nQ1 VCC 7 8 VCC Potato Semiconductor Corporation The device features two single-ended input paths that are multiplexed internally. This mux is controlled by the CLK_SEL pin. The PO74HSTL85352A functions as a signal-level translator and fanout on LVCMOS / LVTTL single-ended signal to two pair of HSTL differential loads. Since the PO74HSTL85352A introduces negligible jitter to the timing budget, it is the ideal choice for distributing high frequency, high precision clocks across back-planes and boards in communication systems. Logic Block Diagram VEE CLK_SEL The PO74HSTL85352A is a low-skew, 1-to-2 differential fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications. The device is implemented on CMOS technology and has a fully differential internal architecture that is optimized to achieve low signal skews at operating frequencies of up to 300MHz . D CLK_EN LE CLK0 0 CLK1 1 CLK_SEL 1 Q Q0 nQ0 Q1 nQ1 01/01/10 PO74HSTL85352A www.potatosemi.com LVCMOS Input to HSTL Output 1:2 Fanout Buffer 300MHz TTL/CMOS Potato Chip Pin Definitions Name Pin I/O Description Type 7, 8,14 VCC VCC 11 NC 3 CLK_SEL I,PD LVCMOS Input clock select with pull down resistor 2 CLK_EN I,PU LVCMOS Clock enabled 4 CLK0 I,PD LVCMOS, LVTTL LVCMOS, LVTTL clock Input 6 CLK1 I,PD LVCMOS, LVTTL LVCMOS, LVTTL clock Input 1, 5 VEE Power Power Ground 12, 9 Q[0:1]# GND O HSTL Complement output 13, 10 Q[0:1] O HSTL Ture output Power Power supply, positive connection No connect Control Input Function Table Inputs CLK_EN 0 CLK_SEL 0 Selected Source C LK 0 Q0, Q1 Disabled; LOW 1 0 C LK 0 Enabled 0 1 1 1 C LK 1 C LK 1 Outputs Disabled; LOW nQ0, nQ1 Disabled; HIGH Disabled; HIGH Enabled Enabled Enabled Function Table Inputs CLK0 or CLK1 0 1 Q0, Q1 LOW HIGH Outputs nQ0, nQ1 HIGH LOW Pin Characteristics Symbol Parameter CIN Input Capacitance RPULLDOWN Input Pulldown Resistor RPULLUP Test Conditions Input Pullup Resistor Potato Semiconductor Corporation Minimum Typical 4 88 88 2 Maximum Units pF K K 01/01/10 PO74HSTL85352A www.potatosemi.com LVCMOS Input to HSTL Output 1:2 Fanout Buffer 300MHz TTL/CMOS Potato Chip Maximum Ratings Description Max Unit Storage Temperature -65 to 150 °C Operation Temperature -40 to 85 °C Operation Voltage -0.5 to +4.6 V Input Voltage -0.5 to +5.5 V Output Voltage -0.5 to Vcc+0.5 V Note: stresses greater than listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability specification is not implied. DC Electrical Characteristics Symbol Description VOH Output High voltage VOL VIK Test Conditions Min Typ Max Unit Vcc=3V Vin=VIH or VIL, IOH= -12mA 2.4 3 - V Output Low voltage Vcc=3V Vin=VIH or VIL, IOH=12mA - 0.3 0.5 V Clamp diode voltage Vcc = Min. And IIN = -18mA - -0.7 -1.2 V Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Notes: 1. 2. 3. 4. 5. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25 °C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. VoH = Vcc – 0.6V at rated current Potato Semiconductor Corporation 3 01/01/10 PO74HSTL85352A www.potatosemi.com LVCMOS Input to HSTL Output 1:2 Fanout Buffer 300MHz TTL/CMOS Potato Chip Power Supply Characteristics Symbol IccQ Description Quiescent Power Supply Current Test Conditions (1) Min Typ Max Unit Vcc=Max, Vin=Vcc or GND - 0.1 30 uA Notes: 1. 2. 3. 4. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25°C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. Switching Characteristics Symbol tPD tr/tf tsk(o) tsk(pp) fmax Description Test Conditions (1) M ax Unit CL = 15pF 3.2 ns 0.8V – 2.0V Output Pin to Pin Skew (Same Package) CL = 15pF, 125MHz 0.8 30 ns ps Output Skew (Different Package) CL = 15pF, 125MHz 350 ps CL =15pF 300 250 MHz Propagation Delay CLKA or CLKB to Output pair Rise/Fall Time Input Frequency Notes: 1. See test circuits and waveforms. 2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested. 3. Airflow of 1m/s is recommended for frequencies above 133MHz Potato Semiconductor Corporation 4 01/01/10 PO74HSTL85352A www.potatosemi.com LVCMOS Input to HSTL Output 1:2 Fanout Buffer 300MHz TTL/CMOS Potato Chip Test Waveforms FIGURE 1. LVTTL/LVCMOS INPUT WAVEFORM DEFINITION 3V 1.5V Input 0V FIGURE 2. HSTL OUTPUT tr,tf, 20-80% VO FIGURE 3. Propogation Delay, Output pulse skew, and output-to-output skew for D to output pair INPUT CLOCK TPLH TPD TPHL OUTPUT CLOCK VO tSK(O) ANOTHER OUTPUT CLOCK FIGURE 4. CLK_EN Timing Diagram Enabled Disabled CLK CLK_EN nQ0:nQ3 Q0:Q3 Potato Semiconductor Corporation 5 01/01/10 PO74HSTL85352A www.potatosemi.com LVCMOS Input to HSTL Output 1:2 Fanout Buffer 300MHz TTL/CMOS Potato Chip Test Circuit Vcc Pulse Generator 15pF to 2pF D.U.T 15pF to 2pF 50Ohm Packaging Mechanical Drawing: 14 pin TSSOP 14 0.169 0.177 1 0.0256 typical 0.65 Potato Semiconductor Corporation 0.193 0.201 4.90 5.10 0.007 0.012 0.240 0.264 4.3 4.5 6.1 6.7 0.047 1.20 max. 0.19 0.30 SEATING PLANE 0.002 0.05 0.006 0.15 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS 6 01/01/10 PO74HSTL85352A www.potatosemi.com LVCMOS Input to HSTL Output 1:2 Fanout Buffer 300MHz TTL/CMOS Potato Chip IC Ordering Information Ordering Code Package Top-Marking TA 14pin 173mil TSSOP Pb-free & Green PO74HSTL85352AS -40°C to 85°C PO74HSTL85352ASR for Tape & Reel 14pin 173mil TSSOP Pb-free & Green PO74HSTL85352AS -40°C to 85°C PO74HSTL85352ASU for Tube IC Package Information PACKAGE CODE T PACKAGE TYPE 14pin 173mil TSSOP Potato Semiconductor Corporation TAPE WIDTH (mm) TAPE PITCH (mm) TAPE & REEL PIN 1 LOCATION TAPE TRAILER LENGTH 12 8 Top Left Corner 39 (12”) 7 QTY PER TAPE 3000 TAPE LEADER LENGTH QTY PER TUBE 64 (20”) 96 01/01/10