RD74VT1G245 Bus Transceiver with 3–state Output / Dual Supply Voltage Translator REJ03D0494–0200 Rev.2.00 Apr. 01, 2005 Description The RD74VT1G245 has one buffer in a 6 pin package. When DIR is high, data is transferred from the A inputs to the B outputs, and when DIR is low, data is transferred from the B inputs to the A outputs. And this product has two terminals (VCCA, VCCB), VCCA is connected with control input and A bus side VCCB is connected with B bus side. VCCA and VCCB are isolated. The A port is designed to track VCCA, which accepts voltages from 1.2V to 3.6V, and the B port is designed to track VCCB, which operation at 1.2V to 3.6V. Therefore, Bidirectional board voltage conversion is possible. Low voltage and high-speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption extends the battery life. Features • This product function as level shift transceiver that change VCCA input level to VCCB output level, VCCB input level to VCCA output level by providing different supply voltage to VCCA and VCCB. • Supply voltage range: VCCA = 1.2 to 3.6 V VCCB = 1.2 to 3.6 V 40 to +85°C • Operating temperature range: −40 • Control input VI(max) = 3.6 V (@VCCA = 0 to 3.6 V) • A bus side input outputs VI/O (max) = 3.6 V (@VCCA = 0 V or Output off state) • B bus side input outputs VI/O (max) = 3.6 V (@VCCB = 0 V or Output off state) • High output current A bus side: ±2 mA (@VCCA = 1.2 V) B bus side: ±2 mA (@VCCB = 1.2 V) ±4 mA (@VCCA = 1.5±0.1 V) ±4 mA (@VCCB = 1.5±0.1 V) ±6 mA (@VCCA = 1.8±0.15 V) ±6 mA (@VCCB = 1.8±0.15 V) ±18 mA (@VCCA = 2.5±0.2 V) ±18 mA (@VCCB = 2.5±0.2 V) ±24 mA (@VCCA = 3.3±0.3 V) ±24 mA (@VCCB = 3.3±0.3 V) • Ordering Information Part Name RD74VT1G245CLE Package Type Package Code (Previous Code) Package Abbreviation WCSP–6 pin SXBG0006KB–A (TBS–6AV) CL Rev.2.00 Apr. 01, 2005 page 1 of 13 Taping Abbreviation (Quantity) E (3,000 pcs / reel) RD74VT1G245 Article Indication Marking Year code Month code VYYM Function Table Input DIR Operation L B→A H A→B H: High level L: Low level Pin Arrangement 0.9 mm 3 4 A 2 5 DIR 1 6 (Bottom view) Rev.2.00 Apr. 01, 2005 page 2 of 13 B VCCB 1.4 mm Height 0.5 mm 0.5 mm pitch 0.23 mm 6–Ball (CL) GND Pin#1 INDEX VCCA (Top view) RD74VT1G245 Logic Diagram DIR A B Absolute Maximum Ratings Item Supply voltage range Input voltage range *1 Input/output voltage range *1, 2 Symbol Ratings Unit VCCA, VCCB –0.5 to 4.6 V VI –0.5 to 4.6 V DIR VI/O –0.5 to VCCA+0.5 V A port output: “H” or “L” –0.5 to 4.6 A port output: “Z” or VCCA: OFF –0.5 to VCCB+0.5 B port output: “H” or “L” –0.5 to 4.6 B port output: “Z” or VCCB: OFF Input clamp current IIK –50 mA Output clamp current IOK –50 mA 50 IO ±50 mA Continuous output current VCC or GND ICCA, ICCB, IGND ±100 mA θja 123 °C/W Tstg –65 to 150 °C Storage temperature Notes: VI < 0 VO < 0 VO > VCC+0.5 Continuous output current Package Thermal impedance Conditions The absolute maximum ratings are values, which mu must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.6 V maximum. Rev.2.00 Apr. 01, 2005 page 3 of 13 RD74VT1G245 Recommended Operating Conditions Item Supply voltage range Input/Output voltage Symbol Ratings Unit VCCA 1.2 to 3.6 V VCCB 1.2 to 3.6 VI 0 to 3.6 V DIR VI/O 0 to VCCA V A port output: “H” or “L” 0 to 3.6 A port output: “Z” or VCCA: OFF 0 to VCCB B port output: “H” or “L” 0 to 3.6 Output current IOHA IOHB –2 B port output: “Z” or VCCB: OFF mA VCCA = 1.5±0.1 V –6 VCCA = 1.8±0.15 V –18 VCCA = 2.5±0.2 V –24 VCCA = 3.3±0.3 V –2 mA VCCB = 1.2 V –4 VCCB = 1.5±0.1 V –6 VCCB = 1.8±0.15 V –18 VCCB = 2.5±0.2 V 2 VCCB = 3.3±0.3 V mA VCCA = 1.2 V 4 VCCA = 1.5±0.1 V 6 VCCA = 1.8±0.15 V 18 VCCA = 2.5±0.2 V 24 IOLB VCCA = 1.2 V –4 –24 IOLA 2 VCCA = 3.3±0.3 V mA VCCB = 1.2 V 4 VCCB = 1.5±0.1 V 6 VCCB = 1.8±0.15 V 18 VCCB = 2.5±0.2 V VCCB = 3.3±0.3 V 24 Input transition rise or fall time ∆t / ∆v 10 ns / V Operation free-air temperature Ta –40 to 85 °C Rev.2.00 Apr. 01, 2005 page 4 of 13 Conditions RD74VT1G245 Electrical Characteristics (Ta = −40 to 85°C) Item Input voltage Symbol VIHA VIHB VILA VILB Output voltage VOH * VCCA (V) 1.2 1.5±0.1 1.8±0.15 2.5±0.2 3.3±0.3 1.2 to 3.6 1.2 1.5±0.1 1.8±0.15 2.5±0.2 3.3±0.3 1.2 to 3.6 * VCCB (V) 1.2 to 3.6 Typ Max VCCA×0.25 VCCA×0.30 VCCA×0.35 0.7 0.8 VCCB×0.25 VCCB×0.30 VCCB×0.35 0.7 0.8 0.2 0.3 0.3 0.3 0.6 0.55 1.5 Unit V 1.2 1.5±0.1 1.8±0.15 2.5±0.2 3.3±0.3 1.2 to 3.6 1.2 1.5±0.1 1.8±0.15 2.5±0.2 3.3±0.3 1.2 to 3.6 1.2 1.5±0.1 1.8±0.15 2.5±0.2 3.3±0.3 3.6 Min VCCA×0.75 VCCA×0.70 VCCA×0.65 1.6 2.0 VCCB×0.75 VCCB×0.70 VCCB×0.65 1.6 2.0 VCC−0.2 0.9 1.1 1.25 1.7 2.2 –1.5 1.2 1.5±0.1 1.8±0.15 2.5±0.2 3.3±0.3 1.2 to 3.6 Test conditions A port Control input V B port V A port Control input V B port V IOH = –100 µA IOH = –2 mA IOH = –4 mA IOH = –6 mA IOH = –18 mA IOH = –24 mA IOL = 100 µA IOL = 2 mA IOL = 4 mA IOL = 6 mA IOL = 18 mA IOL = 24 mA VIN = GND or VCCA control input VIN = VIH or VIL Input current IIN 1.2 to 3.6 1.2 1.5±0.1 1.8±0.15 2.5±0.2 3.3±0.3 1.2 to 3.6 1.2 1.5±0.1 1.8±0.15 2.5±0.2 3.3±0.3 3.6 Off state output current Output leakage current Quiescent supply current IOZ 3.6 3.6 –1.5 1.5 µA IOFF 0 0 1.5 µA ICCA 1.2 to 3.6 1.2 to 3.6 –3.0 3.0 µA ICCB 1.2 to 3.6 1.2 to 3.6 –3.0 3.0 ∆ICCA 3.6 3.6 250 ∆ICCB 3.6 3.6 250 CIN 3.3 3.3 3.5 pF VIN, VOUT = 0 to 3.6 V IO(A port) = 0 VIN = VCCB or GND IO(B port) = 0 VIN = VCCA or GND A port or control VCCA–0.6 (1 input) B port VCCB–0.6 (1 input) VIN = VCC or GND CI/O 3.3 3.3 6.0 pF VO = VCC or GND VOL Increase in ICC per input Input capacitance Input/output capacitance V µA µA Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. Rev.2.00 Apr. 01, 2005 page 5 of 13 RD74VT1G245 Switching Characteristics VCCA = 3.3±0.3 V Ta = –40 to 85°C Item Propagation delay time VCCB= VCCB= 1.2 V 1.5±0.1 V From To Symbol (input) (output) Typ Min Max tPLH A B tPHL tPLH B A tPHL Output tHZ Disable time tLZ tHZ DIR A *1 tZH Enable time tZL Note: VCCB= 3.3±0.3 V Min Max Min Max Min Test Max Unit conditions 9.1 2.0 8.8 1.5 5.8 1.0 4.0 1.0 3.2 9.1 2.0 8.8 1.5 5.8 1.0 4.0 1.0 3.2 4.0 1.0 4.2 1.0 3.8 1.0 3.4 1.0 3.2 4.0 1.0 4.2 1.0 3.8 1.0 3.4 1.0 3.2 4.0 1.0 4.5 1.0 4.5 1.0 4.5 1.0 4.5 4.0 1.0 4.5 1.0 4.5 1.0 4.5 1.0 4.5 8.0 1.0 6.0 1.0 5.5 B 11.2 2.0 10.2 1.5 11.2 2.0 10.2 1.5 8.0 1.0 6.0 1.0 5.5 DIR A 15.2 14.4 11.8 9.4 8.7 15.2 14.4 11.8 9.4 8.7 *1 tZH*1 tZL*1 VCCB= 2.5±0.2 V DIR tLZ Output VCCB= 1.8±0.15 V DIR B 13.1 13.3 10.3 8.5 7.7 13.1 13.3 10.3 8.5 7.7 ns CL = 15pF RL = 2.0kΩ ns CL = 15pF RL = 2.0kΩ ns CL = 15pF RL = 2.0kΩ 1. The enable time is a calculated value, derived using ing the formula shown in the section entitled enable times on page 12. VCCA = 2.5±0.2 V Ta = –40 to 85°C Item Propagation delay time From To Symbol (input) (output) tPLH A B tPHL tPLH B A DIR A tPHL Output tHZ Disable time tLZ tHZ DIR B tLZ Output tZH*1 Enable time tZL*1 tZH*1 tZL Note: DIR DIR A B *1 VCCB= 1.2 V Typ VCCB= 1.5±0.1 V VCCB= 1.8±0.15 V VCCB= 2.5±0.2 V VCCB= 3.3±0.3 V Min Min Min Min Max Max Max Test Max Unit conditions 9.5 2.0 9.2 1.5 6.0 6. 1.0 4.2 1.0 3.4 9.5 2.0 9.2 1.5 6. 6.0 1.0 4.2 1.0 3.4 4.7 1.0 4.8 1.0 4.6 4. 1.0 4.2 1.0 4.0 4.7 1.0 4.8 1.0 4. 4.6 1.0 4.2 1.0 4.0 4.2 1.0 4.7 1.0 4.7 4. 1.0 4.7 1.0 4.7 4.2 1.0 4.7 1.0 4. 4.7 1.0 4.7 1.0 4.7 11.2 2.0 10.6 1.5 8.4 1.0 6.0 1.0 6.0 11.2 2.0 10.6 1.5 8.4 8. 1.0 6.0 1.0 6.0 15.9 15.4 13.0 10.2 10.0 15.9 15.4 13.0 10.2 10.0 13.7 13.9 10.7 8.9 8.1 13.7 13.9 10.7 8.9 8.1 ns CL = 15pF RL = 2.0kΩ ns CL = 15pF RL = 2.0kΩ ns CL = 15pF RL = 2.0kΩ 1. The enable time is a calculated value, derived using the formula shown in the section entitled enable times on page 12. Rev.2.00 Apr. 01, 2005 page 6 of 13 RD74VT1G245 Switching Characteristics (Cont.) VCCA = 1.8±0.15 V Ta = –40 to 85°C Item Propagation delay time VCCB= VCCB= 1.2 V 1.5±0.1 V From To Symbol (input) (output) Typ Min Max tPLH A B tPHL tPLH B A tPHL Output tHZ Disable time tLZ tHZ DIR A DIR B DIR A tLZ *1 Output tZH Enable time tZL *1 tZH*1 tZL*1 Note: DIR B VCCB= 1.8±0.15 V VCCB= 2.5±0.2 V VCCB= 3.3±0.3 V Min Max Min Max Min Test Max Unit conditions 9.8 2.0 9.6 1.5 6.5 1.0 4.6 1.0 3.8 9.8 2.0 9.6 1.5 6.5 1.0 4.6 1.0 3.8 6.4 1.5 7.2 1.5 6.5 1.5 6.0 1.5 5.8 6.4 1.5 7.2 1.5 6.5 1.5 6.0 1.5 5.8 5.5 1.5 7.5 1.5 7.5 1.5 7.5 1.5 7.5 5.5 1.5 7.5 1.5 7.5 1.5 7.5 1.5 7.5 12.0 2.0 11.5 1.5 9.2 1.0 7.2 1.0 7.0 12.0 2.0 11.5 1.5 9.2 1.0 7.2 1.0 7.0 18.4 18.7 15.7 13.2 12.8 18.4 18.7 15.7 13.2 12.8 15.3 17.1 14.0 12.1 11.3 15.3 17.1 14.0 12.1 11.3 ns CL = 15pF RL = 2.0kΩ ns CL = 15pF RL = 2.0kΩ ns CL = 15pF RL = 2.0kΩ 1. The enable time is a calculated value, derived using ing the formula shown in the section entitled enable times on page 12. VCCA = 1.5±0.1 V Ta = –40 to 85°C Item Propagation delay time From To Symbol (input) (output) tPLH A B tPHL tPLH B A DIR A tPHL Output tHZ Disable time tLZ tHZ DIR B tLZ Output tZH*1 Enable time tZL*1 tZH*1 tZL Note: DIR DIR A B *1 VCCB= 1.2 V Typ VCCB= 1.5±0.1 V VCCB= 1.8±0.15 V VCCB= 2.5±0.2 V VCCB= 3.3±0.3 V Min Min Min Min Max Max Max Test Max Unit conditions 10.0 2.0 10.5 1.5 7.2 1.0 4.8 1.0 4.2 10.0 2.0 10.5 1.5 7.2 7. 1.0 4.8 1.0 4.2 8.0 2.0 10.5 2.0 9.6 2.0 9.2 2.0 8.8 8.0 2.0 10.5 2.0 9. 9.6 2.0 9.2 2.0 8.8 6.0 2.0 10.0 2.0 10.0 10. 2.0 10.0 2.0 10.0 6.0 2.0 10.0 2.0 10. 10.0 2.0 10.0 2.0 10.0 12.5 2.0 12.7 1.5 12.0 12. 1.0 10.7 1.0 7.5 12.5 2.0 12.7 1.5 12.0 12. 1.0 10.7 1.0 7.5 20.5 23.2 21.6 19.9 16.3 20.5 23.2 21.6 19.9 16.3 16.0 20.5 17.2 14.8 14.2 16.0 20.5 17.2 14.8 14.2 ns CL = 15pF RL = 2.0kΩ ns CL = 15pF RL = 2.0kΩ ns CL = 15pF RL = 2.0kΩ 1. The enable time is a calculated value, derived using the formula shown in the section entitled enable times on page 12. Rev.2.00 Apr. 01, 2005 page 7 of 13 RD74VT1G245 Switching Characteristics (Cont.) VCCA = 1.2 V Ta = –40 to 85°C Item Propagation delay time From To Symbol (input) (output) tPLH A B tPHL tPLH B A tPHL Output tHZ Disable time tLZ tHZ DIR A *1 tZH Enable time tZL Note: VCCB= 3.3±0.3 V Typ Typ Typ Typ Typ 10.5 8.0 6.4 4.7 4.0 10.5 8.0 6.4 4.7 4.0 10.5 10.0 9.8 9.5 9.1 10.5 10.0 9.8 9.5 9.1 8.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0 10.5 9.5 7.5 7.5 B 13.5 13.5 10.5 9.5 7.5 7.5 DIR A 24.0 20.5 19.3 17.0 16.6 24.0 20.5 19.3 17.0 16.6 18.5 16.0 14.4 12.7 12.0 18.5 16.0 14.4 12.7 12.0 *1 tZH*1 tZL*1 VCCB= VCCB= VCCB= 1.5±0.1 V 1.8±0.15 V 2.5±0.2 V DIR tLZ Output VCCB= 1.2 V DIR B Test Unit conditions ns CL = 15pF RL = 2.0kΩ ns CL = 15pF RL = 2.0kΩ ns CL = 15pF RL = 2.0kΩ 1. The enable time is a calculated value, derived using ing the formula shown in the section entitled enable times on page 12. Operating Characteristics Ta = 25°C Item Power dissipation capacitance Symbol VCCA (V) VCCB (V) Min CPD 3.3 3.3 Typ 12 Max Unit pF Test conditions f = 10 MHz CL = 0 Power–up considerations Level–translation devices offer an opportunity for successful mixed–voltage signal design. A proper power–up sequence always should be followed to aavoid excessive supply current, bus contention, oscillations, or other anomalies caused by improperly biased device pins. Take these precautions to guard against such power–up problems. 1. Connect ground before any supply voltage is applied. 2. Next, power up the control side of the device. (Power up of VCCA is first. Next power up is VCCB) 3. Depending on the direction of the data path, DIR can be high or low. If DIR high is needed (A data to B bus), ramp it with VCCA. Otherwise, DIR low is needed (B data to A bus), ramp it with GND. Rev.2.00 Apr. 01, 2005 page 8 of 13 RD74VT1G245 Test Circuit See under table 2 kΩ S1 OPEN GND *1 CL = 15 pF 2 kΩ Load circuit for outputs Symbol S1 t PLH / tPHL OPEN t ZH / t HZ GND t ZL / t LZ 2 × VCC Note: 1. CL includes probe and jig capacitance. Rev.2.00 Apr. 01, 2005 page 9 of 13 RD74VT1G245 • Waveforms – 1 tr tf Vref Input VIH 90 % Vref 90 % 10 % 10 % t PLH GND t PHL VOH output Vref Vref VOL • Waveforms – 2 Input DIR tr tf 90 % Vref 10 % 90 % 90 % 10 % t ZL 10 % GND VOH Output A or B Waveform–1 Vref VL t ZH Output A or B Waveform–2 Symbol VIH 90 % Vref 10 % t LZ VOL t HZ VOH VH Vref VOL V CC = 1.2 V, 0.1 V 1.5±0.1 V CC = 1.8 1.8±0.15 V V CC = 2.5 2.5±0.2 V V CC = 3.3±0.3 V tr / t f 2.0 ns 2.0 ns 2.0 ns 2.0 ns V IH VCC VCC VCC VCC V ref 1/2 VCC 1/2 VCC 1/2 VCC 1/2 VCC VH / V L VH = VOH-0.1 V VL = VOL+0.1 V VH = VOH-0.15 V VH = VOH-0.15 V VH = VOH-0.3 V VL = VOL+0.15 V VL = VOL+0.15 V VL = VOL+0.3 V Notes: 1. Input waveform : PRR ≤ 10 MHz, Zo = 50 Ω, duty cycle 50%. 2. Waveform – 1 is for an output with internal conditions such that the output is low except when disabled by the output control. 3. Waveform – 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 4. The output are measured one at a time with one transition per measurement. Rev.2.00 Apr. 01, 2005 page 10 of 13 RD74VT1G245 Application Information Figure 1 is an example circuit of the RD74VT1G245 being used in a bidirectional logic level–shifting application. VCC1 VCC2 1 6 VCC1 VCC2 2 5 3 4 SYSTEM–2 SYSTEM–1 Figure 1. Bidirectional Logic Level–Shifting Application Pin Description PIN NAME FUNCTION 1 DIR DIR The GND (low–level) determines B–port to A–port direction 2 A OUT Output level depends on VCC1 voltage 3 GND GND 4 B IN 5 VCCB VCC2 SYSTEM–2 supply voltage (1.2V to 3.6V) 6 VCCA VCC1 SYSTEM–1 supply voltage (1.2V to 3.6V) Rev.2.00 Apr. 01, 2005 page 11 of 13 DESCRIPTION Device GND Input threshold value depends on VCC2 voltage RD74VT1G245 Application Information (Cont.) Figure 2 shows the RD74VT1G245 used in a bidirectional logic level–shifting application. Since the RD74VT1G245 does not have an output enable (OE) pin, the system designer should take precautions to avoid bus contention between SYSTEM–1 and SYSTEM–2 when changing directions. VCC1 VCC1 VCC2 VCC2 Pullup/Down or Bus–Hold* Pullup/Down I/O–1 DIR CTRL 1 6 2 5 3 4 or Bus–Hold* SYSTEM–1 Notes: I/O–2 SYSTEM–2 Following is a sequence that illustrates data transmission from SYSTEM–1 to SYSTEM–2 and then from SYSTEM–2 to SYSTEM–1. STATE DIR CTRL I/O–1 I/O–2 DESCRIPTION 1 H IN OUT SYSTEM–1 data to SYSTEM–2 2 H HI–Z HI–Z SYSTEM–2 is getting ready to send data to SYSTEM–1. I/O–1 and I/O–2 are disabled. The bus–line state depends on Pull–up or Down.* 3 L HI–Z HI–Z DIR bit is flipped. I/O–1 and I/O–2 are atill disabled. The bus–line state depends on Pull–up or Down.* 4 L OUT IN SYSTEM–2 data to SYSTEM–1 *: SYSTEM–1 and SYSTEM–2 must use same conditions, i.e., both pull–up or both pull–down. Figure 2. Bidirectional Logic Level-Shifting Application Calculate the enable times for the RD74VT1G245 using the following formulas: 1. tZH (DIR to A) = tLZ (DIR to B) + tPLH (B to A) 2. tZL (DIR to A) = tHZ (DIR to B) + tPHL (B to A) 3. tZH (DIR to B) = tLZ (DIR to A) + tPLH (A to B) 4. tZL (DIR to B) = tHZ (DIR to A) + tPHL (A to B) In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is switched until an output is expected. For example, if the RD74VT1G245 initially is transmitting from A to B, then the DIR bit is switched, the B port of the device must be disabled before presenting it with an input. After the B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified propagation delay. Rev.2.00 Apr. 01, 2005 page 12 of 13 RD74VT1G245 Package Dimensions JEITA Package Code S-XFBGA6-0.9x1.4-0.50 RENESAS Code SXBG0006KB-A Previous Code TBS-6AV MASS[Typ.] 0.001g e ZD D ZE C E B e B A 1 Pin#1 index area 2 A 6 × φb y1 C φ× M C A B φ× M C Reference Symbol * Reference value. Rev.2.00 Apr. 01, 2005 page 13 of 13 Max 0.50 A1 0.155 0.185 (0.315) * A2 0.25 0.20 D 0.90 E 1.40 e 0.50 x 0.05 y 0.05 A A1 y C A2 Seating plane Nom A b C Dimension in Millimeters Min 0.20 y 1 Z D 0.20 Z E 0.20 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. 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