STB4395 CT2 RECEIVER/TRANSMITTER . .. .. .. .. .. . ADVANCE DATA FULLY INTEGRATED DOUBLE SUPERHETERODYNE RECEIVER OPERATION FROM 800MHz TO 1000MHz RECEIVER OUTPUT AS BITSTREAM FULLY INTEGRATED TRANSMITTER TRANSMITTER INPUT I/Q/REFIQ OR I/I, Q/Q INTEGRATED POWER AMPLIFIER CT2 PA SWITCH-ON PROFILE INTEGRATED VCO’s INTEGRATED SYNTHESIZERS INTEGRATED CHANNEL SELECT LOGIC ON CHIP INTEGRATED VOLTAGE REGULATION SUPPLY VOLTAGES FROM 3.0V TO 5.5V DESCRIPTION The STB4395(A) is a fully integrated receivertransmitter designed for CT2 applications, and incorporates all the VCO’s, synthesizers, PLLs, and channel select logic, to make a fully functional ”single chip” radio. The receiver is of the double superhet architecture and operates from an aerial input (via a SAW filter) to bitstream output to CT2 format, whilst the transmitter operates from I/Q inputs to +13dBm at the final frequency. A single (external) frequency reference is all that is required to give full coverage over the range of 800 to 1000MHz.The on-off slope of the Transmit PAis governed internally to give the required switch-on ramp, whilst the output can be swiched from low to high power by means of an external digital control signal. The channelselect is controlled from a digital serial input, and allows continuous channel control from 800 to 1000MHz. T h e S TB 4 3 9 5 e x is t s in t wo v ersio n s: the STB4395, which has I/I, Q/Q transmit data input/outputs, is designed to operate with the SGS-THOMSON baseband companion part, the ST5095. The STB4395A has a 3 wire I/Q interface and is compatible with commercially available I/Q transmit data baseband IC’s. TQFP64 (Plastic Package) ORDER CODE : STB4395 or STB4395A April 1996 This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without no tice. 1/16 STB4395 CONTENT Page 1 PIN DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 1.2 1.3 1.4 1.5 PIN CONNECTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PIN LIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ANALOG AND FILTER PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIGITAL, SIGNAL AND CONTROL PINS. . . . . . . . . . . . . . . . . . . . POWER SUPPLY PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................ ... ... .... . .. ... ................ .. .. . .. . .. . . . . . . .. .. . .. . .. .. .. . . 4 5 5 6 6 2 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 3.1 3.2 3.3 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RECEIVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TRANSMITTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CHANNEL SELECT CONTROL LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 8 8 4 ABSOLUTE MAXIMUM RATINGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 POWER SUPPLIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.1 5.2 SUPPLIES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GROUND PLANE CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 9 6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 TIMING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.1 7.2 TURN ON-OFF TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CHANNEL SELECT TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 9 8 8.1 8.2 TRANSCEIVER SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RECEIVER-INPUT SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TRANSMITTER OUTPUT SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10 11 8.3 8.3.1 8.3.2 8.3.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 SYNTHESIZER/MODULATOR/CHANNEL SELECT LOOP . . . . . . . . . . . . . . . . . . . . . . Synthesizer phase noise and spurious . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel select loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel frequency setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SYSTEM CLOCK INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RECEIVER -RF INPUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIGITAL INPUT BUFFERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIGITAL OUTPUT BUFFERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RECEIVER- FSH TRI STATE INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RECEIVER- RSSI OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . POWER DOWN BUFFER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 11 12 13 13 13 13 13 14 14 8.11 8.11.1 8.11.2 TRANSMITTER - DATA INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STB4395A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STB4395 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 14 9 9.1 9.1.1 9.1.2 9.2 9.2.1 9.2.2 APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TYPICAL DC CONNECTION SCHEMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . APPLICATION CIRCUIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15 15 15 15 15 15 10 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2/16 STB4395 1 - PIN DESCRIPTION 1.1 - Pin Connections VNRF SAWI NSAWI VRRF VNPA VPRF1 NRF RF VPRF2 ADJPWR SHAPE TXFLT NTXFLT VPD VRD VND STB4395 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 NPRGEN 1 48 VNIF P RGCLK 2 47 SAWO P RGD 3 46 NSAWO NTXEN 4 45 VPIF LOCK 5 44 NIF2O I 6 43 IF2O NI 7 42 DEC NQ 8 TQFP64 41 IF2I Q 9 (from above ) 40 NIF2I EN 10 39 NDEC VNOSC 11 38 VRIF S YNCLK 12 37 RSSI VRO 13 36 VRI VCOO 14 35 VCOI NVCOO 15 34 NVCOI FLTRO 16 33 FLTRI BRF3 BRF1 DISCI DISCO BRF2 VPI VPRF1 VNPA VRRF NSAWI SAWI VNRF 4395-01.EPS VPS2 NVCOS VPRF2 NRF VPS1 ADJPWR VCOS VRS SHAPE RF FLTRS SLTC VPD TXFLT DO VRD FSH VPO VND 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NTXFLT STB4395A 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 NPRGEN 1 48 VNIF P RGCLK 2 47 SAWO P RGD 3 46 NSAWO NTXEN 4 45 VPIF LOCK 5 44 NIF2O I 6 43 IF2O REFIQ 7 42 DEC Q 8 TQFP64 41 IF2I FN 9 (from above ) 40 NIF2I EN 10 39 NDEC VNOSC 11 38 VRIF S YNCLK 12 37 RSSI VRO 13 36 VRI VCOO 14 35 VCOI NVCOO 15 34 NVCOI FLTRO 16 33 FLTRI 4395-02.EPS VPI BRF2 DISCO DISCI BRF1 BRF3 VPS2 VCOS NVCOS VPS1 VRS FLTRS FSH SLTC DO VPO 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 3/16 STB4395 1 - PIN DESCRIPTION (continued) 1.2 - Pin List Pin Name Description 1 2 3 4 5 6 7 8 9 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 NPRGEN PRGCLK PRGD NTXEN LOCK I NI NQ Q REFIQ Q FN EN VNOSC SYNCLK VRO VCOO NVCOO FLTRO VPO DO SLTC FSH FLTRS VRS VPS1 NVCOS VCOS VPS2 BRF3 BRF1 DISCI DISCO BRF2 VPI FLTRI NVCOI VCOI VRI RSSI VRIF NDEC NIF2I IF2I DEC IF2O NIF2O VPIF Serial Data Enable Serial Data Clock Serial Data Input Receive-Transmit Switch VCO Lock Detect-all 3 PLL I - Transmit Quadrature Input I - Transmit Quadrature Input Q-Transmit Quadrature Input Q-Transmit Quadrature Input IQ Reference Quadrature Transmit Input Q-Transmit Quadrature Input Forces Data Slicer Reference Time Constant To fast Power Down all functions except buffer Negative Power Supply all VCO ’s Synthesizer Clock Input PSU Regulated Negative Input for TX IF oscillator and pump circuit TX oscillator tank circuit TX Oscillator Tank Circuit Loop Filter for TX PLL Positive Battery Supply for TX oscillator Receive Data Output Slicer Time Constant Capacitor Data Slicer Time Constant Setting Loop Filter for channel PLL Regulated Negative Supply for channel oscillator and pump circuit Positive Battery Input for channel oscillator and pump circuit Channel Oscillator Tank Input Channel Oscillator Tank Input Positive Battery Supply Input for channel oscillator and pump circuit Bit Rate Filter3 Bit Rate Filter1 FM Discriminator Tank Circuit FM Discriminator Tank Circuit Bit Rate Filter 2 Positive Battery Supply for RXoscillator and pump circuit Loop Filter for RX oscillator RX Oscillator Tank Circuit RX Oscillator Tank Circuit Regulated Negative Supply for RX oscillator and pump circuit RSSI OUTPUT Regulated Negative Supply Output for RX sections RX IF2 Decoupling RX IF2 Filter Input RX IF2 Filter Input RX IF2 Decoupling RX IF2 Filter Output RX IF2 Filter Output Positive Battery Supply Input for RX sections 4/16 Ext. Connection and Suppl. Information STB4395 only STB4395 only STB4395 only STB4395A only STB4395A only STB4395A only f = 14.4MHz A.C. coupled C= 33nF 650 to 850MHz 650 to 850MHz STB4395 1 - PIN DESCRIPTION (continued) 1.2 - Pin List (continued) Pin 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Name NSAWO SAWO VNIF VNRF SAWI NSAWI VRRF VNPA VPRF1 NRF RF VPRF2 ADJPWR SHAPE TXFLT NTXFLT VPD VRD VND Description RX First IF Amplifier Input RX First IF Amplifier Input Negative Battery Supply Input for RX sections Negative Battery Supply Input for RF front end RX First Mixer Output RX First Mixer Output Regulated Negative Supply for RF front end Negative Supply for power amplifier Positive Battery Supply for RF front end Input LNA/Output PA Input LNA/Ouput PA Positive Battery Supply for RF front end Transmit Power Adjust Time Constant for PA on-off ramp Bandpass Filter for TX RF Bandpass Filter for TX RF Positive Battery Supply for digital circuitry Regulated Negative Supply for digital circuitry Negative Battery Supply for digital circuitry Ext. Connection and Suppl. Information R = 8.5kΩ to VRRF C = 560pF 1.3 - Analog and Filter Pins Pin 58 28 31 27 42, 39 29 30 33 16 21 6, 7 40, 41 43, 44 8, 9 7 56, 55 37 50, 51 47, 46 59 19 12 60, 61 35, 34 14, 15 25, 24 Symbol ADJPWR BRF1 BRF2 BRF3 DEC, NDEC DISCI DISCO FLTRI FLTRO FLTRS I, NI(1) IF2I, NIF2I IF2O, NIF2O Q, NQ(1) REFIQ RF, NRF RSSI SAWI, NSAWI SAWO, NSAWO SHAPE SLTC SYNCLK TXFLT/ NTXFLT VCOI, NVCOI VCOO, NVCOO VCOS, NVCOS Description Transmitter Output Power Adjust Bit Rate Filter1 Bit Rate Filter 2 Bit Rate Filter 3 RX IF2 Amplifier Decoupling FM Discriminator Tank Circuit FM Discriminator Tank Circuit Loop Filter for RX PLL Loop Filter for TX PLL Loop Filter for Channel PLL Transmit Quadrature Inputs ((1)STB4395 only) Inputs from 2nd IF Filter Outputs to 2nd IF Filter Q-Transmit Quadrature Input ((1)STB4395 only) IQ Reference Quadrature Transmit Input (STB4395A only) Input RX LNA/Ouput TX PA Received Signal Strength Indicator Output First Mixer Output First IF Amplifier Input Time Constant for PA on-off Ramp Slicer Time Constant Capacitor Synthesizer Clock Input 14.4MHz Bandpass Filter for TX RF Tank Circuit for 152.1MHz RX Oscillator Tank Circuit for 300.8MHz TX Oscillator Tank Circuit for 650 to 850MHz Channel Oscillator 5/16 STB4395 1 - PIN DESCRIPTION (continued) 1.4- Digital, Signal and Control Pins Pin Symbol Description Polarity 18 DO Receive Data Output 20 FSH Data Slicer Time Constant Setting (Fast/Slow/Hold) High: slow, tri-state: fast, low: hold DO goes high on hold (see next table) 9 FN Forces Data Slicer Reference Time Constant to fast (STB4395A only) low: fast (overides FSH) high: fast, slow or hold (set by FSH) 5 LOCK VCO lock detect-all 3 PLL high for LOCK (all three PLL’s) 3 PRGD Serial Synthesizer Data Input, 16 bits word high for logic 1. Input sequence: LO, D14, D13,...,D0. D14 is the MSB. LO: logic 1 is low transmit power. 1 NPRGEN Serial Synthesizer Data Enable low to enable PRGD buffer 2 PRGCLK Serial Data Clock held high when no clocking, clocks in data on positive edge 10 EN 4 NTXEN Power Down all functions except Enable Buffer high for power up, low for standby Receive-Transmit Switch high for receive, low for transmit The time constant of the data slicer is set through the pins FSH and FN for the STB4395A and through FSH only for the STB4395(FN internally connected to High), as listed in the following table : FN PIN FSH High Low High Slow, DO active Fast, DO active TriState Fast, DO active Fast, DO active Low Hold, DO high Fast, DO high 1.5 - Power Supply Pins Pin Symbol 64 VND Negative supply for digital regulators, digital input and output buffers Description 48 VNIF Negative supply for IF regulators, data output buffer 11 VNOSC 49 VNRF Negative supply RF regulators, quadrature input buffers 53 VNPA Negative supply for PA 62 VPD Positive supply for digital circuitry Negative supply for the oscillator regulators + substrate 32 VPI Positive supply for receive oscillator + charge pump 45 VPIF Positive supply for RX IF + baseband sections 17 VPO Positive supply for transmit oscillator + charge pump 54, 57 VPRF1 / VPRF2 23, 26 VPS1/ VPS2 63 VRD Regulated negative supply for digital circuitry 36 VRI Regulated negative supply for receive oscillator + charge pump 38 VRIF Regulated negative supply for RX IF + baseband sections 13 VRO Regulated negative supply for transmit oscillator + charge pump 52 VRRF 22 VRS 6/16 Positive supplies for RF front end Positive supplies for ch. select oscillator + charge pump Regulated negative supply for RF front end Regulated negative supply ch. select oscillator + charge pump STB4395 2 - BLOCK DIAGRAM Figure 1 RF S AW 866.05MHz 61 56 55 51 1 S yn the s ize r P RGCLK Contro l 2 P RGD 3 1 1 1 1 47 46 CONTROL DECODER 2nd Mixe r 15 IQ Modu lator I IQ Inp ut Da ta Tx Mixe r ÷2 44 43 41 40 Q 15 Tra ns mit VCO 300.8MHz CHARGE P UMP CHARGE P UMP 34 CHARGE P UMP 33 16 Re ce ive VCO 152.1MHz FM Modulator Cha nne l VCO 71 6.45 MHz NSAWO NIF2O IF2O 1.7MHz LC IF2I NIF2I 2nd IF Amplifier 37 P HASE DETECTOR 35 RS S I VCOI NVCOI FLTRI VCO TANK P LL FILTER DATA S LICER STB439 5 VCO TANK P LL FILTER 27 28 31 Da ta Out 29 DISCI 20 30 DISCO 19 BRF2 18 BRF1 21 BRF3 25 FSH 24 SLTC FLTRO 14 PHASE DETE CTOR DO PLL FILTER NVCOO FLTRS VCO TANK P HASE DETE CTOR VCOS VCOO 12 NVCOS S YNCLK 14.4MHz Rx DIVIDER REFERENCE DIVIDERS Tx DIVIDER SAWO DEMOD. TANK 4395-03.EPS NP RGEN P A/LNA CONTROL SYNTHESIZER 4 150.4MHz 50 1s t Mixe r LNA PA NTXEN SAWI NRF RF 60 NSAWI IF S AW TXFLT NTXFLT LC 50kHz Bit Ra te Filter 7/16 STB4395 3 - FUNCTIONAL DESCRIPTION Figure 1 is a simplified block diagram of the circuit. It shows the key on-chip and off-chip functional blocks and signal paths. For illustration purposes frequencies have been added representing the situation when receiving or transmitting a particular CT2 channel. 3.1 - Receiver The receive signal enters the STB4395 via an input SAW filter (866 MHZ for CT2 in Europe). The RF filter changes the input signal from a single ended to a balanced signal, after which the signal passes through the LNA, first mixer, and mixer buffer. The mixer is driven by the channel VCO, which is in turn controlled by the synthesizer. The signal path continues via the first IF SAW (150.4MHz), IF amplifier to the second mixer. The second mixer stage mixes down to 1.7MHz, and via an external LC IF filter, is passed to the second IF amplifier, where the main system gain takes place. The RSSI output is available from this point.The signal is then demodulated and sliced into a data stream which is the binary digital output available to the base band chip. The channel selection is provided by the two external filters: the first IF SAW and a second IF 2-pole LC filter. 3.2 - Transmitter The chip accepts 72Kbits/s data in an I/Q format. The I/Q inputs pass via the I/Q modulator to the TX mixer. The TX mixer is driven by the same channel VCO as the receive first mixer. The on-off ramp of the transmit PA.is controlled via an external capacitor to give minimum spurious responses when switching on and off. The PA output power can be switched from full power to -3dBm by the channel select control signal (bit LO of the 16bits serial word PRGD, see table, paragraph 1.4). 3.3 - Channel Select Control Logic All channel phase locked loops and oscillators are included on chip. The channel control synthesizer is controlled externally via a 3 wire interface. The Reference clock input of 14.4 MHz is divided using preset counters to set the phase detector /charge pump loops for the synthesizer/channel select VCO, the second receiver VCO, and the I/Q transmit VCO. The phase detector inputs for the fixed frequency VCO’s arevia pre set dividers also. The channel select control and Transmit PA control is via a 16 bit serial word, which is generated by the system controller. 15 bits of this serial word are used for the channel information, and 1 bit is used to setthe output power of the transmit PA. Theword length is sufficient to give full channel coverage over the range from 800 to 1000MHz with integer multiples of 50KHz. The section ”system clock input” gives a detailed description. Not shown in the diagram are the voltage regulators for the receive LNA/first mixer, Transmit PA, TX mixer and the remainder of the circuit.There are 6 internal voltage regulators to ensure the minimum of mutual interference. 4 - ABSOLUTE MAXIMUM RATINGS Symbol Value Unit Power Supply Voltage 7.0 V VP - VIN Voltages on Input (except SYNCLK) 5.9 V VP - VIN Voltage on Input (SYNCLK) 3.0 V VP-VN Parameter VIN - VN Voltages on Input 7.0 V VP- VOUT Voltages on Output 7.0 V VN - VOUT Voltages on Output 7.0 V VPP 8/16 VRFO Voltage Out of RF or NRF in TX 3.5 Tstg Storage Temperature 125 o C Toper Operating Temperature 40 o C STB4395 5 - POWER SUPPLIES 5.1 - Supplies The chip operates from a power supply of 3.0 to 5.5 Volts. All interface circuits to the baseband chips are operated between these supplies. Six on-chip regulators are included on-chip which provide to all parts of the circuit separate regulated voltage supplies of -2.85 ±0.15 Volts relative to the top rail for the RF circuitry, the IF circuitry, the digital circuitry and for the three VCO’s. The chip can be operated in 3 modes, power down, receive and transmit. Power down is activated taking the Pin EN to VN . To transfer to the receive mode, NTXEN is taken to VP. The built-in regulators can be by-passed ,if so required. 5.2 - Ground Plane Connections The chip has been designed to be decoupled to the positive supply, VP , at many points. Therefore it is strongly recommended that the chip be mounted on a board with a ground plane connected to VP. Because the base band chip is specified relative to a negative ground, it is further recommended that the board used is a 4 layer board with both a positive, VP , and negative ground plane VN . This has the additional advantage of providing good high frequency decoupling between supplies. The question as to whether to call VP or VN ground depends on which external equipment is connected. For testing the baseband section, this is VN ; for testing the radio chip, this is VP. In a product, this will depend on the application. For clarity all voltages specified in this document will be specified with respect to the supply, VP or VN , that the voltage normally tracks with when the supply is varied. 6 - ELECTRICAL CHARACTERISTICS Symbol VN VREG IRX ITX IQ Parameter Power Supply Voltage (unregulated) Power Supply bypassing Internal Regulators (this is also interface supply) Receive Mode Transmit Mode Standby/Power Down Min. -3 -2.7 Typ. 32 68 Max. -5.5 -3 40 80 20 Unit V V mA mA µA 7 - TIMING INFORMATION 7.1 - Turn on-off Times Times are relative to the NTXEN transition (high to low for receive to transmit and low to high for transmit to receive). Symbol tON tRAMPON tTXRX Parameter Turn-on Time From standby to receive PA Power Ramp up to reach -3dB of final power Switchover Time Transmit to Receive (LNA/first mixer active) Min. Typ. Max. 10 27.78 27.78 Unit µs µs µs 7.2 - Channel Select Timing PRGCLK must be high before NPRGEN goes low to programme the synthesizer. Figure 2 : Timing of Serial Programming Data Orde r of NPRGEN &PRGD unimportant NPRGEN PRGCLK 4395-04.EPS PRGD PROGRAM CODE Code changes on Rising Edge ofNPRGEN Note that although a new program code is implemented on the rising edge of the NPRGEN, the transmitted power level is delayed until at the start of the next burst of transmission. In order to change transmit power during a conversation, the required power code must be serially loaded with the power change instruction. 9/16 STB4395 8 - TRANSCEIVER SECTION Symbol fOP Description Min. Frequency Range Typ. 800 Channel Frequency Accuracy -1 0 Modulation Deviation (synchronised with72 Kbits/s data rate) POUTTX Max. Unit 1000 MHz 1 kHz 18 Output Power (300Ω balanced) high power mode 13 Sensitivity (source 300Ω balanced) for 1E-3 BER -103 kHz dBm -105 Signal max. for 1E-3 BER dBm 0 dBm Max. Unit 8.1 - Receiver-Input Specification LNA, first mixer and buffer Symbol Parameter Min. Typ. Conversion voltage gain 33.7 ± 1.5 dB Available conversion power gain 21.5 ± 1.5 dB Input impedance 300Ω // 3pF - Output impedance 5kΩ // 3pF - Source impedance 300Ω // -3pF - Load impedance 5kΩ // -3pF - 3.5 dB Noise figure 1dB compression point (input) -24 dBm Third order intercept (input) -14 dBm First IF amplifier, second mixer and buffer Symbol Parameter Min. Conversion Voltage Gain Available Conversion Power Gain Typ. Max. Units 22.0 ± 1.5 dB 16.3 ± 1.5 dB Input Impedance 700Ω // 2pF - Output Impedance 2kΩ // 2pF - Source Impedance 700Ω // -2pF - Load Impedance 2.8kΩ // -2pF - 6 dB 1dB Compression Point (input) -32 dBm Third Order Intercept (input) -22 dBm Noise Figure Second IF amplifier Symbol Parameter Typ. Max. Unit Conversion Voltage Gain 82 ± 3 Available Power Gain (to DISCO) 86 ± 3 dB 3 MHz Input Impedance 10kΩ // pF - Output Impedance (to DISCO) 1.1kΩ // 2F - 2.2kΩ // -2pF - Bandwith (3dB) Source Impedance Load Impedance (at DISCO) Noise Figure 1dB Compression Point (input) 10/16 Min. dB see App. Diag. 6 dB -108 dBm STB4395 8 - TRANSCEIVER SECTION (continued) Dataslicer time constants Symbol Parameter Min. Typ. Max. Unit Slow 3* Fast 130* µs 1 mV/ms Hold Drift Rate 60mV < signal < 100mV ms For 33nF capacitor at SLTC 8.2 - Transmitter-Output Specification Symbol POUT Parameter Min. Typ. Max. Unit Output Power into 300Ω balanced, high power mode 13 dBm LO Rejection 25 dBC Output Control Switch 14 dB TXFLT/NTXFLT output Symbol Parameter Min. Typ. Output Impedance Max. 2 Units kΩ Load Impedance (external) 1.2 kΩ Voltage Out (channel frequency, application circuit of this D/S) 200 mVPP Voltage Out (channel frequency-300.8MHz, app. cct of this D/S) 80 mVPP 8.3 - Synthesizer/Modulator/Channel Select Loop 8.3.1 - Synthesizer Phase Noise and Spurious Phase noise and spurious are measured at the RF outputs RF / NRF in transmit mode, no RF SAW filter. Phase Noise (Average) Offset Frequency from carrier Min. Typ. Max. Unit ±100kHz -106 dBc/Hz ±500kHz -121 dBc/Hz ±1MHz -127 dBc/Hz ±10MHz -145 dBc/Hz Spurious Offset Frequency from carrier Min. Typ. Max. Unit ±50kHz -55 dBc ±100kHz -63 dBc ±200kHz -70 dBc ±200kHz to ±10MHz -75 dBc ±10MHz to ±100MHz -40 dBc 8.3.2 - Channel Select Loop Symbol Parameter Frequency Frequency Steps Min. Typ. Max. Unit channel - 150.4 MHz 50 kHz 11/16 STB4395 8 - TRANSCEIVER SECTION (continued) 8.3.3 - Channel Frequency Setting 8.3.3.1 - General Case Using, from the divider ratios : and from the mixers : FCH = CH*FX/288 FIF2= FRX - FIF1 FRX = RX *FX/16 FIF1= FRF - FCH FIFT X = 0.5 *FTX FRF = FCH+FIFTX FTX = TX*FSYN/18 the RF frequency is related to the other frequencies by : = CH * FSYN/288 + TX * FSYN/18 * 0.5 FRF = FCH + FIFTX = FCH + FRX - FIF2 = CH * FSYN/288 + RX * FSYN/16 - FIF2 Hence the channel select input (15 of the 16 digits, see pin table, paragraph 1.4) serial data stream : CH = (FRF - TX*FSYN/18*0.5 ) * 288/FSYN = 288* F RF /FSYN - 3008 and CH = 288 (FRF + FIF2)/FSYN - 3042 where : FCH is the channel PLL synthesizer frequency FIF1 is the first if frequency (receive) FIF2 is the second if frequency (receive) FIFT X is the transmit if frequency FRF is the desired rf frequency FRX is the receive offset PLL frequency FSYN is the reference input frequency (on SYNCLK) FTX is the transmit offset PLL frequency RX is the fixed receive divide ratio of 169 TX is the fixed transmit divide ratio of 376 CH is the channel synthesizer divide ratio defined by the binary channel number, e.g. D14,D13,...........D0 The channel synthesizer provides integral division for all numbers between 3968 and 32764 (binary 000111110000000 to 111111111111100).Binary numbers outside this range will cause division ratios not directly related to binary code. 8.3.3.2 - Particular Case. with FSYN = 14.4MHz : FRX = 152.1MHz FTX = 300.8MHz FIFT X = 150.4MHz FIF1 = 150.4MHz FIF2 = 1.7MHz Then CH = 20 * FRF - 3008 Example : desired RF frequency, FRF = 866.05MHz Then substituting in : CH = 20*866.05-3008 = 14313 (binary 011011111101001) 12/16 STB4395 8 - TRANSCEIVER SECTION (continued) 8.4 - System Clock Input Symbol fREF (*1) Description Min. Typ. Reference Frequency Max. 14.4 VS Input Voltage Swing, AC Coupled, referenced to VP 0.4 IIH Input Current-High (with respect to VN) -40 IIL Input Current-low (with respect to VN) Unit MHz 0.8 V µA 40 µA Max. Unit (*1) limits according to ETSI specification 8.5 - RF/NRF Receive/Transmit Pins Symbol ZIN VSWR Description Min. Input Impedance (balanced, RX) Typ. 300Ω // 3.5pF 1.5:1 - VIN DC Max. DC Input Voltage 0 V PIN AC Max. AC Input Power 0 dBm ZOUT VSWR - Output Impedance (balanced, TX) 300Ω // 3pF - 8.6 - Digital Input Buffers NTXEN, PRGD, NPRGEN, PRGCLK, FN Symbol Description Min. Typ. Max. Unit VIH Upper Level Input Voltage VP -1 VP +0.4 V VIL Lower Level Input Voltage VN -0.4 VN + 1 V IIH Input Current High IIL Input Current Low Tt Input Edge Transition µA -10 0.1 40 µA 1 µs/V Max. Unit 8.7 - Digital Output Buffers xLOCK, DO Symbol Description Min. Typ. VOH Upper Level Output Voltage VP -0.3 VP V VOL Lower Level Output Voltage VN VN + 1 V tR Rise Time (load of 5pF) 0.3 µs/V tF Fall Time (load of 5pF) 0.4 µs/V 8.8 - Receiver - FSH Tri State Input Symbol Description Min. Typ. Max. Units VIH Upper Level Input Voltage VP -0.3 VP +0.4 V VIL Lower Level Input Voltage VN-0.4 VN + 1 V ITR Tri State Current -10 10 µA IIH Input Current High -100 IIL Input Current Low Tt Input Edge Transition 0.1 µA 100 µA 1 µs/V 13/16 STB4395 8 - TRANSCEIVER SECTION (continued) 8.9 - Receiver-RSSI Output The receiver output swings between VP and VN.The buffer output supplies a current to an on-chip resistor connected to VN . The output has to be smoothed externally with a capacitor to VN. Symbol Description PMIN Min RF Input Power Registered PMAX Max RF Input Power Registered R OUT Output Resistance (internally connected to VN) VMIN Voltage for PMIN VMAX Voltage for PMAX CF conversion factor Min. Typ. Max. Unit -90 dBm -44 dBm 50 kΩ VN+1.25 VN VN+2 V VN+0.25 V -200 mV/decade 8.10 - Power Down Buffer, EN Symbol Max. Unit VIH Upper Level Input Voltage Description VP -0.3 Min. Typ. VP +0.4 V VIL Lower Level Input Voltage VN -0.4 VN +0.3 IIH Input Current High IIL Input Current Low 10 µA tON Buffer Delay to LOCK HI (1) 10 ms tOFF Buffer Delay to min Supply Current (1) 10 ms V µA -350 (1) assumes application circuit with 100nF on each regulator. 8.11 - Transmitter-Data Inputs 8.11.1 - I,Q,REFIQ (STB4395A) Symbol Description Min. Typ. Max. Units REXT External Input Resistance 6.5 6.8 7 kΩ R INT Internal Input Resistance 32 40 50 kΩ R IM RINT Matching Error 1 % VDC DC Bias to REXT 0.96VHS VDC match VDC Matching Error to REXT VS Peak Voltage Swing to REXT VS match V 5 mV V 0.45 0.5 0.56 0.5 dB 88.5 90 91.5 degrees Min. Typ. Max. Unit VS Matching Error to REXT Phase(I-Q) 1.04VHS VHS = (VP + VN)/2 8.11.2 - I,Q,NI,NQ (STB4395) VHS = (VP+VN)/2 - VHR = (VP+VRD)/2 Symbol Description REXT External Input Resistance R INT Internal Input Resistance R IM RINT Matching Error VDC DC bias to REXT VDC match VDC Matching Error to REXT VS Peak Voltage Swing to REXT VS match 32 40 VHS-0.7 0.7 0.75 VS Matching Error to REXT Phase (I/Ibar and Q/Qbar) Phase I to Ibar or Q to Qbar 14/16 2 88.5 90 0 kΩ 50 kΩ 1 % VHR+0.7 V 12 mV 0.85 V 20 mV 91.5 degrees degrees STB4395 9 - APPLICATIONS 9.1 - Typical DC connection schemes 9.1.1 - Internal Regulator The STB4395 has built-in internal regulators which allows 15mA to be used for external circuitry. The output of this regulator is -2.85V with respect to the positive supply rail. configurations : - The STB4395operatesfrom positive ground. The decoupling of the supply lines should take into account that the a.c. ground connections will be reversed with respect to the baseband circuit and/or the microcontroller. The use of multilayer PCB is recommended. - The filters have been adapted for the best performance of the IC, although standard configurations are also considered. 9.1.2 - External Regulator The STB4395 will always generate its own supply voltage(-2.85V with respect to VP), but the I/O interfaces allow the STB4395 to swing its output levels to the supply rails (VP to VN ). The system and baseband controller can therefore be connected from the same -unregulated- supply and be individually regulated, if required . 9.2.2 - Fully Configured Applications Example Figure 3 is a typical application circuit for a complete system. It shows the typical external components to the circuit. As the reactance of the components is critical in many locations, the use of surface mounted componentsis essential. Atypical component list is also attached. It also shows the typical values for the the various VCO circuits.The values are very dependenton layout. 9.2 - Application Circuits 9.2.1 - Introduction The STB4395 makes use of some unusual circuit Figure 3 5 0Ω SAW 8 66MHz L14 7 50 nH 3 00Ω R23 L7 10 nH C24 0pF VP C3 10µF C6 1 00 nF C9 100 nF NVBAT VRD C22 10 0n F VN L1 330 µH C26 56 0pF L5 8. 2nH L8 8nH L10 8n H L11 10n H R21 0 -10kΩ 20Ω 700 Ω and 2pF R15 2kΩ 700 Ω and 2pF L16 2 70 nH R18 5Ω SAW 15 0.4 MHz L15 2 70 nH C29 1 00 nF R16 4 .7kΩ L13 7 50 nH VN VN VN C1 56 pF NPRGE N C4 5 6pF C7 56p F L4 56µH C10 56 pF PRGCLK 64 63 62 61 60 59 58 57 56 55 54 53 VN 52 51 50 L21 3 90 nH 49 1 48 2 47 3 46 4 45 5 44 6 43 VN L19 12 00n H R1 2kΩ PRGD C43 1n F R2 2kΩ NTXEN L20 3 90 nH R4 2 kΩ LOCK R7 2 kΩ R6 0Ω R5 0Ω 7 R3 0Ω 42 STB4395A R9 6.8 kΩ C8 0pF C12 30 0p F C13 30 0p F C14 30 0p F 41 TQFP 64 (from above) 9 C41 2-50 pF 40 C33 1kΩ FN 10 39 10n F EN 11 38 10n F 12 37 13 36 C11 C18 20 0nF SYNCLK R8 51Ω R12 50Ω L2 1 5n H RSSI R26 10 kΩ L22 10µH C47 100 nF C38 L3 1 5n H 100 nF FSH C49 4 7p F 10 0nF C16 2-6p F 14 35 15 34 16 33 L17 47 nH C37 2-6p F R25 100 Ω L18 47 nH R13 5 .1kΩ C15 82n F 17 18 19 21 22 23 24 25 26 27 28 29 30 31 32 R24 5 .1kΩ C20 C19 8.2 nF 3 3n F R14 5 .1kΩ C21 4 7n F C16 , C15, C19, C21 , C23, C41, C45 provision for co nn ection to grou nd also 20 C36 5. 6nF L6 8nH C23 4.7 pF C27 0 pF C28 L9 68p F 8n H R17 2 0Ω C25 10 0nF Approx value s of b uried trac k indu ctanc es to grou nd C40 5 6nF C46 VN R19 27kΩ 1 00 nF C31 20 pF R20 27kΩ R22 1 0kΩ L12 56µH C35 1 00p F C39 2-50 pF 4395-05.EPS DO C48 4 7p F C32 C17 10n F C44 82 0pF 1kΩ 1 0n F 8 Q C5 0p F L23 10µH C45 82 0pF C34 R10 6. 8kΩ REFIQ C2 0pF C42 2 -50p F R11 6. 8kΩ I C28 6 8p F 15/16 STB4395 PACKAGE MECHANICAL DATA 64 PINS - PLASTIC QUAD FLAT PACK (THIN) D D1 A D3 A2 A1 48 33 49 32 0.10mm E E1 E3 B B Seating Plane 17 64 16 1 C PMTQFP64.EPS L L1 e K TQFP6 4 A A1 A2 B C D D1 D3 e E E1 E3 K L L1 Min. 0.05 1.35 0.18 0.12 0.40 Millimeters Typ. 1.40 0.23 0.16 12.00 10.00 7.50 0.50 12.00 10.00 7.50 0.60 1.00 Max. 1.60 0.15 1.45 0.28 0.20 Min. 0.002 0.053 0.007 0.0047 1 0o (Min.), 7o (Max.) 0.75 0.0157 Inches Typ. 0.055 0.009 0.0063 0.472 0.394 0.295 0.0197 0.472 0.394 0.295 0.0236 0.0393 Max. 0.063 0.006 0.057 0.011 0.0079 0.0295 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without noti ce. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1996 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system confo rms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 16/16 TQFP64.TBL Dimensions