54ABT273 Octal D-Type Flip-Flop General Description The ’ABT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. n n n n n n n n n n n Buffered common clock Buffered, asynchronous Master Reset See ’ABT377 for clock enable version See ’ABT373 for transparent latch version See ’ABT374 for TRI-STATE ® version Output sink capability of 48 mA, source capability of 24 mA Guaranteed latchup protection High impedance glitch free bus loading during entire power up and power down cycle Non-destructive hot insertion capability Disable time less than enable time to avoid bus contention Standard Microcircuit Drawing (SMD) 5962-9321701 Features n Eight edge-triggered D flip-flops Ordering Code Military Package Package Description Number 54ABT273J-QML J20A 20-Lead Ceramic Dual-In-Line 54ABT273W-QML W20A 20-Lead Cerpack 54ABT273E-QML E20A 20-Lead Ceramic Leadless Chip Carrier, Type C TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100205 www.national.com 54ABT273 Octal D-Type Flip-Flop July 1998 Connection Diagrams Pin Assignment for DIP and Flatpack Pin Assignment for LCC DS100205-2 DS100205-1 Pin Description Names D0–D7 Data Inputs MR Master Reset CP Clock Pulse Input Q0–Q7 Data Outputs (Active LOW) (Active Rising Edge) Truth Table H = HIGH Voltage Level steady state h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition L = LOW Voltage Level steady state I = LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition X = Immaterial N = LOW-to-HIGH clock transition Mode Select-Function Table Operating Mode Inputs Output MR CP Dn Reset (Clear) L X X L Load “1” H N h H Load “0” H N l L Qn Logic Diagram DS100205-3 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2 Absolute Maximum Ratings (Note 1) DC Latchup Source Current (Across Comm Operating Range) Over Voltage Latchup If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) −500 mA VCC + 4.5V Recommended Operating Conditions −65˚C to +150˚C −55˚C to +125˚C Free Air Ambient Temperature Military Supply Voltage Military Minimum Input Edge Rate Data Input Enable Input −55˚C to +175˚C −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA −55˚C to +125˚C +4.5V to +5.5V (∆V/∆t) 50 mV/ns 20 mV/ns Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. −0.5V to +4.75V −0.5V to VCC Note 2: Either voltage limit or current limit is sufficient to protect inputs. twice the rated IOL (mA) DC Electrical Characteristics Symbol Parameter ABT273 Min VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IIH Input HIGH Current Typ Units 2.0 54ABT 2.5 54ABT 2.0 54ABT VCC V Recognized HIGH Signal 0.8 V −1.2 V Min Recognized LOW Signal IIN = −18 mA V Min 0.55 V Min 5 µA Max 7 µA Max −5 µA Max 5 IBVI Input HIGH Current Conditions Max IOH = −3 mA IOH = −24 mA IOL = 48 mA VIN = 2.7V (Note 4) VIN = VCC VIN = 7.0V Breakdown Test IIL Input LOW Current −5 VID Input Leakage Test 4.75 IOS Output Short-Circuit Current −100 ICEX ICCH VIN = 0.5V (Note 4) VIN = 0.0V IID = 1.9 µA V 0.0 −275 mA Max All Other Pins Grounded VOUT = 0.0V Output High Leakage Current 50 µA Max VOUT = VCC Power Supply Current 50 µA Max All Outputs HIGH ICCL Power Supply Current 30 mA Max ICCT Maximum ICC/Input 1.5 mA Max All Outputs LOW VI = VCC − 2.1V Data Input VI = VCC − 2.1V 0.3 mA/ Max Outputs Enabled All Others at VCC or GND ICCD Dynamic ICC No Load MHz Outputs Open (Note 3) One Bit Toggling, 50% Duty Cycle Note 3: For 8 bits toggling, ICCD < 0.5 mA/MHz. Note 4: Guaranteed but not tested. 3 www.national.com AC Electrical Characteristics Symbol Parameter 54ABT TA = −55˚C to +125˚C VCC = 4.5V to 5.5V Units CL = 50 pF Min fmax Max Clock Max 150 MHz Frequency tPLH Propagation Delay 1.0 7.0 tPHL CP to On 1.0 7.5 tPHL Propagation Delay 1.0 8.2 ns ns MR to On AC Operating Requirements Symbol 54ABT TA = −55˚C to +125˚C VCC = 4.5V to 5.5V Parameter Units CL = 50 pF Min Max ts(H) Setup Time, HIGH 2.0 ts(L) or LOW Dn to CP 2.5 th(H) Hold Time, HIGH 1.4 th(L) or LOW Dn to CP 1.4 tw(H) Pulse Width, CP, 3.3 tw(L) HIGH or LOW 3.3 tw(L) Master Reset Pulse 3.3 ns 2.0 ns ns ns ns Width, LOW tREC Recovery Time MR to CP Capacitance Symbol Parameter Typ Units CIN Input Capacitance 5 pF COUT (Note 5) Output Capacitance 9 pF Note 5: COUT is measured at frequency f = 1 MHz, per MIL-STD-833B, Method 3012. www.national.com 4 Conditions TA = 25˚C VCC = 0V VCC = 5.0V AC Loading DS100205-4 DS100205-6 *Includes jig and probe capacitance FIGURE 3. VM = 1.5V Input Pulse Requirements FIGURE 1. Standard AC Test Load Amplitude Rep. Rate tw tr tf 3.0V 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 4. Test Input Signal Requirements DS100205-5 FIGURE 2. Propagation Delay, Pulse Width Waveforms DS100205-8 FIGURE 5. Propagation Delay Waveforms for Inverting and Non-Inverting Functions DS100205-9 FIGURE 6. Setup Time, Hold Time and Recovery Time Waveforms 5 www.national.com 6 Physical Dimensions inches (millimeters) unless otherwise noted 20-Terminal Ceramic Chip Carrier (L) NS Package Number E20A 20-Lead Ceramic Dual-In-Line (D) NS Package Number J20A 7 www.national.com 54ABT273 Octal D-Type Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Ceramic Flatpak (F) NS Package Number W20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: [email protected] National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.