INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT7080 16-bit even/odd parity generator/checker Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification 16-bit even/odd parity generator/checker 74HC/HCT7080 The 74HC/HCT7080 are 16-bit parity generators or checkers commonly used to detect errors in high-speed data transmission or data retrieval systems. FEATURES • Word-length easily expanded by cascading • Generates either even or odd parity for 16-data bits The even and odd parity output is available for generating or checking even/odd parity up to 16-bits. • Output capability: standard • ICC category: MSI GENERAL DESCRIPTION The even/odd parity output (E/O) is HIGH when an even number of data inputs (I0 to I15) are HIGH and the cascade/even-odd-changing input (X) is HIGH. The 74HC/HCT7080 are high-speed Si-gate CMOS devices. They are specified in compliance with JEDEC standard no. 7A. Expansion to larger word sizes is accomplished by connecting the even/odd parity output (E/O) to the cascade/even-odd-changing input (X) of the final stage. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH PARAMETER CONDITIONS HCT In to E/O 29 32 ns X to E/O 12 15 ns 3.5 3.5 pF 24 25 pF propagation delay CI input capacitance CPD power dissipation capacitance per package CL = 15 pF; VCC = 5 V notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL ×VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. December 1990 UNIT HC 2 Philips Semiconductors Product specification 16-bit even/odd parity generator/checker 74HC/HCT7080 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1 X cascade/even-odd-changing input 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18 I0 to I15 data inputs 10 GND ground (0 V) 19 E/O even/odd parity output 20 VCC positive supply voltage Fig.1 Pin configuration. December 1990 Fig.2 Logic symbol. 3 Fig.3 IEC logic symbol. Philips Semiconductors Product specification 16-bit even/odd parity generator/checker 74HC/HCT7080 Fig.4 Functional diagram. FUNCTION TABLE INPUTS OUTPUTS In X E/O ∑=E H L H L ∑≠E H L L H Fig.5 Logic diagram. Notes 1. H = HIGH voltage level L = LOW voltage level E = even December 1990 4 Philips Semiconductors Product specification 16-bit even/odd parity generator/checker 74HC/HCT7080 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER min. +25 −40 to +85 −40 to +125 typ. max. min. max. min. max. UNIT V CC WAVEFORMS (V) tPHL/ tPLH propagation delay In to E/O 91 33 26 280 56 48 350 70 60 420 84 71 ns 2.0 4.5 6.0 Fig.7 tPHL/ tPLH propagation delay X to E/O 41 15 12 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 Fig.6 tTHL/ tTLH output transition time 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 Figs 6 and 7 December 1990 5 Philips Semiconductors Product specification 16-bit even/odd parity generator/checker 74HC/HCT7080 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT In X 1.0 1.0 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 −40 to +85 min. typ. max. min. −40 to +125 UNIT V CC WAVEFORMS (V) max. min. max. tPHL/ tPLH propagation delay In to E/O 37 63 79 95 ns 4.5 Fig.7 tPHL/ tPLH propagation delay X to E/O 18 32 40 48 ns 4.5 Fig.6 tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Figs 6 and 7 December 1990 6 Philips Semiconductors Product specification 16-bit even/odd parity generator/checker 74HC/HCT7080 AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the cascade/even-odd-changing input (X) to the even/odd parity output (E/O) propagation delays and the output transition times. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the data inputs (In) to the even/odd parity output (E/O) propagation delays and the output transition times. December 1990 7 Philips Semiconductors Product specification 16-bit even/odd parity generator/checker TEST CIRCUIT AND WAVEFORMS CL = load capacitance including jig and probe capacitance (see AC CHARACTERISTICS for values). RT = termination resistance should be equal to the output impedance ZO of the pulse generator. tr; tf FAMILY AMPLITUDE VM 74HC VCC 50% < 2 ns 6 ns 74HCT 3.0 V 1.3 V < 2 ns 6 ns fmax; PULSE WIDTH OTHER Fig.8 Test circuit for measuring AC performance. CL = load capacitance including jig and probe capacitance (see AC CHARACTERISTICS for values). RT = termination resistance should be equal to the output impedance ZO of the pulse generator. tr; tf FAMILY AMPLITUDE VM 74HC VCC 50% < 2 ns 6 ns 74HCT 3.0 V 1.3 V < 2 ns 6 ns fmax; PULSE WIDTH OTHER Fig.9 Input pulse definitions. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. December 1990 8 74HC/HCT7080