INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT640 Octal bus transceiver; 3-state; inverting Product specification File under Integrated Circuits, IC06 March 1988 Philips Semiconductors Product specification Octal bus transceiver; 3-state; inverting 74HC/HCT640 FEATURES GENERAL DESCRIPTION • Octal bidirectional bus interface The 74HC/HCT640 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. • Inverting 3-state outputs • Output capability: bus driver • ICC category: MSI The 74HC/HCT640 are octal transceivers featuring inverting 3-state bus compatible outputs in both send and receive directions. The “640” features an output enable (OE) input for easy cascading and a send/receive (DIR) for direction control. OE controls the outputs so that the buses are effectively isolated. The “640” is similar to the “245” but has inverting outputs. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC tPHL/ tPLH propagation delay An to Bn; Bn to An CI CI/O CPD power dissipation capacitance per transceiver CL = 15 pF; VCC = 5 V 9 9 ns input capacitance 3.5 3.5 pF input/output capacitance 10 10 pF 35 35 pF notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. March 1988 HCT 2 Philips Semiconductors Product specification Octal bus transceiver; 3-state; inverting 74HC/HCT640 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1 DIR direction control 2, 3, 4, 5, 6, 7, 8, 9 A0 to A7 data inputs/outputs 10 GND ground (0 V) 18, 17, 16, 15, 14, 13, 12, 11 B0 to B7 data inputs/outputs 19 OE output enable input (active LOW) 20 VCC positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. FUNCTION TABLE inputs OE DIR L L H L H X inputs/outputs An Bn A=B inputs Z inputs B=A Z Note 1. H L X Z = HIGH voltage level = LOW voltage level = don’t care = high impedance OFF-state Fig.3 IEC logic symbol. March 1988 Fig.4 Functional diagram. 3 Philips Semiconductors Product specification Octal bus transceiver; 3-state; inverting 74HC/HCT640 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: bus driver ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER −40 to +85 +25 −40 to +125 min. typ. max. min. max. min. UNIT V CC WAVEFORMS (V) max. tPHL/ tPLH propagation delay An to Bn; Bn to An 30 11 9 90 18 15 115 23 20 135 27 23 ns 2.0 4.5 6.0 Fig.5 tPZH/ tPZL 3-state output enable time OE, DIR to An; OE, DIR to Bn 44 16 13 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 Fig.6 tPHZ/ tPLZ 3-state output disable time OE, DIR to An; OE, DIR to Bn 50 18 14 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 Fig.6 tTHL/ tTLH output transition time 14 5 4 60 12 10 75 15 13 90 18 15 ns 2.0 4.5 6.0 Fig.5 March 1988 4 Philips Semiconductors Product specification Octal bus transceiver; 3-state; inverting 74HC/HCT640 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: bus driver ICC category: MSI Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT An Bn OE DIR 1.50 1.50 1.50 0.90 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER −40 to +85 +25 −40 to +125 min. typ. max. min. max. min. UNIT V CC WAVEFORMS (V) max. tPHL/ tPLH propagation delay An to Bn; Bn to An 11 22 28 33 ns 4.5 Fig.5 tPZH/ tPZL 3-state output enable time OE, DIR to An; OE, DIR to Bn 18 30 38 45 ns 4.5 Fig.6 tPHZ/ tPLZ 3-state output disable time OE, DIR to An; OE, DIR to Bn 19 30 38 45 ns 4.5 Fig.6 tTHL/ tTLH output transition time 5 12 15 18 ns 4.5 Fig.5 March 1988 5 Philips Semiconductors Product specification Octal bus transceiver; 3-state; inverting 74HC/HCT640 AC WAVEFORMS (1) (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.5 HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the input (An, Bn) to output (Bn, An) propagation delays and the output transition times. Waveforms showing the 3-state enable and disable times. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. March 1988 6