PHILIPS 74LVC1G99DP

74LVC1G99
Ultra-configurable multiple function gate; 3-state
Rev. 01 — 3 January 2008
Product data sheet
1. General description
The 74LVC1G99 provides a low voltage, ultra-configurable, multiple function gate with
3-state output. The device can be configured as one of several logic functions including,
AND, OR, NAND, NOR, XOR, XNOR, inverter, buffer and MUX. No external components
are required to configure the device as all inputs can be connected directly to VCC or GND.
The 3-state output is controlled by the output enable input (OE). A HIGH level at OE
causes the output (Y) to assume a high-impedance OFF-state. When OE is LOW, the
output state is determined by the signals applied to the Schmitt-trigger inputs (A, B, C and
D).
Due to the use of Schmitt-trigger inputs the device is tolerant of slowly changing input
signals, transforming them into sharply defined, jitter free output signals. By eliminating
leakage current paths to VCC and GND, the inputs and disabled output are also
over-voltage tolerant, making the device suitable for mixed-voltage applications.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74LVC1G99 is fully specified over the supply range from 1.65 V to 5.5 V.
2. Features
n
n
n
n
n
n
n
n
n
n
n
n
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant inputs for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
u JESD8-7 (1.65 V to 1.95 V)
u JESD8-5 (2.3 V to 2.7 V)
u JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
u HBM JESD22-A114E exceeds 2000 V
u MM JESD22-A115-A exceeds 200 V
±24 mA output drive (VCC = 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from −40 °C to +85 °C and −40 °C to +125 °C.
74LVC1G99
NXP Semiconductors
Ultra-configurable multiple function gate; 3-state
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVC1G99DP
−40 °C to +125 °C
TSSOP8
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
SOT505-2
74LVC1G99GT
−40 °C to +125 °C
XSON8
plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1 × 1.95 × 0.5 mm
74LVC1G99GM
−40 °C to +125 °C
XQFN8U
plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6 × 1.6 × 0.5 mm
SOT902-1
4. Marking
Table 2.
Marking
Type number
Marking code
74LVC1G99DP
V99
74LVC1G99GT
V99
74LVC1G99GM
V99
5. Functional diagram
OE
A
B
Y
C
D
001aah322
Fig 1. Logic symbol
74LVC1G99_1
Product data sheet
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Rev. 01 — 3 January 2008
2 of 26
74LVC1G99
NXP Semiconductors
Ultra-configurable multiple function gate; 3-state
6. Pinning information
6.1 Pinning
74LVC1G99
OE
1
8
VCC
A
2
7
Y
B
3
6
D
GND
4
5
C
001aah323
Fig 2. Pin configuration SOT505-2 (TSSOP8)
74LVC1G99
1
8
VCC
A
2
7
Y
B
3
6
D
Y
1
D
C
7
OE
2
6
A
3
5
B
4
OE
8
74LVC1G99
VCC
terminal 1
index area
4
5
C
GND
GND
001aah324
001aah325
Transparent top view
Transparent top view
Fig 3. Pin configuration SOT833-1 (XSON8)
Fig 4. Pin configuration SOT902-1 (XQFN8U)
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
Description
SOT505-2 and
SOT833-1
SOT902-1
OE
1
7
output enable input OE (active LOW)
A
2
6
data input
B
3
5
data input
GND
4
4
ground (0 V)
C
5
3
data input
D
6
2
data input
Y
7
1
data output
VCC
8
8
supply voltage
74LVC1G99_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 3 January 2008
3 of 26
74LVC1G99
NXP Semiconductors
Ultra-configurable multiple function gate; 3-state
7. Functional description
Table 4.
Function table [1]
Input
Output
OE
D
C
B
A
Y
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
H
L
L
L
L
L
H
H
H
L
L
H
L
L
L
L
L
H
L
H
L
L
L
H
H
L
H
L
L
H
H
H
H
L
H
L
L
L
H
L
H
L
L
H
L
L
H
L
H
L
H
L
H
L
H
H
L
L
H
H
L
L
H
L
H
H
L
H
H
L
H
H
H
L
L
L
H
H
H
H
L
H
X
X
X
X
Z
[1]
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state.
74LVC1G99_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 3 January 2008
4 of 26
74LVC1G99
NXP Semiconductors
Ultra-configurable multiple function gate; 3-state
7.1 Logic configurations
Table 5.
Function selection table
Primary function
Complementary function
3-state buffer
3-state inverter
3-state 2-input multiplexer
3-state 2-input multiplexer with inverting output
3-state 2-input AND
3-state 2-input NOR with two inverting inputs
3-state 2-input AND with one inverting input
3-state 2-input NOR with one inverting input
3-state 2-input AND with two inverting inputs
3-state 2-input NOR
3-state 2-input NAND
3-state 2-input OR with two inverting inputs
3-state 2-input NAND with one inverting input
3-state 2-input OR with one inverting input
3-state 2-input NAND with two inverting inputs
3-state 2-input OR
3-state 2-input XOR
3-state 2-input XNOR
3-state 2-input XOR with one inverting input
7.2 3-state buffer functions available
Table 6.
Function table [1]
See Figure 5.
Function
3-state buffer
[1]
Input
OE
A
B
C
D
L
input
H or L
L
L
L
H or L
input
H
L
L
L
H
input
L
L
H
L
input
H
L
H
H or L
L
input
L
H or L
L
H
input
L
L
L
H or L
input
H = HIGH voltage level;
L = LOW voltage level.
OE
input
Y
001aah326
Fig 5. 3-state buffer function
74LVC1G99_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 3 January 2008
5 of 26
74LVC1G99
NXP Semiconductors
Ultra-configurable multiple function gate; 3-state
7.3 3-state inverter functions available
Table 7.
Function table [1]
See Figure 6.
Function
Input
OE
3-state inverter
[1]
A
B
C
D
L
input
H or L
L
H
L
X
input
H
H
L
L
H
input
H
L
H
L
input
L
L
H
H or L
L
input
L
H or L
H
H
input
L
H
H
H or L
input
H = HIGH voltage level;
L = LOW voltage level.
X = don’t care.
OE
input
Y
001aah327
Fig 6. 3-state inverter function
7.4 3-state multiplexer functions available
Table 8.
Function table [1]
See Figure 7.
Function
3-state 2-input
multiplexer
[1]
Input
OE
A
B
C
D
L
input 1
input 2
input 1 or input 2
L
L
input 2
input 1
input 2 or input 1
L
L
input 1
input 2
input 1 or input 2
H
L
input 2
input 1
input 2 or input 1
H
H = HIGH voltage level;
L = LOW voltage level.
OE
OE
input 1
input 1
Y
Y
input 2
input 2
A/B
A/B
001aah328
Fig 7. 3-state 2-input multiplexer function
74LVC1G99_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 3 January 2008
6 of 26
74LVC1G99
NXP Semiconductors
Ultra-configurable multiple function gate; 3-state
7.5 3-state AND/NOR functions available
Table 9.
Function table [1]
See Figure 8.
Number of inputs Function
Input
AND/NAND
OR/NOR
OE
A
B
C
D
2
3-state AND
3-state NOR
L
L
input 1
input 2
L
2
3-state AND
3-state NOR
L
L
input 2
input 1
L
[1]
H = HIGH voltage level;
L = LOW voltage level.
OE
OE
input 1
input 1
Y
Y
input 2
input 2
001aah329
Fig 8. 3-state AND/NOR function
Table 10. Function table [1]
See Figure 9.
Number of inputs Function
Input
AND/NAND
OR/NOR
OE
A
B
C
D
2
3-state AND
3-state NOR
L
input 2
L
input 1
L
2
3-state AND
3-state NOR
L
H
input 1
input 2
H
[1]
H = HIGH voltage level;
L = LOW voltage level.
OE
OE
input 1
input 1
Y
input 2
Y
input 2
001aah330
Fig 9. 3-state AND/NOR function
74LVC1G99_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 3 January 2008
7 of 26
74LVC1G99
NXP Semiconductors
Ultra-configurable multiple function gate; 3-state
Table 11. Function table [1]
See Figure 10.
Number of inputs Function
Input
AND/NAND
OR/NOR
OE
A
B
C
D
2
3-state AND
3-state NOR
L
input 1
L
input 2
L
2
3-state AND
3-state NOR
L
H
input 2
input 1
H
[1]
H = HIGH voltage level;
L = LOW voltage level.
OE
OE
input 1
input 1
Y
Y
input 2
input 2
001aah331
Fig 10. 3-state AND/NOR function
Table 12. Function table [1]
See Figure 11.
Number of inputs Function
Input
AND/NAND
OR/NOR
OE
A
B
C
D
2
3-state AND
3-state NOR
L
input 1
H
input 2
L
2
3-state AND
3-state NOR
L
input 2
H
input 1
L
[1]
H = HIGH voltage level;
L = LOW voltage level.
OE
OE
input 1
input 1
Y
input 2
Y
input 2
001aah332
Fig 11. 3-state AND/NOR function
74LVC1G99_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 3 January 2008
8 of 26
74LVC1G99
NXP Semiconductors
Ultra-configurable multiple function gate; 3-state
7.6 3-state NAND/OR functions available
Table 13. Function table [1]
See Figure 12.
Number of inputs Function
Input
AND/NAND
OR/NOR
OE
A
B
C
D
2
3-state NAND
3-state OR
L
L
input 1
input 2
H
2
3-state NAND
3-state OR
L
L
input 2
input 1
H
[1]
H = HIGH voltage level;
L = LOW voltage level.
OE
OE
input 1
input 1
Y
Y
input 2
input 2
001aah333
Fig 12. 3-state NAND/OR function
Table 14. Function table [1]
See Figure 13.
Number of inputs Function
Input
AND/NAND
OR/NOR
OE
A
B
C
D
2
3-state NAND
3-state OR
L
input 2
L
input 1
H
2
3-state NAND
3-state OR
L
H
input 1
input 2
L
[1]
H = HIGH voltage level;
L = LOW voltage level.
OE
OE
input 1
input 1
Y
input 2
Y
input 2
001aah334
Fig 13. 3-state AND/NOR function
74LVC1G99_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 3 January 2008
9 of 26
74LVC1G99
NXP Semiconductors
Ultra-configurable multiple function gate; 3-state
Table 15. Function table [1]
See Figure 14.
Number of inputs Function
Input
AND/NAND
OR/NOR
OE
A
B
C
D
2
3-state NAND
3-state OR
L
input 1
L
input 2
H
2
3-state NAND
3-state OR
L
H
input 2
input 1
L
[1]
H = HIGH voltage level;
L = LOW voltage level.
OE
OE
input 1
input 1
Y
Y
input 2
input 2
001aah335
Fig 14. 3-state AND/NOR function
Table 16. Function table [1]
See Figure 15.
Number of inputs Function
Input
AND/NAND
OR/NOR
OE
A
B
C
D
2
3-state NAND
3-state OR
L
input 1
H
input 2
L
2
3-state NAND
3-state OR
L
input 2
H
input 1
L
[1]
H = HIGH voltage level;
L = LOW voltage level.
OE
OE
input 1
input 1
Y
input 2
Y
input 2
001aah336
Fig 15. 3-state AND/NOR function
74LVC1G99_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 3 January 2008
10 of 26
74LVC1G99
NXP Semiconductors
Ultra-configurable multiple function gate; 3-state
7.7 3-state XOR/XNOR functions available
Table 17. Function table [1]
See Figure 16.
Function
Input
OE
3-state XOR
[1]
A
B
C
D
L
input 1
H or L
L
input 2
L
input 2
H or L
L
input 1
L
H or L
input 1
H
input 2
L
H or L
input 2
H
input 1
L
L
H
input 1
input 2
L
L
H
input 2
input 1
H = HIGH voltage level;
L = LOW voltage level.
OE
input 1
Y
input 2
001aah337
Fig 16. 3-state XOR function
Table 18. Function table [1]
See Figure 17.
Function
3-state XOR
[1]
Input
OE
A
B
C
D
L
H
L
input 1
input 2
H = HIGH voltage level;
L = LOW voltage level.
OE
input 1
Y
input 2
001aah338
Fig 17. 3-state XOR function
74LVC1G99_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 3 January 2008
11 of 26
74LVC1G99
NXP Semiconductors
Ultra-configurable multiple function gate; 3-state
Table 19. Function table [1]
See Figure 18.
Function
3-state XOR
[1]
Input
OE
A
B
C
D
L
H
L
input 1
input 2
H = HIGH voltage level;
L = LOW voltage level.
OE
input 1
Y
input 2
001aah339
Fig 18. 3-state XOR function
Table 20. Function table [1]
See Figure 19.
Function
3-state XNOR
[1]
Input
OE
A
B
C
D
L
H
L
input 1
input 2
L
H
L
input 2
input 1
H = HIGH voltage level;
L = LOW voltage level.
OE
input 1
Y
input 2
001aah340
Fig 19. 3-state XNOR function
74LVC1G99_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 3 January 2008
12 of 26
74LVC1G99
NXP Semiconductors
Ultra-configurable multiple function gate; 3-state
8. Limiting values
Table 21. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
output voltage
VO
IO
output current
ICC
supply current
IGND
ground current
Ptot
total power dissipation
Tstg
storage temperature
Conditions
VI < 0 V
[1]
Min
Max
Unit
−0.5
+6.5
V
−50
-
mA
−0.5
+6.5
V
-
±50
mA
Active mode
[1][2]
−0.5
VCC + 0.5
V
Power-down mode
[1][2]
−0.5
+6.5
V
-
±50
mA
-
100
mA
−100
-
mA
-
250
mW
−65
+150
°C
VO > VCC or VO < 0 V
VO = 0 V to VCC
Tamb = −40 °C to +125 °C
[3]
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3]
For TSSOP8 package: above 110 °C the value of Ptot derates linearly with 8.0 mW/K.
For XSON8 and XQFN8U packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.
9. Recommended operating conditions
Table 22.
Recommended operating conditions
Symbol
Parameter
VCC
Min
Typ
Max
Unit
supply voltage
1.65
-
5.5
V
VI
input voltage
0
-
5.5
V
VO
output voltage
Tamb
ambient temperature
∆t/∆V
input transition rise and fall rate
Conditions
Active mode
0
-
VCC
V
Power-down mode; VCC = 0 V
0
-
5.5
V
−40
-
+125
°C
VCC = 1.65 V to 2.7 V
-
-
20
ns/V
VCC = 2.7 V to 4.5 V
-
-
10
ns/V
VCC = 4.5 V to 5.5 V
-
-
5
ns/V
74LVC1G99_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 3 January 2008
13 of 26
74LVC1G99
NXP Semiconductors
Ultra-configurable multiple function gate; 3-state
10. Static characteristics
Table 23. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Min
Typ[1] Max
Unit
IO = −100 µA; VCC = 1.65 V to 5.5 V
VCC − 0.1
-
-
V
IO = −4 mA; VCC = 1.65 V
1.2
-
-
V
IO = −8 mA; VCC = 2.3 V
1.9
-
-
V
Conditions
Tamb = −40 °C to +85 °C
VOH
VOL
HIGH-level output voltage
LOW-level output voltage
VI = VIH or VIL
IO = −12 mA; VCC = 2.7 V
2.2
-
-
V
IO = −24 mA; VCC = 3.0 V
2.3
-
-
V
IO = −32 mA; VCC = 4.5 V
3.8
-
-
V
VI = VIH or VIL
IO = 100 µA; VCC = 1.65 V to 5.5 V
-
-
0.1
V
IO = 4 mA; VCC = 1.65 V
-
-
0.45
V
IO = 8 mA; VCC = 2.3 V
-
-
0.3
V
IO = 12 mA; VCC = 2.7 V
-
-
0.4
V
IO = 24 mA; VCC = 3.0 V
-
-
0.55
V
IO = 32 mA; VCC = 4.5 V
-
-
0.55
V
II
input leakage current
VCC = 0 V to 5.5 V; VI = 5.5 V or GND
-
±0.1
±5
µA
IOZ
OFF-state output current
VCC = 3.6 V; VI = VIH or VIL;
VO = 5.5 V or GND
-
±0.1
±10
µA
IOFF
power-off leakage current
VCC = 0 V; VI or VO = 5.5 V
-
±0.1
±10
µA
ICC
supply current
VCC = 1.65 V to 5.5 V;
VI = 5.5 V or GND; IO = 0 A
-
0.1
10
µA
∆ICC
additional supply current
per pin; VCC = 2.3 V to 5.5 V;
VI = VCC − 0.6 V; IO = 0 A
-
5
500
µA
CI
input capacitance
VCC = 3.3 V; VI = GND to VCC
-
2.5
-
pF
IO = −100 µA; VCC = 1.65 V to 5.5 V
VCC − 0.1
-
-
V
IO = −4 mA; VCC = 1.65 V
0.95
-
-
V
IO = −8 mA; VCC = 2.3 V
1.7
-
-
V
Tamb = −40 °C to +125 °C
VOH
VOL
HIGH-level output voltage
LOW-level output voltage
VI = VIH or VIL
IO = −12 mA; VCC = 2.7 V
1.9
-
-
V
IO = −24 mA; VCC = 3.0 V
2.0
-
-
V
IO = −32 mA; VCC = 4.5 V
3.4
-
-
V
VI = VIH or VIL
IO = 100 µA; VCC = 1.65 V to 5.5 V
-
-
0.1
V
IO = 4 mA; VCC = 1.65 V
-
-
0.70
V
IO = 8 mA; VCC = 2.3 V
-
-
0.45
V
IO = 12 mA; VCC = 2.7 V
-
-
0.60
V
IO = 24 mA; VCC = 3.0 V
-
-
0.80
V
IO = 32 mA; VCC = 4.5 V
-
-
0.80
V
74LVC1G99_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 3 January 2008
14 of 26
74LVC1G99
NXP Semiconductors
Ultra-configurable multiple function gate; 3-state
Table 23. Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ[1] Max
II
input leakage current
VCC = 0 V to 5.5 V; VI = 5.5 V or GND
-
-
±100
µA
IOZ
OFF-state output current
VCC = 3.6 V; VI = VIH or VIL;
VO = 5.5 V or GND
-
-
±200
µA
IOFF
power-off leakage current
VCC = 0 V; VI or VO = 5.5 V
-
-
±200
µA
ICC
supply current
VCC = 1.65 V to 5.5 V;
VI = 5.5 V or GND; IO = 0 A
-
-
200
µA
∆ICC
additional supply current
per pin; VCC = 2.3 V to 5.5 V;
VI = VCC − 0.6 V; IO = 0 A
-
-
5000
µA
[1]
Unit
All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
11. Dynamic characteristics
Table 24. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 22.
Symbol Parameter
tpd
25 °C
Conditions
Unit
Min
Max
Min
VCC = 1.65 V to 1.95 V
-
7.5
-
2.8
30.8
38.5
ns
VCC = 2.3 V to 2.7 V
-
5.0
-
2.0
11.7
14.6
ns
VCC = 2.7 V
-
5.4
-
2.0
9.0
11.3
ns
VCC = 3.0 V to 3.6 V
-
4.5
-
1.8
8.4
10.5
ns
-
3.8
-
1.8
5.5
6.9
ns
propagation delay A to Y; see Figure 20
B to Y; see Figure 20
Max
Max
(85 °C) (125 °C)
[2]
VCC = 4.5 V to 5.5 V
[2]
VCC = 1.65 V to 1.95 V
-
7.5
-
2.8
28.9
36.2
ns
VCC = 2.3 V to 2.7 V
-
5.0
-
2.0
11.3
14.2
ns
VCC = 2.7 V
-
5.4
-
2.0
9.0
11.3
ns
VCC = 3.0 V to 3.6 V
-
4.5
-
1.8
8.2
10.3
ns
-
3.8
-
1.8
5.4
6.8
ns
VCC = 1.65 V to 1.95 V
-
7.8
-
3.2
29.8
37.3
ns
VCC = 2.3 V to 2.7 V
-
5.2
-
2.3
12.3
15.4
ns
VCC = 2.7 V
-
5.3
-
2.3
9.6
12.0
ns
VCC = 3.0 V to 3.6 V
-
4.6
-
2.3
8.6
10.8
ns
-
3.8
-
1.8
5.7
7.2
ns
VCC = 4.5 V to 5.5 V
C to Y; see Figure 20
[2]
VCC = 4.5 V to 5.5 V
D to Y; see Figure 20
[2]
VCC = 1.65 V to 1.95 V
-
7.0
-
2.8
25.7
32.2
ns
VCC = 2.3 V to 2.7 V
-
4.6
-
2.0
10.7
13.4
ns
VCC = 2.7 V
-
4.8
-
2.0
9.2
11.5
ns
VCC = 3.0 V to 3.6 V
-
4.1
-
1.8
7.6
9.5
ns
VCC = 4.5 V to 5.5 V
-
3.4
-
1.6
5.2
6.5
ns
74LVC1G99_1
Product data sheet
−40 °C to +125 °C
Typ[1]
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 3 January 2008
15 of 26
74LVC1G99
NXP Semiconductors
Ultra-configurable multiple function gate; 3-state
Table 24. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 22.
Symbol Parameter
ten
enable time
disable time
tdis
25 °C
Conditions
Max
Min
VCC = 1.65 V to 1.95 V
-
5.7
-
2.0
25.2
32.0
ns
VCC = 2.3 V to 2.7 V
-
3.8
-
1.4
11.3
14.0
ns
VCC = 2.7 V
-
4.2
-
1.4
8.6
11.0
ns
VCC = 3.0 V to 3.6 V
-
3.5
-
1.4
7.0
9.0
ns
VCC = 4.5 V to 5.5 V
-
2.7
-
1.4
4.7
6.0
ns
-
5.7
-
3.0
15.0
19.0
ns
OE to Y; see Figure 21
OE to Y; see Figure 21
[4]
VCC = 2.3 V to 2.7 V
-
3.6
-
2.0
5.8
7.3
ns
VCC = 2.7 V
-
4.5
-
2.0
6.6
8.2
ns
VCC = 3.0 V to 3.6 V
-
4.5
-
2.1
5.9
7.4
ns
-
3.4
-
1.0
4.5
5.6
ns
-
14
-
-
-
-
pF
per buffer (output enabled);
fi = 10 MHz; CL = 50 pF;
VI = GND to VCC
[5]
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
-
16
-
-
-
-
pF
VCC = 2.7 V
-
18
-
-
-
-
pF
VCC = 3.0 V to 3.6 V
-
25
-
-
-
-
pF
VCC = 4.5 V to 5.5 V
-
30
-
-
-
-
pF
[1]
All typical values are measured at nominal VCC.
[2]
tpd is the same as tPLH and tPHL.
[3]
ten is the same as tPZH and tPZL.
[4]
tdis is the same as tPHZ and tPLZ.
[5]
CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
74LVC1G99_1
Product data sheet
Max
Max
(85 °C) (125 °C)
[3]
VCC = 4.5 V to 5.5 V
power dissipation
capacitance
Unit
Min
VCC = 1.65 V to 1.95 V
CPD
−40 °C to +125 °C
Typ[1]
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 3 January 2008
16 of 26
74LVC1G99
NXP Semiconductors
Ultra-configurable multiple function gate; 3-state
12. Waveforms
VI
VM
A, B, C, D input
VM
GND
tPHL
tPLH
VOH
VM
Y output
VM
VOL
tPLH
tPHL
VOH
VM
Y output
VM
VOL
001aah341
Measurement points are given in Table 25.
Logic levels: VOL and VOH are typical output voltage drop that occur with the output load.
Fig 20. The data input (A, B, C, D) to output (Y) propagation delays
VI
OE input
VM
GND
tPLZ
tPZL
VCC
output
LOW-to-OFF
OFF-to-LOW
VM
VX
VOL
tPHZ
tPZH
VOH
VY
output
HIGH-to-OFF
OFF-to-HIGH
VM
GND
outputs
enabled
outputs
enabled
outputs
disabled
mna644
Measurement points are given in Table 25.
Logic levels: VOL and VOH are typical output voltage drop that occur with the output load.
Fig 21. 3-state enable and disable times
Table 25.
Measurement points
Supply voltage
Input
Output
VCC
VM
VM
VX
VY
1.65 V to 1.95 V
0.5VCC
0.5VCC
VOL + 0.15 V
VOH − 0.15 V
2.3 V to 2.7 V
0.5VCC
0.5VCC
VOL + 0.15 V
VOH − 0.15 V
2.7 V
1.5 V
1.5 V
VOL + 0.3 V
VOH − 0.3 V
3.0 V to 3.6 V
1.5 V
1.5 V
VOL + 0.3 V
VOH − 0.3 V
4.5 V to 5.5 V
0.5VCC
0.5VCC
VOL + 0.3 V
VOH − 0.3 V
74LVC1G99_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 3 January 2008
17 of 26
74LVC1G99
NXP Semiconductors
Ultra-configurable multiple function gate; 3-state
VEXT
VCC
VI
RL
VO
G
DUT
RT
CL
RL
mna616
Test data is given in Table 26.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 22. Load circuitry for switching times
Table 26.
Test data
Supply voltage
Input
Load
VEXT
VI
tr = tf
CL
RL
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ
1.65 V to 1.95 V
VCC
≤ 2.0 ns
30 pF
1 kΩ
open
GND
2VCC
2.3 V to 2.7 V
VCC
≤ 2.0 ns
30 pF
500 Ω
open
GND
2VCC
2.7 V
2.7 V
≤ 2.5 ns
50 pF
500 Ω
open
GND
6V
3.0 V to 3.6 V
2.7 V
≤ 2.5 ns
50 pF
500 Ω
open
GND
6V
4.5 V to 5.5 V
VCC
≤ 2.5 ns
50 pF
500 Ω
open
GND
2VCC
13. Transfer characteristics
Table 27. Transfer characteristics
Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 22
Symbol Parameter
−40 °C to +85 °C
Conditions
Typ[1]
Min
VT+
positive-going
threshold voltage
Min
Unit
Max
see Figure 23, Figure 24,
Figure 25, Figure 26 and
Figure 27
VCC = 1.8 V
0.70
1.02
1.20
0.67
1.20
V
VCC = 2.3 V
1.11
1.42
1.60
1.08
1.60
V
VCC = 3.0 V
1.50
1.79
2.00
1.47
2.00
V
VCC = 4.5 V
2.16
2.52
2.74
2.13
2.74
V
VCC = 5.5 V
2.61
2.99
3.33
2.58
3.33
V
74LVC1G99_1
Product data sheet
Max
−40 °C to +125 °C
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 3 January 2008
18 of 26
74LVC1G99
NXP Semiconductors
Ultra-configurable multiple function gate; 3-state
Table 27. Transfer characteristics …continued
Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 22
Symbol Parameter
−40 °C to +85 °C
Conditions
Typ[1]
Min
VT−
negative-going
threshold voltage
Min
Unit
Max
see Figure 23, Figure 24,
Figure 25, Figure 26 and
Figure 27
VCC = 1.8 V
0.30
0.53
0.72
0.30
0.75
V
VCC = 2.3 V
0.58
0.77
1.00
0.58
1.03
V
VCC = 3.0 V
0.80
1.04
1.30
0.80
1.33
V
VCC = 4.5 V
1.21
1.55
1.90
1.21
1.93
V
VCC = 5.5 V
1.45
1.86
2.29
1.45
2.32
V
VCC = 1.8 V
0.30
0.48
0.62
0.23
0.62
V
VCC = 2.3 V
0.40
0.64
0.80
0.34
0.80
V
VCC = 3.0 V
0.50
0.75
1.00
0.44
1.00
V
VCC = 4.5 V
0.71
0.97
1.20
0.65
1.20
V
VCC = 5.5 V
0.71
1.13
1.40
0.65
1.40
V
hysteresis voltage (VT+ − VT−); see Figure 23,
Figure 24, Figure 25,
Figure 26 and Figure 27
VH
[1]
Max
−40 °C to +125 °C
All typical values are measured at Tamb = 25 °C
14. Waveforms transfer characteristics
VO
VT+
VI
VT−
VI
VH
VT−
VT+
Fig 23. Transfer characteristic
VO
mna207
mna208
Fig 24. Definition of VT+, VT− and VH
74LVC1G99_1
Product data sheet
VH
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 3 January 2008
19 of 26
74LVC1G99
NXP Semiconductors
Ultra-configurable multiple function gate; 3-state
VO
VI
VT+
VT−
VT−
VO
VI
VH
VT+
VH
mnb155
mnb154
Fig 25. Transfer characteristic
Fig 26. Definition of VT+, VT− and VH
001aab594
16
I CC
(mA)
12
8
4
0
0
1
2
3
VI (V)
Fig 27. Typical 74LVC1G99 transfer characteristic; VCC = 3.0 V
74LVC1G99_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 3 January 2008
20 of 26
74LVC1G99
NXP Semiconductors
Ultra-configurable multiple function gate; 3-state
15. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
D
E
A
SOT505-2
X
c
HE
y
v M A
Z
5
8
A
A2
(A3)
A1
pin 1 index
θ
Lp
L
1
4
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(1)
e
HE
L
Lp
v
w
y
Z(1)
θ
mm
1.1
0.15
0.00
0.95
0.75
0.25
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
0.65
4.1
3.9
0.5
0.47
0.33
0.2
0.13
0.1
0.70
0.35
8°
0°
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE
VERSION
SOT505-2
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
02-01-16
---
Fig 28. Package outline SOT505-2 (TSSOP8)
74LVC1G99_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 3 January 2008
21 of 26
74LVC1G99
NXP Semiconductors
Ultra-configurable multiple function gate; 3-state
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
1
2
SOT833-1
b
4
3
4×
(2)
L
L1
e
8
7
6
e1
5
e1
e1
8×
A
(2)
A1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max
A1
max
b
D
E
e
e1
L
L1
mm
0.5
0.04
0.25
0.17
2.0
1.9
1.05
0.95
0.6
0.5
0.35
0.27
0.40
0.32
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT833-1
---
MO-252
---
EUROPEAN
PROJECTION
ISSUE DATE
07-11-14
07-12-07
Fig 29. Package outline SOT833-1 (XSON8)
74LVC1G99_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 3 January 2008
22 of 26
74LVC1G99
NXP Semiconductors
Ultra-configurable multiple function gate; 3-state
XQFN8U: plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm
B
D
SOT902-1
A
terminal 1
index area
E
A
A1
detail X
L1
e
e
C
∅v M C A B
∅w M C
L
4
y1 C
y
5
3
metal area
not for soldering
e1
b
2
6
e1
7
1
terminal 1
index area
8
X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max
A1
b
D
E
e
e1
L
L1
v
w
y
y1
mm
0.5
0.05
0.00
0.25
0.15
1.65
1.55
1.65
1.55
0.55
0.5
0.35
0.25
0.15
0.05
0.1
0.05
0.05
0.05
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT902-1
---
MO-255
---
EUROPEAN
PROJECTION
ISSUE DATE
05-11-25
07-11-14
Fig 30. Package outline SOT902-1 (XQFN8U)
74LVC1G99_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 3 January 2008
23 of 26
74LVC1G99
NXP Semiconductors
Ultra-configurable multiple function gate; 3-state
16. Abbreviations
Table 28.
Abbreviations
Acronym
Description
CMOS
Complementary Metal Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
17. Revision history
Table 29.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74LVC1G99_1
20080103
Product data sheet
-
-
74LVC1G99_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 3 January 2008
24 of 26
74LVC1G99
NXP Semiconductors
Ultra-configurable multiple function gate; 3-state
18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
18.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
19. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [email protected]
74LVC1G99_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 3 January 2008
25 of 26
74LVC1G99
NXP Semiconductors
Ultra-configurable multiple function gate; 3-state
20. Contents
1
2
3
4
5
6
6.1
6.2
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
9
10
11
12
13
14
15
16
17
18
18.1
18.2
18.3
18.4
19
20
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 4
Logic configurations . . . . . . . . . . . . . . . . . . . . . 5
3-state buffer functions available . . . . . . . . . . . 5
3-state inverter functions available . . . . . . . . . . 6
3-state multiplexer functions available . . . . . . . 6
3-state AND/NOR functions available. . . . . . . . 7
3-state NAND/OR functions available. . . . . . . . 9
3-state XOR/XNOR functions available . . . . . 11
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13
Recommended operating conditions. . . . . . . 13
Static characteristics. . . . . . . . . . . . . . . . . . . . 14
Dynamic characteristics . . . . . . . . . . . . . . . . . 15
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Transfer characteristics. . . . . . . . . . . . . . . . . . 18
Waveforms transfer characteristics . . . . . . . . 19
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 21
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 24
Legal information. . . . . . . . . . . . . . . . . . . . . . . 25
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 25
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Contact information. . . . . . . . . . . . . . . . . . . . . 25
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 3 January 2008
Document identifier: 74LVC1G99_1