74AUP1G98 Low-power configurable multiple function gate Rev. 01 — 8 November 2006 Product data sheet 1. General description The 74AUP1G98 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74AUP1G98 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions MUX, AND, OR, NAND, NOR, inverter and buffer. All inputs can be connected to VCC or GND. The 74AUP1G98 has Schmitt trigger inputs making it capable of transforming slowly changing input signals into sharply defined, jitter-free output signals The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT− is defined as the input hysteresis voltage VH. 2. Features ■ Wide supply voltage range from 0.8 V to 3.6 V ■ High noise immunity ■ ESD protection: ◆ HBM JESD22-A114-D Class 3A exceeds 5000 V ◆ MM JESD22-A115-A exceeds 200 V ◆ CDM JESD22-C101-C exceeds 1000 V ■ Low static power consumption; ICC = 0.9 µA (maximum) ■ Latch-up performance exceeds 100 mA per JESD 78 Class II ■ Inputs accept voltages up to 3.6 V ■ Low noise overshoot and undershoot < 10 % of VCC ■ IOFF circuitry provides partial Power-down mode operation ■ Multiple package options ■ Specified from −40 °C to +85 °C and −40 °C to +125 °C 74AUP1G98 NXP Semiconductors Low-power configurable multiple function gate 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1G98GW −40 °C to +125 °C SC-88 plastic surface-mounted package; 6 leads SOT363 74AUP1G98GM −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1 × 1.45 × 0.5 mm 74AUP1G98GF −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; SOT891 6 terminals; body 1 × 1 × 0.5 mm 4. Marking Table 2. Marking Type number Marking code 74AUP1G98GW a9 74AUP1G98GM a9 74AUP1G98GF a9 5. Functional diagram A 3 4 B C 1 Y 6 001aad987 Fig 1. Logic symbol 74AUP1G98_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 8 November 2006 2 of 19 74AUP1G98 NXP Semiconductors Low-power configurable multiple function gate 6. Pinning information 6.1 Pinning 74AUP1G98 74AUP1G98 B 1 6 B 1 6 C GND 2 5 VCC C GND 2 5 VCC A 3 4 Y A 3 4 Y 74AUP1G98 B 1 6 C GND 2 5 VCC A 3 4 Y 001aad989 001aad990 Transparent top view Transparent top view 001aad988 Fig 2. Pin configuration SOT363 (SC-88) Fig 3. Pin configuration SOT886 (XSON6) Fig 4. Pin configuration SOT891 (XSON6) 6.2 Pin description Table 3. Pin description Symbol Pin Description B 1 data input B GND 2 ground (0 V) A 3 data input A Y 4 data output Y VCC 5 supply voltage C 6 data input C 7. Functional description Table 4. Function table[1] Input Output C B A Y L L L H L L H H L H L L L H H L H L L H H L H L H H L H H H H L [1] H = HIGH voltage level; L = LOW voltage level. 74AUP1G98_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 8 November 2006 3 of 19 74AUP1G98 NXP Semiconductors Low-power configurable multiple function gate 7.1 Logic configurations Table 5. Function selection table Logic function Figure 2-input MUX with inverted output see Figure 5 2-input NAND see Figure 6 2-input NOR with one input inverted see Figure 7 2-input AND with one input inverted see Figure 7 2-input NAND with one input inverted see Figure 8 2-input OR with one input inverted see Figure 8 2-input NOR see Figure 9 Buffer see Figure 10 Inverter see Figure 11 VCC B B 1 6 C Y A A C 2 5 3 4 VCC A C Y A Y 1 6 2 5 3 4 001aad991 Fig 5. 2-input MUX with inverted output C Y 001aad992 Fig 6. 2-input NAND gate VCC VCC A C Y A C Y A 1 6 2 5 3 4 C Y B C Y B C Y B 1 6 2 5 3 4 001aad993 Fig 7. 2-input AND gate with input A inverted or 2-input NOR gate with inverted C input C Y 001aad994 Fig 8. 2-input OR gate with input B inverted or 2-input NAND gate with input C inverted VCC B B C Y 1 6 2 5 3 4 VCC C C 2 5 3 4 C Y 001aad996 Fig 10. Buffer 74AUP1G98_1 Product data sheet 6 Y 001aad995 Fig 9. 2-input NOR gate Y 1 © NXP B.V. 2006. All rights reserved. Rev. 01 — 8 November 2006 4 of 19 74AUP1G98 NXP Semiconductors Low-power configurable multiple function gate VCC B B Y 1 6 2 5 3 4 Y 001aad997 Fig 11. Inverter 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage Conditions Min Max Unit −0.5 +4.6 V - −50 mA [1] −0.5 +4.6 V - ±50 mA [1] −0.5 +4.6 V - ±20 mA - 50 mA VI < 0 V IOK output clamping current VO > VCC or VO < 0 V VO output voltage Active mode and Power-down mode IO output current VO = 0 V to VCC ICC supply current IGND ground current - −50 mA Tstg storage temperature −65 +150 °C Ptot total power dissipation - 250 mW Tamb = −40 °C to +125 °C [2] [1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SC-88 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K. 9. Recommended operating conditions Table 7. Recommended operating conditions Symbol Parameter Min Max Unit VCC supply voltage Conditions 0.8 3.6 V VI input voltage 0 3.6 V VO output voltage Active mode 0 VCC V Power-down mode; VCC = 0 V 0 3.6 V Tamb ambient temperature −40 +125 °C 74AUP1G98_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 8 November 2006 5 of 19 74AUP1G98 NXP Semiconductors Low-power configurable multiple function gate 10. Static characteristics Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit IO = −20 µA; VCC = 0.8 V to 3.6 V VCC − 0.1 - - V IO = −1.1 mA; VCC = 1.1 V 0.75 × VCC - - V IO = −1.7 mA; VCC = 1.4 V 1.11 - V Tamb = 25 °C VOH VOL HIGH-level output voltage LOW-level output voltage VI = VIH or VIL - IO = −1.9 mA; VCC = 1.65 V 1.32 - - V IO = −2.3 mA; VCC = 2.3 V 2.05 - - V IO = −3.1 mA; VCC = 2.3 V 1.9 - - V IO = −2.7 mA; VCC = 3.0 V 2.72 - - V IO = −4.0 mA; VCC = 3.0 V 2.6 - - V IO = 20 µA; VCC = 0.8 V to 3.6 V - - 0.1 V IO = 1.1 mA; VCC = 1.1 V - - 0.3 × VCC V VI = VIH or VIL IO = 1.7 mA; VCC = 1.4 V - - 0.31 V IO = 1.9 mA; VCC = 1.65 V - - 0.31 V IO = 2.3 mA; VCC = 2.3 V - - 0.31 V IO = 3.1 mA; VCC = 2.3 V - - 0.44 V IO = 2.7 mA; VCC = 3.0 V - - 0.31 V IO = 4.0 mA; VCC = 3.0 V - - 0.44 V II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - ±0.1 µA IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - ±0.2 µA ∆IOFF additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - ±0.2 µA ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 0.5 µA ∆ICC additional supply current VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V - - 40 µA CI input capacitance VCC = 0 V to 3.6 V; VI = GND or VCC - 1.1 - pF CO output capacitance VO = GND; VCC = 0 V - 1.8 - pF IO = −20 µA; VCC = 0.8 V to 3.6 V VCC − 0.1 - - V IO = −1.1 mA; VCC = 1.1 V 0.7 × VCC - - V IO = −1.7 mA; VCC = 1.4 V 1.03 - - V IO = −1.9 mA; VCC = 1.65 V 1.30 - - V IO = −2.3 mA; VCC = 2.3 V 1.97 - - V IO = −3.1 mA; VCC = 2.3 V 1.85 - - V IO = −2.7 mA; VCC = 3.0 V 2.67 - - V IO = −4.0 mA; VCC = 3.0 V 2.55 - - V [1] Tamb = −40 °C to +85 °C VOH HIGH-level output voltage VI = VIH or VIL 74AUP1G98_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 8 November 2006 6 of 19 74AUP1G98 NXP Semiconductors Low-power configurable multiple function gate Table 8. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VOL VI = VIH or VIL LOW-level output voltage II input leakage current Min Typ Max Unit IO = 20 µA; VCC = 0.8 V to 3.6 V - - 0.1 V IO = 1.1 mA; VCC = 1.1 V - - 0.3 × VCC V IO = 1.7 mA; VCC = 1.4 V - - 0.37 V IO = 1.9 mA; VCC = 1.65 V - - 0.35 V IO = 2.3 mA; VCC = 2.3 V - - 0.33 V IO = 3.1 mA; VCC = 2.3 V - - 0.45 V IO = 2.7 mA; VCC = 3.0 V - - 0.33 V IO = 4.0 mA; VCC = 3.0 V - - 0.45 V VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - ±0.5 µA IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - ±0.5 µA ∆IOFF additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - ±0.6 µA ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 0.9 µA ∆ICC additional supply current VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V - - 50 µA [1] Tamb = −40 °C to +125 °C VOH VOL HIGH-level output voltage LOW-level output voltage VI = VIH or VIL IO = −20 µA; VCC = 0.8 V to 3.6 V VCC − 0.11 - - V IO = −1.1 mA; VCC = 1.1 V 0.6 × VCC - - V IO = −1.7 mA; VCC = 1.4 V 0.93 - - V IO = −1.9 mA; VCC = 1.65 V 1.17 - - V IO = −2.3 mA; VCC = 2.3 V 1.77 - - V IO = −3.1 mA; VCC = 2.3 V 1.67 - - V IO = −2.7 mA; VCC = 3.0 V 2.40 - - V IO = −4.0 mA; VCC = 3.0 V 2.30 - - V IO = 20 µA; VCC = 0.8 V to 3.6 V - - 0.11 V IO = 1.1 mA; VCC = 1.1 V - - 0.33 × VCC V VI = VIH or VIL IO = 1.7 mA; VCC = 1.4 V - - 0.41 V IO = 1.9 mA; VCC = 1.65 V - - 0.39 V IO = 2.3 mA; VCC = 2.3 V - - 0.36 V IO = 3.1 mA; VCC = 2.3 V - - 0.50 V IO = 2.7 mA; VCC = 3.0 V - - 0.36 V IO = 4.0 mA; VCC = 3.0 V - - 0.50 V II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - ±0.75 µA IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - ±0.75 µA 74AUP1G98_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 8 November 2006 7 of 19 74AUP1G98 NXP Semiconductors Low-power configurable multiple function gate Table 8. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit ∆IOFF additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - ±0.75 µA ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 1.4 µA ∆ICC additional supply current VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V - - 75 µA [1] [1] One input at VCC − 0.6 V, other input at VCC or GND. 11. Dynamic characteristics Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13. Symbol Parameter 25 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min - 23.3 - - - - ns VCC = 1.1 V to 1.3 V 2.9 6.7 12.9 2.7 13.2 13.4 ns VCC = 1.4 V to 1.6 V 2.4 4.8 7.7 2.4 8.3 8.7 ns Max Max (85 °C) (125 °C) CL = 5 pF tpd propagation delay A, B, C to Y; see Figure 12 [2] VCC = 0.8 V VCC = 1.65 V to 1.95 V 2.2 4.0 6.3 1.9 7.0 7.4 ns VCC = 2.3 V to 2.7 V 2.0 3.2 4.6 1.8 5.2 5.4 ns VCC = 3.0 V to 3.6 V 1.9 2.9 4.0 1.6 4.2 4.4 ns - 27.1 - - - - ns VCC = 1.1 V to 1.3 V 3.3 7.6 14.5 3.0 15.1 15.3 ns VCC = 1.4 V to 1.6 V 2.7 5.4 8.8 2.8 9.5 9.9 ns CL = 10 pF tpd propagation delay A, B, C to Y; see Figure 12 [2] VCC = 0.8 V VCC = 1.65 V to 1.95 V 2.5 4.6 7.2 2.3 8.0 8.4 ns VCC = 2.3 V to 2.7 V 2.4 3.8 5.3 2.2 5.9 6.2 ns VCC = 3.0 V to 3.6 V 2.3 3.5 4.7 2.0 4.9 5.2 ns - 30.6 - - - - ns VCC = 1.1 V to 1.3 V 3.6 8.4 16.1 3.3 16.9 17.2 ns VCC = 1.4 V to 1.6 V 3.0 6.0 9.7 3.1 10.5 11.0 ns CL = 15 pF tpd propagation delay A, B, C to Y; see Figure 12 VCC = 0.8 V [2] VCC = 1.65 V to 1.95 V 2.8 5.1 7.9 2.5 8.9 9.3 ns VCC = 2.3 V to 2.7 V 2.7 4.2 5.9 2.5 6.6 7.0 ns VCC = 3.0 V to 3.6 V 2.5 3.9 5.2 2.2 5.5 5.8 ns 74AUP1G98_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 8 November 2006 8 of 19 74AUP1G98 NXP Semiconductors Low-power configurable multiple function gate Table 9. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13. Symbol Parameter 25 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min - 38.7 - - - - ns VCC = 1.1 V to 1.3 V 4.5 10.7 21.1 4.1 22.0 22.4 ns VCC = 1.4 V to 1.6 V 3.8 7.6 12.3 3.8 13.5 14.2 ns VCC = 1.65 V to 1.95 V 3.5 6.3 10.1 3.1 11.3 11.9 ns VCC = 2.3 V to 2.7 V 3.4 5.3 7.5 3.2 8.4 8.9 ns VCC = 3.0 V to 3.6 V 3.2 5.0 6.7 2.9 7.1 7.5 ns VCC = 0.8 V - 3.0 - - - - pF VCC = 1.1 V to 1.3 V - 3.2 - - - - pF VCC = 1.4 V to 1.6 V - 3.3 - - - - pF VCC = 1.65 V to 1.95 V - 3.5 - - - - pF VCC = 2.3 V to 2.7 V - 4.1 - - - - pF VCC = 3.0 V to 3.6 V - 4.6 - - - - pF Max Max (85 °C) (125 °C) CL = 30 pF propagation delay tpd A, B, C to Y; see Figure 12 [2] VCC = 0.8 V CL = 5 pF, 10 pF, 15 pF and 30 pF power dissipation capacitance CPD fi = 1 MHz; VI = GND to VCC [3] [1] All typical values are measured at nominal VCC. [2] tpd is the same as tPLH and tPHL [3] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. 74AUP1G98_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 8 November 2006 9 of 19 74AUP1G98 NXP Semiconductors Low-power configurable multiple function gate 12. Waveforms VI A, B, C input VM VM GND t PHL t PLH VOH VM Y output VM VOL t PLH t PHL VOH Y output VM VM VOL 001aab593 Measurement points are given in Table 10. VOL and VOH are typical output voltage drop that occur with the output load. Fig 12. Input A, B and C to output Y propagation delay times. Table 10. Measurement points Supply voltage Output Input VCC VM VM VI tr = tf 0.8 V to 3.6 V 0.5 × VCC 0.5 × VCC VCC ≤ 3.0 ns 74AUP1G98_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 8 November 2006 10 of 19 74AUP1G98 NXP Semiconductors Low-power configurable multiple function gate VCC VEXT 5 kΩ PULSE GENERATOR VI VO DUT RT CL RL 001aac521 Test data is given in Table 11. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 13. Load circuitry for switching times Table 11. Test data Supply voltage Load VEXT RL[1] VCC CL 0.8 V to 3.6 V 5 pF, 10 pF, 15 pF and 30 pF 5 kΩ or 1 MΩ [1] tPLH, tPHL tPZH, tPHZ tPZL, tPLZ open GND 2 × VCC For measuring enable and disable times RL = 5 kΩ, for measuring propagation delays, setup and hold times and pulse width RL = 1 MΩ. 13. Transfer characteristics Table 12. Transfer characteristics Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 13. Symbol Parameter VT+ VT− 25 °C Conditions positive-going see Figure 14 and Figure 15 threshold voltage VCC = 0.8 V Typ Max Min Max (85 °C) Max (125 °C) Unit 0.30 - 0.60 0.30 0.60 0.62 V VCC = 1.1 V 0.53 - 0.90 0.53 0.90 0.92 V VCC = 1.4 V 0.74 - 1.11 0.74 1.11 1.13 V VCC = 1.65 V 0.91 - 1.29 0.91 1.29 1.31 V VCC = 2.3 V 1.37 - 1.77 1.37 1.77 1.80 V VCC = 3.0 V 1.88 - 2.29 1.88 2.29 2.32 V 0.10 - 0.60 0.10 0.60 0.60 V VCC = 1.1 V 0.26 - 0.65 0.26 0.65 0.65 V VCC = 1.4 V 0.39 - 0.75 0.39 0.75 0.75 V VCC = 1.65 V 0.47 - 0.84 0.47 0.84 0.84 V VCC = 2.3 V 0.69 - 1.04 0.69 1.04 1.04 V VCC = 3.0 V 0.88 - 1.24 0.88 1.24 1.24 V negative-going see Figure 14 and Figure 15 threshold voltage VCC = 0.8 V 74AUP1G98_1 Product data sheet −40 °C to +125 °C Min © NXP B.V. 2006. All rights reserved. Rev. 01 — 8 November 2006 11 of 19 74AUP1G98 NXP Semiconductors Low-power configurable multiple function gate Table 12. Transfer characteristics …continued Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 13. Symbol Parameter VH 25 °C Conditions −40 °C to +125 °C Unit Min Typ Max Min Max (85 °C) Max (125 °C) VCC = 0.8 V 0.07 - 0.50 0.07 0.50 0.50 V VCC = 1.1 V 0.08 - 0.46 0.08 0.46 0.46 V VCC = 1.4 V 0.18 - 0.56 0.18 0.56 0.56 V VCC = 1.65 V 0.27 - 0.66 0.27 0.66 0.66 V VCC = 2.3 V 0.53 - 0.92 0.53 0.92 0.92 V VCC = 3.0 V 0.79 - 1.31 0.79 1.31 1.31 V (VT+ − VT−); see Figure 14, Figure 15, Figure 16 and Figure 17 hysteresis voltage 14. Waveforms transfer characteristics VT+ VO VI VH VT− VO VI VH VT− VT+ mna208 mna207 VT+ and VT− limits at 70 % and 20 %. Fig 14. Transfer characteristic Fig 15. Definition of VT+, VT− and VH 74AUP1G98_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 8 November 2006 12 of 19 74AUP1G98 NXP Semiconductors Low-power configurable multiple function gate 001aad691 240 ICC (µA) 160 80 0 0 0.4 0.8 1.2 1.6 2.0 VI (V) Fig 16. Typical transfer characteristics; VCC = 1.8 V 001aad692 1200 ICC (µA) 800 400 0 0 1.0 2.0 3.0 VI (V) Fig 17. Typical transfer characteristics; VCC = 3.0 V 74AUP1G98_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 8 November 2006 13 of 19 74AUP1G98 NXP Semiconductors Low-power configurable multiple function gate 15. Package outline Plastic surface-mounted package; 6 leads SOT363 D E B y X A HE 6 5 v M A 4 Q pin 1 index A A1 1 2 e1 3 bp c Lp w M B e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.30 0.20 0.25 0.10 2.2 1.8 1.35 1.15 1.3 0.65 2.2 2.0 0.45 0.15 0.25 0.15 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC SOT363 JEDEC JEITA SC-88 EUROPEAN PROJECTION ISSUE DATE 04-11-08 06-03-16 Fig 18. Package outline SOT363 (SC-88) 74AUP1G98_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 8 November 2006 14 of 19 74AUP1G98 NXP Semiconductors Low-power configurable multiple function gate XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886 b 1 2 3 4× (2) L L1 e 6 5 e1 4 e1 6× A (2) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A (1) max A1 max b D E e e1 L L1 mm 0.5 0.04 0.25 0.17 1.5 1.4 1.05 0.95 0.6 0.5 0.35 0.27 0.40 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT886 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 04-07-15 04-07-22 MO-252 Fig 19. Package outline SOT886 (XSON6) 74AUP1G98_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 8 November 2006 15 of 19 74AUP1G98 NXP Semiconductors Low-power configurable multiple function gate XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm 1 SOT891 b 3 2 L L1 e 6 5 4 e1 e1 A A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 max b D E e e1 L L1 mm 0.5 0.04 0.20 0.12 1.05 0.95 1.05 0.95 0.55 0.35 0.35 0.27 0.40 0.32 OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-03-11 05-04-06 SOT891 Fig 20. Package outline SOT891 (XSON6) 74AUP1G98_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 8 November 2006 16 of 19 74AUP1G98 NXP Semiconductors Low-power configurable multiple function gate 16. Abbreviations Table 13. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 17. Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AUP1G98_1 20061108 Product data sheet - - 74AUP1G98_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 8 November 2006 17 of 19 74AUP1G98 NXP Semiconductors Low-power configurable multiple function gate 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. 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This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] 74AUP1G98_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 8 November 2006 18 of 19 74AUP1G98 NXP Semiconductors Low-power configurable multiple function gate 20. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 12 13 14 15 16 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Logic configurations . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Transfer characteristics. . . . . . . . . . . . . . . . . . 11 Waveforms transfer characteristics . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2006. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 8 November 2006 Document identifier: 74AUP1G98_1