INTERSIL ACS174D

ACS174MS
Data Sheet
Radiation Hardened Hex D-Type Flip-Flop
with Reset
The Radiation Hardened ACS174MS is a Hex D-Type FlipFlop with Reset. Information at the D input is transferred to
the Q output on the positive-going transition of the clock. All
six flip-flops are controlled by a common clock (CP) and a
common reset (MR). Resetting is accomplished by a LOW
level independent of the clock. All inputs are buffered and
the outputs are designed for balanced propagation delay
and transition times.
The ACS174MS is fabricated on a CMOS Silicon on
Sapphire (SOS) process, which provides an immunity to
Single Event Latch-up and the capability of highly reliable
performance in any radiation environment. These devices
offer significant power reduction and faster performance
when compared to ALSTTL types.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed below must be used when ordering.
Detailed Electrical Specifications for the ACS174MS are
contained in SMD 5962-98634. A “hot-link” is provided
on our homepage for downloading.
http://www.intersil.com/spacedefense/spaceselect.htm
July 1999
File Number
4762
Features
• QML Qualified Per MIL-PRF-38535 Requirements
• 1.25 Micron Radiation Hardened SOS CMOS
• Radiation Environment
- Latch-Up Free Under Any Conditions
- Total Dose (Max.) . . . . . . . . . . . . . . . . . 3 x 105 RAD(Si)
- SEU Immunity . . . . . . . . . . . . . <1 x 10-10 Errors/Bit/Day
- SEU LET Threshold . . . . . . . . . . . . >100MeV/(mg/cm2)
• Input Logic Levels. . . . VIL = (0.3)(VCC), VIH = (0.7)(VCC)
• Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . ±12mA (Min)
• Quiescent Supply Current . . . . . . . . . . . . . . . 10µA (Max)
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . . 23ns (Max)
Applications
• High Speed Control Circuits
• Sensor Monitoring
• Low Power Designs
Ordering Information
INTERNAL MARKETING
NUMBER
ORDERING NUMBER
5962F9863401VCC
ACS174DMSR-03
ACS174D/SAMPLE-03
ACS174D/SAMPLE-03
5962F9863401VXC
ACS174KMSR-03
ACS174K/SAMPLE-03
5962F9863401V9A
TEMP. RANGE (oC)
PACKAGE
DESIGNATOR
-55 to 125
16 Ld SBDIP
CDIP2-T16
25
16 Ld SBDIP
CDIP2-T16
-55 to 125
16 Ld Flatpack
CDFP4-F16
ACS174K/SAMPLE-03
25
16 Ld Flatpack
CDFP4-F16
ACS174HMSR-03
25
Die
NA
Pinouts
ACS174MS
(SBDIP)
TOP VIEW
ACS174MS
(FLATPACK)
TOP VIEW
MR 1
16 VCC
MR
1
16
VCC
Q0 2
15 Q5
Q0
2
15
Q5
D0 3
14 D5
D0
3
14
D5
D1 4
13 D4
D1
4
13
D4
12 Q4
Q1
5
12
Q4
D2
6
11
D3
Q2
7
10
Q3
GND
8
9
CP
Q1 5
11 D3
D2 6
Q2 7
10 Q3
GND 8
9 CP
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
ACS174MS
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
Size: 2390µm x 2390µm (94 mils x 94 mils)
Thickness: 525µm ±25µm (20.6 mils ±1 mil)
Bond Pad: 110µm x 110µm (4.3 x 4.3 mils)
Type: Phosphorous Silicon Glass (PSG)
Thickness: 1.30µm ±0.15µm
SPECIAL INSTRUCTIONS
METALLIZATION: AI
Bond VCC First
Metal 1 Thickness: 0.7µm ±0.1µm
Metal 2 Thickness: 1.0µm ±0.1µm
ADDITIONAL INFORMATION:
Worst Case Current Density: <2.0 x 105 A/cm2
Transistor Count: 358
SUBSTRATE POTENTIAL
Unbiased Insulator
Metallization Mask Layout
ACS174MSX
Q0
(2)
MR
(1)
VCC
(16)
Q5
(15)
(14) D5
D0 (3)
(13) D4
D1 (4)
(12) Q4
Q1 (5)
(11) D3
D2 (6)
(7)
Q2
(8)
GND
(9)
CP
(10)
Q3
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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