a APPLICATIONS Routing of High Speed Signals Including: Composite Video (NTSC, PAL, S, SECAM) Component Video (YUV, RGB) Compressed Video (MPEG, Wavelet) 3-Level Digital Video (HDB3) PRODUCT DESCRIPTION The AD8110 and AD8111 are high speed 16 × 8 video crosspoint switch matrices. They offer a –3 dB signal bandwidth greater than 260 MHz, and channel switch times of less than 25 ns with 1% settling. With –78 dB of crosstalk and –97 dB isolation (@ 5 MHz), the AD8110/AD8111 are useful in many high speed applications. The differential gain and differential FUNCTIONAL BLOCK DIAGRAM SER/PAR D0 D1 D2 D3 D4 A0 A1 CLK 40-BIT SHIFT REGISTER WITH 5-BIT PARALLEL LOADING UPDATE CE 40 PARALLEL LATCH RESET 40 DECODE 8 3 5:16 DECODERS AD8110/AD8111 128 SWITCH MATRIX 16 INPUTS DATA OUT SET INDIVIDUAL OR RESET ALL OUTPUTS TO "OFF" DATA IN A2 8 OUTPUT BUFFER G = +1, G = +2 ENABLE/DISABLE FEATURES 16 3 8 High Speed Nonblocking Switch Arrays AD8110: G = +1 AD8111: G = +2 Serial or Parallel Switch Array Control Serial Data Out Allows “Daisy Chaining” of Multiple Crosspoints to Create Larger Switch Arrays Pin Compatible with AD8108/AD8109 8 3 8 Switch Arrays For a 16 3 16 Array See AD8116 Complete Solution Buffered Inputs Eight Output Amplifiers, AD8110 (G = +1), AD8111 (G = +2) Drives 150 V Loads Excellent Video Performance 60 MHz 0.1 dB Gain Flatness 0.02% Differential Gain Error (RL = 150 V) 0.028 Differential Phase Error (RL = 150 V) Excellent AC Performance 260 MHz –3 dB Bandwidth 500 V/ms Slew Rate Low Power of 50 mA Low All Hostile Crosstalk of –78 dB @ 5 MHz Output Disable Allows Direct Connection of Multiple Device Outputs Reset Pin Allows Disabling of All Outputs (Connected Through a Capacitor to Ground Provides “PowerOn” Reset Capability) Excellent ESD Rating: Exceeds 4000 V Human Body Model 80-Lead TQFP Package (12 mm 3 12 mm) 260 MHz, 16 3 8 Buffered Video Crosspoint Switches AD8110/AD8111* 8 OUTPUTS phase of better than 0.02% and 0.02° respectively, along with 0.1 dB flatness out to 60 MHz, make the AD8110/AD8111 ideal for video signal switching. The AD8110 and AD8111 include eight independent output buffers that can be placed into a high impedance state for paralleling crosspoint outputs so that off channels do not load the output bus. The AD8110 has a gain of +1, while the AD8111 offers a gain of +2. They operate on voltage supplies of ± 5 V while consuming only 50 mA of idle current. The channel switching is performed via a serial digital control (which can accommodate “daisy chaining” of several devices) or via a parallel control, allowing updating of an individual output without reprograming the entire array. The AD8110/AD8111 is packaged in an 80-lead TQFP package and is available over the extended industrial temperature range of –40°C to +85°C. *Patent Pending. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1997 AD8110/AD8111–SPECIFICATIONS (V = 65 V, T = +258C, R = 1 kV unless otherwise noted) S Parameter DYNAMIC PERFORMANCE –3 dB Bandwidth Propagation Delay Slew Rate Settling Time Gain Flatness NOISE/DISTORTION PERFORMANCE Differential Gain Error Differential Phase Error Crosstalk, All Hostile Off Isolation, Input-Output Input Voltage Noise DC PERFORMANCE Gain Error Gain Matching A Output Disable Capacitance Output Leakage Current Output Voltage Range Output Current Short Circuit Current INPUT CHARACTERISTICS Input Offset Voltage Input Voltage Range Input Capacitance Input Resistance Input Bias Current SWITCHING CHARACTERISTICS Enable On Time Switching Time, 2 V Step Switching Transient (Glitch) POWER SUPPLIES Supply Current Supply Voltage Range PSRR OPERATING TEMPERATURE RANGE Temperature Range θJA AD8110/AD8111 Typ Conditions Min 200 mV p-p, RL = 150 Ω 2 V p-p, RL = 150 Ω 2 V p-p, RL = 150 Ω 2 V Step, RL = 150 Ω 0.1%, 2 V Step, RL = 150 Ω 0.05 dB, 200 mV p-p, RL = 150 Ω 0.05 dB, 2 V p-p, R L = 150 Ω 0.1 dB, 200 mV p-p, RL = 150 Ω 0.1 dB, 2 V p-p, RL = 150 Ω 300/190 Max Units 390/260 150 5 500 40 60/40 65/40 80/57 70/57 MHz MHz ns V/µs ns MHz MHz MHz MHz NTSC or PAL, RL = 1 kΩ NTSC or PAL, RL =150 Ω NTSC or PAL, RL = 1 kΩ NTSC or PAL, RL = 150 Ω f = 5 MHz f = 10 MHz f = 10 MHz, RL =150 Ω, One Channel 0.01 MHz to 50 MHz 0.01 0.02 0.01 0.02 78/85 70/80 93/99 15 % % Degrees Degrees dB dB dB nV/√Hz RL = 1 kΩ RL = 150 Ω No Load, Channel-Channel RL = 1 kΩ, Channel-Channel 0.04/0.1 0.15/0.25 DC, Enabled Disabled Disabled Disabled, AD8110 Only No Load ± 2.5 20 Worse Case (All Configurations) Temperature Coefficient Any Switch Configuration Per Output Selected 0.07/0.5 11, 17 6, 12 6, 12 6, 12 6, 12 7, 13 7, 13 22, 28 19, 25 0.2 10/0.001 2 1/NA ±3 40 65 Ω MΩ pF µA V mA mA 23, 29 20, 26 mV µV/°C V pF MΩ µA 34, 40 35, 41 5 12 ± 2.5/± 1.25 ± 3/± 1.5 2.5 1 10 2 20 5 ns ns mV p-p f = 100 kHz f = 1 MHz 38 15 38 15 11 ± 4.5 to ±5.5 75/78 –55/–58 mA mA mA mA mA V dB dB Operating (Still Air) Operating (Still Air) –40 to +85 48 °C °C/W AVCC, Outputs Enabled, No Load AVCC, Outputs Disabled AVEE, Outputs Enabled, No Load AVEE, Outputs Disabled DVCC 6, 12 6, 12 0.5/8 60 25 20/30 50% UPDATE to 1% Settling Measured at Output Reference Figure No. % % % % ppm/°C 0.02/1.0 0.09/1.0 Gain Temperature Coefficient OUTPUT CHARACTERISTICS Output Impedance L 21, 27 18, 24 Specifications subject to change without notice. –2– REV. 0 AD8110/AD8111 TIMING CHARACTERISTICS (Serial) Parameter Symbol Min Serial Data Setup Time CLK Pulsewidth Serial Data Hold Time CLK Pulse Separation, Serial Mode CLK to UPDATE Delay UPDATE Pulsewidth CLK to DATA OUT Valid, Serial Mode Propagation Delay, UPDATE to Switch On or Off Data Load Time, CLK = 5 MHz, Serial Mode CLK, UPDATE Rise and Fall Times RESET Time t1 t2 t3 t4 t5 t6 t7 – – – – 20 100 20 100 0 50 t2 1 CLK 0 1 DATA IN 0 t1 Limit Typ Units ns ns ns ns ns ns ns ns µs ns ns 180 8 8 100 200 t4 LOAD DATA INTO SERIAL REGISTER ON FALLING EDGE t3 OUT7 (D4) OUT7 (D3) OUT00 (D0) t5 1 = LATCHED UPDATE 0 = TRANSPARENT Max t6 TRANSFER DATA FROM SERIAL REGISTER TO PARALLEL LATCHES DURING LOW LEVEL t7 DATA OUT Figure 1. Timing Diagram, Serial Mode Table I. Logic Levels VIH VIL RESET, SER/PAR CLK, DATA IN, CE, UPDATE RESET, SER/PAR CLK, DATA IN, CE, UPDATE 2.0 V min 0.8 V max REV. 0 VOH VOL IIH IIL IOH IOL DATA OUT DATA OUT RESET, SER/PAR CLK, DATA IN, CE, UPDATE RESET, SER/PAR CLK, DATA IN, CE, UPDATE DATA OUT DATA OUT 2.7 V min 0.5 V max 20 µA max –400 µA min –400 µA max 3.0 mA min –3– AD8110/AD8111 TIMING CHARACTERISTICS (Parallel) Limit Parameter Symbol Min Data Setup Time CLK Pulsewidth Data Hold Time CLK Pulse Separation CLK to UPDATE Delay UPDATE Pulsewidth Propagation Delay, UPDATE to Switch On or Off CLK, UPDATE Rise and Fall Times RESET Time t1 t2 t3 t4 t5 t6 – – – 20 100 20 100 0 50 t2 Max Units ns ns ns ns ns ns ns ns ns 8 100 200 t4 1 CLK 0 t1 D0–D4 A0–A2 t3 1 0 t5 t6 1 = LATCHED UPDATE 0 = TRANSPARENT Figure 2. Timing Diagram, Parallel Mode Table II. Logic Levels VIH VIL RESET, SER/PAR CLK, D0, D1, D2, D3, D4, A0, A1, A2 CE, UPDATE 2.0 V min VOH VOL IIH IIL IOH IOL RESET, SER/PAR CLK, D0, D1, D2, D3, D4, A0, A1, A2 CE, UPDATE DATA OUT DATA OUT RESET, SER/PAR CLK, D0, D1, D2, D3, D4, A0, A1, A2 CE, UPDATE RESET, SER/PAR CLK, D0, D1, D2, D3, D4, A0, A1, A2 CE, UPDATE DATA OUT DATA OUT 0.8 V max 0.5 V max 20 µA max –400 µA min –400 µA max 3.0 mA min 2.7 V min –4– REV. 0 AD8110/AD8111 ABSOLUTE MAXIMUM RATINGS 1 MAXIMUM POWER DISSIPATION Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12.0 V Internal Power Dissipation2 AD8110/AD8111 80-Lead Plastic TQFP (ST) . . . . . 2.6 W Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .± VS Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves Storage Temperature Range . . . . . . . . . . . . –65°C to +125°C Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C The maximum power that can be safely dissipated by the AD8110/AD8111 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately +150°C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of +175°C for an extended period can result in device failure. NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2Specification is for device in free air (T = +25°C): A 80-lead plastic TQFP (ST): θ JA = 48°C/W. While the AD8110/AD8111 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (+150°C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves shown in Figure 3. MAXIMUM POWER DISSIPATION – Watts 5.0 TJ = 1508C 4.0 3.0 2.0 1.0 0 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 AMBIENT TEMPERATURE – 8C 80 90 Figure 3. Maximum Power Dissipation vs. Temperature ORDERING GUIDE Model AD8110AST AD8111AST AD8110-EB AD8111-EB Temperature Range Package Description Package Option –40°C to +85°C –40°C to +85°C 80-Lead Plastic TQFP (12 mm × 12 mm) 80-Lead Plastic TQFP (12 mm × 12 mm) Evaluation Board Evaluation Board ST-80A ST-80A CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8110/AD8111 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –5– WARNING! ESD SENSITIVE DEVICE AD8110/AD8111 Table III. Operation Truth Table CE UPDATE CLK DATA IN DATA OUT RESET SER/ PAR 1 0 X 1 X f X Data i X Data i-40 X 1 X 0 0 1 f D0 . . . D4, A0 . . . A2 NA in Parallel Mode 1 1 0 0 X X X 1 X X X X X X 0 X PARALLEL DATA (OUTPUT ENABLE) Operation/Comment No change in logic. The data on the serial DATA IN line is loaded into serial register. The first bit clocked into the serial register appears at DATA OUT 40 clocks later. The data on the parallel data lines, D0–D4, are loaded into the 40-bit serial shift register location addressed by A0–A2. Data in the 40-bit shift register transfers into the parallel latches that control the switch array. Latches are transparent. Asynchronous operation. All outputs are disabled. Remainder of logic is unchanged. D0 D1 D2 D3 D4 SER/PAR S D1 Q D0 DATA IN (SERIAL) S D1 D Q Q D0 CLK S D1 D Q Q D0 CLK S D1 D Q Q D0 CLK D Q CLK S D1 S D1 Q D Q D0 CLK Q D0 D Q CLK S D1 S D1 Q D Q D0 CLK Q D0 S D1 D Q Q D0 CLK S D1 D Q Q D0 CLK S D1 D Q Q D0 CLK S D1 D Q Q D0 CLK D Q DATA OUT CLK CLK CE UPDATE OUT0 EN A0 A1 A2 3 TO 8 DECODER OUT1 EN OUT2 EN OUT3 EN OUT4 EN OUT5 EN OUT6 EN OUT7 EN LE D LE D LE D LE D LE D LE D LE D LE D LE D LE D LE D LE D OUT0 B0 OUT0 B1 OUT0 B2 OUT0 B3 OUT0 EN OUT1 B0 OUT6 EN OUT7 B0 OUT7 B1 OUT7 B2 OUT7 B3 OUT7 EN Q Q Q Q CLR Q Q Q Q Q Q CLR Q CLR Q RESET (OUTPUT ENABLE) DECODE 8 128 SWITCH MATRIX OUTPUT ENABLE Figure 4. Logic Diagram –6– REV. 0 AD8110/AD8111 PIN FUNCTION DESCRIPTIONS Pin Name Pin Numbers Pin Description INxx 66, 68, 70, 72, 74, 76, 78, 1, 3, 5, 7, 9, 11, 13, 15, 64 57 58 59 56 Analog Inputs; xx = Channel Numbers 00 Through 15. DATA IN CLK DATA OUT UPDATE RESET CE SER/PAR OUTyy AGND DVCC DGND AVEE AVCC AGNDxx AVCCxx/yy AVEExx/yy A0 A1 A2 D0 D1 D2 D3 D4 61 60 55 41, 38, 35, 32, 29, 26, 23, 20 2, 4, 6, 8, 10, 12, 14, 16, 46 65, 67, 69, 71, 73, 75, 77 63, 79 62, 80 17, 45 18, 44 42, 39, 36, 33, 30, 27, 24, 21 43, 37, 31, 25, 22, 19 40, 34, 28, 22 54 53 52 51 50 49 48 47 Serial Data Input, TTL Compatible. Clock, TTL Compatible. Falling Edge Triggered. Serial Data Out, TTL Compatible. Enable (Transparent) “Low.” Allows serial register to connect directly to switch matrix. Data latched when “High.” Disable Outputs, Active “Low.” Chip Enable, Enable “Low.” Must be “low” to clock in and latch data. Selects Serial Data Mode, “Low” or Parallel Data Mode, “High.” Must be connected. Analog Outputs yy = Channel Numbers 00 Through 07. Analog Ground for Inputs and Switch Matrix. +5 V for Digital Circuitry. Ground for Digital Circuitry. –5 V for Inputs and Switch Matrix. +5 V for Inputs and Switch Matrix. Ground for Output Amp, xx = Output Channel Numbers 00 Through 07. Must be connected. +5 V for Output Amplifier that is shared by Channel Numbers xx and yy. Must be connected. –5 V for Output Amplifier that is shared by Channel Numbers xx and yy. Must be connected. Parallel Data Input, TTL Compatible (Output Select LSB). Parallel Data Input, TTL Compatible (Output Select). Parallel Data Input, TTL Compatible (Output Select MSB). Parallel Data Input, TTL Compatible (Input Select LSB). Parallel Data Input, TTL Compatible (Input Select). Parallel Data Input, TTL Compatible (Input Select). Parallel Data Input, TTL Compatible (Input Select MSB). Parallel Data Input, TTL Compatible (Output Enable). VCC VCC VCC ESD ESD ESD RESET OUTPUT INPUT ESD ESD 1kV (AD8111 ONLY) ESD AVEE AVEE DGND b. Analog Output a. Analog Input c. Reset Input VCC VCC 2kV ESD ESD OUTPUT INPUT ESD ESD DGND DGND d. Logic Input e. Logic Output Figure 5. I/O Schematics REV. 0 20kV –7– AD8110/AD8111 1 2 61 RESET 62 DGND 63 DVCC 64 IN00 66 IN01 65 AGND 67 AGND 68 IN02 69 AGND 70 IN03 71 AGND 73 AGND 72 IN04 74 IN05 75 AGND 77 AGND 76 IN06 78 IN07 80 DGND IN08 AGND 79 DVCC PIN CONFIGURATION 60 CE 59 DATA OUT PIN 1 IDENTIFIER IN09 3 58 CLK AGND 4 57 DATA IN IN10 5 AGND 6 56 UPDATE 55 SER/PAR IN11 7 AGND 8 IN12 9 54 A0 AD8110/AD8111 53 A1 16 3 8 80L TQFP (12mm 3 12mm) AGND 10 IN13 11 52 A2 51 D0 50 D1 TOP VIEW (PINS DOWN) AGND 12 IN14 13 49 D2 48 D3 0.5mm LEAD PITCH 47 D4 AGND 14 IN15 15 46 AGND AGND 16 45 AVEE AVEE 17 44 AVCC AVCC 18 43 AVCC00 AVCC07 19 42 AGND00 OUT07 20 –8– AVEE00/01 40 AGND01 39 OUT01 38 AVCC01/02 37 AGND02 36 OUT02 35 AVEE02/03 34 AGND03 33 OUT03 32 AGND04 30 AVCC03/04 31 OUT04 29 AVEE04/05 28 OUT05 26 AGND05 27 AVCC05/06 25 OUT06 23 AGND06 24 AGND07 21 AVEE06/07 22 41 OUT00 REV. 0 Typical Characteristics–AD8110/AD8111 5 RL = 150V 3 0.2 0.1 GAIN – dB 2 200mV p-p FLATNESS 1 0 0 –0.1 RL = 150V 50 25mV/DIV 0.3 FLATNESS – dB 4 GAIN 0 225 250 –0.2 –1 25 2V p-p –0.3 –2 25ns/DIV –3 100k 1M 10M FREQUENCY – Hz 100M 1G Figure 6. AD8110 Frequency Response Figure 9. AD8110 Step Response, 100 mV Step –30 RL = 1kV RL = 150V –40 1 0.5V/DIV CROSSTALK – dB –50 –60 ALL HOSTILE 0.5 0 20.5 –70 21 ADJACENT –80 25ns/DIV –90 –100 0.3 1 10 FREQUENCY – MHz 100 200 Figure 7. AD8110 Crosstalk vs. Frequency Figure 10. AD8110 Step Response, 2 V Step –40 2V STEP RL = 150V RL = 150V VOUT = 2V p-p –60 0.1%/DIV DISTORTION – dB –50 2ND HARMONIC –70 –80 3RD HARMONIC –90 –100 100k 0 1M 10M FREQUENCY – Hz 100M 20 30 40 50 10ns/DIV 60 70 80 Figure 11. AD8110 Settling Time Figure 8. AD8110 Distortion vs. Frequency REV. 0 10 –9– AD8110/AD8111–Typical Characteristics 0.8 0.4 2 0.2 200mV p-p FLATNESS GAIN – dB 1 0 50 25mV/DIV 3 FLATNESS – dB 0.6 –0.2 0 0 225 250 GAIN –1 25 –0.4 2V p-p –2 –3 100k 1M 10M FREQUENCY – Hz –0.6 100M 25ns/DIV 1G Figure 15. AD8111 Step Response, 100 mV Step Figure 12. AD8111 Frequency Response –20 RL = 1kV –30 1 –50 ADJACENT 500mV/DIV CROSSTALK – dB –40 –60 –70 –80 0.5 0 20.5 21 ALL HOSTILE –90 25ns/DIV –100 –110 0.3 1 10 FREQUENCY – MHz 100 200 Figure 16. AD8111 Step Response, 2 V Step Figure 13. AD8111 Crosstalk vs. Frequency 230 250 260 0.1%/DIV DISTORTION 2 dB 240 2V STEP RTO RL = 150V RL = 150V VOUT = 2V p-p 2ND HARMONIC 270 3RD HARMONIC 280 290 0 2100 100k 1M 10M FREQUENCY 2 Hz 10 20 30 40 50 10ns/DIV 60 70 80 100M Figure 17. AD8111 Settling Time Figure 14. AD8111 Distortion vs. Frequency –10– REV. 0 AD8110/AD8111 230 240 SWITCHING BETWEEN TWO INPUTS 5 4 1V/DIV 250 260 3 UPDATE INPUT 2 1 0 270 10mV/DIV POWER SUPPLY REJECTION 2 dB RL = 150V 280 290 10k 100k 1M FREQUENCY 2 Hz 10 0 TYPICAL VIDEO OUT (RTO) –10 50ns/DIV 10M Figure 18. AD8110 PSRR vs. Frequency Figure 21. AD8110 Switching Transient (Glitch) 100 –50 56.3 VIN = 2V p-p RL = 150V OFF ISOLATION – dB –60 nV Hz 31.6 17.8 10 –70 –80 –90 –100 –110 –120 5.63 –130 3.16 10 1k 100 100k 10k FREQUENCY 2 Hz 1M 10M 100k Figure 19. AD8110 Voltage Noise vs. Frequency 1M 10M FREQUENCY – Hz 100M 500M Figure 22. AD8110 Off Isolation, Input-Output 1M 10,000 OUTPUT IMPEDANCE – V OUTPUT IMPEDANCE 2 V 1000 100k 10k 1k 100 10 1 100 0.1 1 10 FREQUENCY 2 MHz 100 0.1 100k 500 Figure 20. AD8110 Output Impedance, Disabled REV. 0 1M 10M FREQUENCY – Hz 100M 500M Figure 23. AD8110 Output Impedance, Enabled –11– AD8110/AD8111 –30 SWITCHING BETWEEN TWO INPUTS 5 –40 1V/DIV 4 –50 3 2 UPDATE INPUT 1 0 –60 10mV/DIV POWER SUPPLY REJECTION – dB RTI RL = 150V –70 10 0 TYPICAL VIDEO OUT (RTO) –10 50ns/DIV –80 10k 100k 1M FREQUENCY – Hz 10M Figure 24. AD8111 PSRR vs. Frequency Figure 27. AD8111 Switching Transient (Glitch) 100 –40 –50 56.3 VOUT = 2V p-p RL = 150V OFF ISOLATION – dB –60 nV Hz 31.6 17.8 10 –70 –80 –90 –100 –110 5.63 –120 3.16 10 100 1k 10k 100k FREQUENCY 2 Hz 1M –130 100k 10M Figure 25. AD8111 Voltage Noise vs. Frequency 100M 500M 1k 10k OUTPUT IMPEDANCE 2 V OUTPUT IMPEDANCE 2 V 10M FREQUENCY – Hz Figure 28. AD8111 Off Isolation, Input-Output 100k 1k 100 10 0.1 1M 1 10 FREQUENCY 2 MHz 100 100 10 1 0.1 100k 500 Figure 26. AD8111 Output Impedance, Disabled. 1M 10M FREQUENCY 2 Hz 100M 500M Figure 29. AD8111 Output Impedance, Enabled –12– REV. 0 AD8110/AD8111 10M INPUT 1 AT +1V 1V/DIV 1 VOUT 0 –1 100k INPUT 0 AT –1V 5 2V/DIV INPUT IMPEDANCE – V 1M 10k UPDATE 0 1k 100 30k 50ns/DIV 100k 1M 10M FREQUENCY – Hz 100M 500M Figure 30. AD8110 Input Impedance vs. Frequency Figure 33. AD8110 Switching Time 14 12 260 VIN = 200mV p-p RL = 150V 240 220 10 200 8 180 FREQUENCY GAIN – dB 18pF = 7.7dB 6 4 12pF = 4.5dB 2 160 140 120 100 80 0 60 –2 40 20 –4 0.1M 1M 10M 100M 1G 0 –0.020 3G Figure 31. AD8110 Frequency Response vs. Capacitive Load Figure 34. AD8110 Offset Voltage Distribution 0.7 0.6 2.0 VIN = 200mV p-p RL = 150V 1.5 1.0 0.4 VOS – mV FLATNESS – dB 0.5 0.3 0.2 CL = 18pF 0.5 0 –0.5 0.1 –1.0 CL = 12pF 0 –1.5 –0.1 –0.2 0.1M 1M 10M 100M 1G –2.0 –60 3G FREQUENCY – Hz Figure 32. AD8110 Flatness vs. Capacitive Load REV. 0 0.020 –0.010 0.000 0.010 OFFSET VOLTAGE – Volts FREQUENCY – Hz –40 –20 0 20 40 TEMPERATURE – 8C 60 80 100 Figure 35. AD8110 Offset Voltage vs. Temperature (Normalized at +25 °C) –13– AD8110/AD8111 10M 1V/DIV 100k 1 INPUT 1 AT +1V –1 5 10k INPUT 0 AT –1V UPDATE 0 1k 100 30k VOUT 0 2V/DIV INPUT IMPEDANCE – V 1M 50ns/DIV 1M 10M FREQUENCY – Hz 100k 100M 500M Figure 36. AD8111 Input Impedance vs. Frequency Figure 39. AD8111 Switching Time 480 12 440 10 400 8 360 18pF 320 FREQUENCY GAIN – dB 6 4 2 12pF 280 240 200 0 160 120 –2 80 –4 –6 0.1M 40 1M 10M 100M 1G 0 –0.020 3G –0.010 0.000 0.010 OFFSET VOLTAGE – Volts FREQUENCY – Hz Figure 37. AD8111 Frequency Response vs. Capacitive Load Figure 40. AD8111 Offset Voltage Distribution (RTI) 0.7 0.6 0.020 2.0 VIN = 100mV RL = 150V 1.5 0.5 1.0 GAIN – dB 0.3 VOS – mV 0.4 18pF 0.2 0.1 0.5 0 –0.5 0 12pF –1.0 –0.1 –1.5 –0.2 –0.3 0.1M 1M 10M 100M 1G –2.0 –60 3G FREQUENCY – Hz –40 –20 0 20 40 TEMPERATURE – 8C 60 80 100 Figure 41. AD8111 Offset Voltage Drift vs. Temperature (Normalized at +25 °C) Figure 38. AD8111 Flatness vs. Capacitive Load –14– REV. 0 AD8110/AD8111 THEORY OF OPERATION: The AD8110 (G = +1) and AD8111 (G = +2) share a common core architecture consisting of an array of 128 transconductance (gm) input stages organized as eight 16:1 multiplexers with a common, 16-line analog input bus. Each multiplexer is basically a folded-cascode high speed voltage feedback amplifier with 16 input stages. The input stages are NPN differential pairs whose differential current outputs are combined at the output stage, which contains the high impedance node, compensation and a complementary emitter follower output buffer. In the AD8110, the output of each multiplexer is fed directly back to the inverting inputs of its 16 gm stages. In the AD8111, the feedback network is a voltage divider consisting of two equal resistors. This switched-gm architecture results in a low power crosspoint switch that is able to directly drive a back terminated video load (150 Ω) with low distortion (differential gain and differential phase errors are better than 0.02% and 0.02°, respectively). This design also achieves high input resistance and low input capacitance without the signal degradation and power dissipation of additional input buffers. However, the small input bias current at any input will increase almost linearly with the number of outputs programmed to that input. The output disable feature of these crosspoints allows larger switch matrices to be built simply by busing together the outputs of multiple 16 × 8 ICs. However, while the disabled output impedance of the AD8110 is very high (10 MΩ), that of the AD8111 is limited by the resistive feedback network (which has a nominal total resistance of 1 kΩ) that appears in parallel with the disabled output. If the outputs of multiple AD8111s are connected through separate back termination resistors, the loading due to these finite output impedances will lower the effective back termination impedance of the overall matrix. This problem is eliminated if the outputs of multiple AD8111s are connected directly and share a single back termination resistor for each output of the overall matrix. This configuration increases the capacitive loading of the disabled AD8111 on the output of the enabled AD8111. APPLICATIONS The AD8110/AD8111 have two options for changing the programming of the crosspoint matrix. In the first option a serial word of 40 bits can be provided that will update the entire matrix each time. The second option allows for changing a single output’s programming via a parallel interface. The serial option requires fewer signals, but requires more time (clock cycles) for changing the programming, while the parallel programming technique requires more signals, but can change a single output at a time and requires fewer clock cycles to complete programming. Serial Programming The serial programming mode uses the device pins CE, CLK, DATA IN, UPDATE, and SER/PAR. The first step is to assert a LOW on SER/PAR in order to enable the serial programming mode. CE for the chip must be LOW to allow data to be REV. 0 clocked into the device. The CE signal can be used to address an individual device when devices are connected in parallel. The UPDATE signal should be HIGH during the time that data is shifted into the device’s serial port. Although the data will still shift in when UPDATE is LOW, the transparent, asynchronous latches will allow the shifting data to reach the matrix. This will cause the matrix to try to update to every intermediate state as defined by the shifting data. The data at DATA IN is clocked in at every down edge of CLK. A total of 40 data bits must be shifted in to complete the programming. For each of the eight outputs, there are four bits (D0–D3) that determine the source of its input followed, by one bit (D4) that determines the enabled state of the output. If D4 is LOW (output disabled) the four associated bits (D0–D3) do not matter, because no input will be switched to that output. The most-significant-output-address data is shifted in first, then following in sequence until the least-significant-output-address data is shifted in. At this point UPDATE can be taken LOW, which will cause the programming of the device according to the data that was just shifted in. The UPDATE registers are asynchronous and when UPDATE is LOW (and CE is LOW), they are transparent. If more than one AD8110/AD8111 device is to be serially programmed in a system, the DATA OUT signal from one device can be connected to the DATA IN of the next device to form a serial chain. All of the CLK, CE, UPDATE and SER/PAR pins should be connected in parallel and operated as described above. The serial data is input to the DATA IN pin of the first device of the chain, and it will ripple on through to the last. Therefore, the data for the last device in the chain should come at the beginning of the programming sequence. The length of the programming sequence will be 40 times the number of devices in the chain. Parallel Programming When using the parallel programming mode, it is not necessary to reprogram the entire device when making changes to the matrix. In fact, parallel programming allows the modification of a single output at a time. Since this takes only one CLK/ UPDATE cycle, significant time savings can be realized by using parallel programming. One important consideration in using parallel programming is that the RESET signal DOES NOT RESET ALL REGISTERS in the AD8110/AD8111. When taken low, the RESET signal will only set each output to the disabled state. This is helpful during power-up to ensure that two parallel outputs will not be active at the same time. After initial power-up, the internal registers in the device will generally have random data, even though the RESET signal was asserted. If parallel programming is used to program one output, that output will be properly programmed, but the rest of the device will have a random program state depending on the internal register content at power-up. Therefore, when using parallel programming, it is essential that ALL OUTPUTS BE PROGRAMMED TO A DESIRED STATE AFTER POWER-UP. –15– AD8110/AD8111 This will ensure that the programming matrix is always in a known state. From then on, parallel programming can be used to modify a single output or more at a time. cause all the outputs to be disabled. The capacitor will then charge through the pull-up resistor to the HIGH state; thus allowing full programming capability of the device. In a similar fashion, if both CE and UPDATE are taken LOW after initial power-up, the random power-up data in the shift register will be programmed into the matrix. Therefore, in order to prevent the crosspoint from being programmed into an unknown state DO NOT APPLY LOW LOGIC LEVELS TO BOTH CE AND UPDATE AFTER POWER IS INITIALLY APPLIED. Programming the full shift register one time to a desired state by either serial or parallel programming after initial power-up will eliminate the possibility of programming the matrix to an unknown state. GAIN SELECTION The 16 × 8 crosspoints come in two versions depending on the desired gain of the analog circuit paths. The AD8110 device is unity gain and can be used for analog logic switching and other applications where unity gain is desired. The AD8110 can also be used for the input and interior sections of larger crosspoint arrays where termination of output signals is not usually used. The AD8110 outputs have a very high impedance when their outputs are disabled. To change an output’s programming via parallel programming, SER/PAR and UPDATE should be taken HIGH and CE should be taken LOW. The CLK signal should be in the HIGH state. The address of the output that is to be programmed should be put on A0–A2. The first four data bits (D0–D3) should contain the information that identifies the input that is programmed to the output that is addressed. The fourth data bit (D4) will determine the enabled state of the output. If D4 is LOW (output disabled), the data on D0–D3 does not matter. For devices that will be used to drive a terminated cable with its outputs, the AD8111 can be used. This device has a built-in gain of two that eliminates the need for a gain-of-two buffer to drive a video line. Because of the presence of the feedback network in these devices, the disabled output impedance is about 1 kΩ. After the desired address and data signals have been established, they can be latched into the shift register by a HIGH-to-LOW transition of the CLK signal. The matrix will not be programmed, however, until the UPDATE signal is taken low. Thus, it is possible to latch in new data for several or all of the outputs first via successive negative transitions of CLK while UPDATE is held high, and then have all the new data take effect when UPDATE goes LOW. This technique should be used when programming the device for the first time after power-up when using parallel programming. CREATING LARGER CROSSPOINT ARRAYS If external amplifiers are used to provide a gain = +2, our AD8079 provides a fixed G = +2 function. The AD8110/AD8111 are high density building blocks for creating crosspoint arrays of dimensions larger than 16 × 8. Various features such as output disable, chip enable, and gain-of-oneand-two options are useful for creating larger arrays. For very large arrays, they can be used along with the AD8116, a 16 × 16 video crosspoint device. In addition, when required for customizing a crosspoint array size, they can be used with the AD8108 and AD8109 a pair (unity gain and gain-of-two) of 8 × 8 video crosspoint switches. The first consideration in constructing a larger crosspoint is to determine the minimum number of devices that are required. The 16 × 8 architecture of the AD8110/AD8111 contains 128 “points,” which is a factor of 32 greater than a 4 × 1 crosspoint. The PC board area and power consumption savings are readily apparent when compared to using these smaller devices. POWER-ON RESET When powering up the AD8110/AD8111 it is usually desirable to have the outputs come up in the disabled state. The RESET pin, when taken LOW will cause all outputs to be in the disabled state. However, the RESET signal DOES NOT RESET ALL REGISTERS in the AD8110/AD8111 This is important when operating in the parallel programming mode. Please refer to that section for information about programming internal registers after power-up. Serial programming will program the entire matrix each time, so no special considerations apply. For a nonblocking crosspoint, the number of points required is the product of the number of inputs multiplied by the number of outputs. Nonblocking requires that the programming of a given input to one or more outputs does not restrict the availability of that input to be a source for any other outputs. Since the data in the shift register is random after power-up, it should not be used to program the matrix or else the matrix can enter unknown states. To prevent this, DO NOT APPLY LOGIC LOW SIGNALS TO BOTH CE AND UPDATE INITIALLY AFTER POWER-UP. The shift register should first be loaded with the desired data, and then UPDATE can be taken LOW to program the device. Some nonblocking crosspoint architectures will require more than this minimum as calculated above. Also, there are blocking architectures that can be constructed with fewer devices than this minimum. These systems have connectivity available on a statistical basis that is determined when designing the overall system. The RESET pin has a 20 kΩ pull-up resistor to DVDD that can be used to create a simple power-up reset circuit. A capacitor from RESET to ground will hold RESET LOW for some time while the rest of the device stabilizes. The LOW condition will –16– REV. 0 AD8110/AD8111 The basic concept in constructing larger crosspoint arrays is to connect inputs in parallel in a horizontal direction and to “wireOR” the outputs together in the vertical direction. The meaning of horizontal and vertical can best be understood by looking at a diagram. Figure 42 illustrates this concept for a 32 × 8 crosspoint array. IN 00–15 16 16 At some point, the number of outputs that are wire-ORed becomes too great to maintain system performance. This will vary according to which system specifications are most important. It will also depend on whether the matrix consists of AD8110s or AD8111s. The output disabled impedance of the AD8110 is much higher than that of the AD8111, so its disabled parasitics will have a smaller effect on the one output that is enabled. For example, a 128 × 8 crosspoint can be created with eight AD8110/ AD8111s. This design will have 128 separate inputs and have the corresponding outputs of each device wire-ORed together in groups of eight. AD8110 OR AD8111 RTERM 8 IN 16–31 16 16 Using additional crosspoint devices in the design can lower the number of outputs that have to be wire-ORed together. Figure 43 shows a block diagram of a system using eight AD8110s and two AD8111s to create a nonblocking, gain-of-two, 128 × 8 crosspoint that restricts the wire-ORing at the output to only four outputs. These devices are the AD8110, which has a higher disabled output impedance than the AD8111. AD8110 OR AD8111 RTERM 8 Figure 42. A 32 × 8 Crosspoint Array Using Two AD8110s or Two AD8111s Additionally, by using the lower four outputs from each of the two Rank 2 AD8111s, a blocking 128 × 16 crosspoint array can be realized. There are, however, some drawbacks to this technique. The offset voltages of the various cascaded devices will accumulate and the bandwidth limitations of the devices will compound. In addition, the extra devices will consume more current and take up more board space. Once again, the overall system design specifications will determine how to make the various tradeoffs. The inputs are each uniquely assigned to each of the 32 inputs of the two devices and terminated appropriately. The outputs are wire-ORed together in pairs. The output from only one of a wired OR pair should be enabled at any given time. The device programming software must be properly written to cause this to happen. RANK 1 (8 x AD8110) 128:16 4 IN 00–15 AD8110 16 4 RTERM 4 IN 16–31 AD8110 16 4 RTERM 4 IN 32–47 AD8110 16 4 RANK 2 16:8 NONBLOCKING (16:16 BLOCKING) RTERM 4 4 IN 48–63 AD8110 16 4 4 1kV RTERM 4 IN 64–79 AD8110 16 4 AD8110 16 4 OUT 00 – 07 NONBLOCKING 4 1kV 4 RTERM IN 80–95 AD8111 4 1kV 4 AD8111 4 4 ADDITIONAL 8 OUTPUTS (SUBJECT TO BLOCKING) 4 1kV RTERM 4 IN 96–111 AD8110 16 4 RTERM 4 IN 112–127 AD8110 16 4 RTERM Figure 43. A Gain-of-Two 128 × 8 Nonblocking Crosspoint Array (128 × 16 Blocking) REV. 0 –17– AD8110/AD8111 Multichannel Video CROSSTALK The excellent video specifications of the AD8110/AD8111 make them ideal candidates for creating composite video crosspoint switches. These can be made quite dense by taking advantage of the AD8110/AD8111’s high level of integration and the fact that composite video requires only one crosspoint channel per system video channel. There are, however, other video formats that can be routed with the AD8110/AD8111 requiring more than one crosspoint channel per video channel. Many systems, such as broadcast video, that handle numerous analog signal channels have strict requirements for keeping the various signals from influencing any of the others in the system. Crosstalk is the term used to describe the coupling of the signals of other nearby channels to a given channel. Some systems use twisted-pair wiring to carry video signals. These systems utilize differential signals and can lower costs because they use lower cost cables, connectors and termination methods. They also have the ability to lower crosstalk and reject common-mode signals, which can be important for equipment that operates in noisy environments or where common-mode voltages are present between transmitting and receiving equipment. When there are many signals in close proximity in a system, as will undoubtedly be the case in a system that uses the AD8110/ AD8111, the crosstalk issues can be quite complex. A good understanding of the nature of crosstalk and some definition of terms is required in order to specify a system that uses one or more AD8110/AD8111s. Types of Crosstalk Crosstalk can be propagated by means of any of three methods. These fall into the categories of electric field, magnetic field and sharing of common impedances. This section will explain these effects. In such systems, the video signals are differential; there is a positive and negative (or inverted) version of the signals. These complementary signals are transmitted onto each of the two wires of the twisted pair, yielding a first order zero commonmode signal. At the receive end, the signals are differentially received and converted back into a single-ended signal. Every conductor can be both a radiator of electric fields and a receiver of electric fields. The electric field crosstalk mechanism occurs when the electric field created by the transmitter propagates across a stray capacitance (e.g., free space) and couples with the receiver and induces a voltage. This voltage is an unwanted crosstalk signal in any channel that receives it. When switching these differential signals, two channels are required in the switching element to handle the two differential signals that make up the video channel. Thus, one differential video channel is assigned to a pair of crosspoint channels, both input and output. For a single AD8110/AD8111, eight differential video channels can be assigned to the 16 inputs and four to the outputs. This will effectively form an 8 × 4 differential crosspoint switch. Currents flowing in conductors create magnetic fields that circulate around the currents. These magnetic fields will then generate voltages in any other conductors whose paths they link. The undesired induced voltages in these other channels are crosstalk signals. The channels that crosstalk can be said to have a mutual inductance that couples signals from one channel to another. Programming such a device will require that inputs and outputs be programmed in pairs. This information can be deduced by inspection of the programming format of the AD8110/AD8111 and the requirements of the system. There are other analog video formats requiring more than one analog circuit per video channel. One two-circuit format that is commonly being used in systems such as satellite TV, digital cable boxes and higher quality VCRs, is called S-video or Y/C video. This format carries the brightness (luminance or Y) portion of the video signal on one channel and the color (chrominance, chroma or C) on a second channel. All these sources of crosstalk are vector quantities, so the magnitudes cannot be simply added together to obtain the total crosstalk. In fact, there are conditions where driving additional circuits in parallel in a given configuration can actually reduce the crosstalk. Areas of Crosstalk Since S-video also uses two separate circuits for one video channel, creating a crosspoint system requires assigning one video channel to two crosspoint channels as in the case of a differential video system. Aside from the nature of the video format, other aspects of these two systems will be the same. There are yet other video formats using three channels to carry the video information. Video cameras produce RGB (red, green, blue) directly from the image sensors. RGB is also the usual format used by computers internally for graphics. RGB can also be converted to Y, R-Y, B-Y format, sometimes called YUV format. These three-circuit, video standards are referred to as component analog video. The component video standards require three crosspoint channels per video channel to handle the switching function. In a fashion similar to the two-circuit video formats, the inputs and outputs are assigned in groups of three and the appropriate logic programming is performed to route the video signals. The power supplies, grounds and other signal return paths of a multichannel system are generally shared by the various channels. When a current from one channel flows in one of these paths, a voltage that is developed across the impedance becomes an input crosstalk signal for other channels that share the common impedance. For a practical AD8110/AD8111 circuit, it is required that it be mounted to some sort of circuit board in order to connect it to power supplies and measurement equipment. Great care has been taken to create a characterization board (also available as an evaluation board) that adds minimum crosstalk to the intrinsic device. This, however, raises the issue that a system’s crosstalk is a combination of the intrinsic crosstalk of the devices in addition to the circuit board to which they are mounted. It is important to try to separate these two areas of crosstalk when attempting to minimize its effect. In addition, crosstalk can occur among the inputs to a crosspoint and among the outputs. It can also occur from input to output. Techniques will be discussed for diagnosing which part of a system is contributing to crosstalk. –18– REV. 0 AD8110/AD8111 Measuring Crosstalk Input and Output Crosstalk Crosstalk is measured by applying a signal to one or more channels and measuring the relative strength of that signal on a desired selected channel. The measurement is usually expressed as dB down from the magnitude of the test signal. The crosstalk is expressed by: The flexible programming capability of the AD8110/AD8111 can be used to diagnose whether crosstalk is occurring more on the input side or the output side. Some examples are illustrative. A given input channel (IN07 in the middle for this example) can be programmed to drive OUT03. The input to IN07 is just terminated to ground (via 50 or 75 Ω) and no signal is applied. |XT| = 20 log 10 (Asel(s)/Atest(s)) where s = jω is the Laplace transform variable, Asel(s) is the amplitude of the crosstalk-induced signal in the selected channel and Atest(s) is the amplitude of the test signal. It can be seen that crosstalk is a function of frequency, but not a function of the magnitude of the test signal (to first order). In addition, the crosstalk signal will have a phase relative to the test signal associated with it. A network analyzer is most commonly used to measure crosstalk over a frequency range of interest. It can provide both magnitude and phase information about the crosstalk signal. As a crosspoint system or device grows larger, the number of theoretical crosstalk combinations and permutations can become extremely large. For example, in the case of the 16 × 8 matrix of the AD8110/AD8111, we can examine the number of crosstalk terms that can be considered for a single channel, say IN00 input. IN00 is programmed to connect to one of the AD8110/AD8111 outputs where the measurement can be made. For output crosstalk measurement, a single input channel (IN00 for example) is driven and all outputs other than a given output (IN03 in the middle) are programmed to connect to IN00. OUT03 is programmed to connect to IN15 (far away from IN00), which is terminated to ground. Thus OUT03 should not have a signal present since it is listening to a quiet input. Any signal measured at the OUT03 can be attributed to the output crosstalk of the other seven hostile outputs. Again, this method can be modified to measure other channels and other crosspoint matrix combinations. We can first measure the crosstalk terms associated with driving a test signal into each of the other 15 inputs one at a time. We can then measure the crosstalk terms associated with driving a parallel test signal into all 15 other inputs taken two at a time in all possible combinations; and then three at a time, etc., until, finally, there is only one way to drive a test signal into all 15 other inputs. Effect of Impedances on Crosstalk Each of these cases is legitimately different from the others and might yield a unique value depending on the resolution of the measurement system, but it is hardly practical to measure all these terms and then to specify them. In addition, this describes the crosstalk matrix for just one input channel. A similar crosstalk matrix can be proposed for every other input. In addition, if the possible combinations and permutations for connecting inputs to the other (not used for measurement) outputs are taken into consideration, the numbers rather quickly grow to astronomical proportions. If a larger crosspoint array of multiple AD8110/ AD8111s is constructed, the numbers grow larger still. Obviously, some subset of all these cases must be selected to be used as a guide for a practical measure of crosstalk. One common method is to measure “all hostile” crosstalk. This term means that the crosstalk to the selected channel is measured, while all other system channels are driven in parallel. In general, this will yield the worst crosstalk number, but this is not always the case due to the vector nature of the crosstalk signal. Other useful crosstalk measurements are those created by one nearest neighbor or by the two nearest neighbors on either side. These crosstalk measurements will generally be higher than those of more distant channels, so they can serve as a worst case measure for any other one-channel or two-channel crosstalk measurements. REV. 0 All the other inputs are driven in parallel with the same test signal (practically provided by a distribution amplifier), with all other outputs except OUT03 disabled. Since grounded IN07 is programmed to drive OUT03, there should be no signal present. Any signal that is present can be attributed to the other 15 hostile input signals, because no other outputs are driven (they are all disabled). Thus, this method measures the all-hostile input contribution to crosstalk into IN07. Of course, the method can be used for other input channels and combinations of hostile inputs. The input side crosstalk can be influenced by the output impedance of the sources that drive the inputs. The lower the impedance of the drive source, the lower the magnitude of the crosstalk. The dominant crosstalk mechanism on the input side is capacitive coupling. The high impedance inputs do not have significant current flow to create magnetically induced crosstalk. However, significant current can flow through the input termination resistors and the loops that drive them. Thus, the PC board on the input side can contribute to magnetically coupled crosstalk. From a circuit standpoint, the input crosstalk mechanism looks like a capacitor coupling to a resistive load. For low frequencies the magnitude of the crosstalk will be given by: |XT| = 20 log10 [(RS CM) × s] where RS is the source resistance, CM is the mutual capacitance between the test signal circuit and the selected circuit, and s is the Laplace transform variable. From the equation it can be observed that this crosstalk mechanism has a high pass nature; it can also be minimized by reducing the coupling capacitance of the input circuits and lowering the output impedance of the drivers. If the input is driven from a 75 Ω terminated cable, the input crosstalk can be reduced by buffering this signal with a low output impedance buffer. –19– AD8110/AD8111 On the output side, the crosstalk can be reduced by driving a lighter load. Although the AD8110/AD8111 is specified with excellent differential gain and phase when driving a standard 150 Ω video load, the crosstalk will be higher than the minimum obtainable due to the high output currents. These currents will induce crosstalk via the mutual inductance of the output pins and bond wires of the AD8110/AD8111. From a circuit standpoint, this output crosstalk mechanism looks like a transformer with a mutual inductance between the windings that drives a load resistor. For low frequencies, the magnitude of the crosstalk is given by: The input and output signals will have minimum crosstalk if they are located between ground planes on layers above and below, and separated by ground in between. Vias should be located as close to the IC as possible to carry the inputs and outputs to the inner layer. The only place the input and output signals surface is at the input termination resistors and the output series back termination resistors. These signals should also be separated, to the extent possible, as soon as they emerge from the IC package. Evaluation Board A four-layer evaluation board is available for the AD8110/AD8111. The exact same board and external components are used for each device. The only difference is the device itself, which offers a selection of a gain of unity or gain of two through the analog channels. This board has been carefully laid out and tested to demonstrate the specified high speed performance of the device. Figure 44 shows the schematic of the evaluation board. Figure 45 shows the component side silk-screen. The layouts of the board’s four layers are given in: |XT| = 20 log10 (Mxy × s/R L) where Mxy is the mutual inductance of output x to output y, and R L is the load resistance on the measured output. This crosstalk mechanism can be minimized by keeping the mutual inductance low and increasing RL. The mutual inductance can be kept low by increasing the spacing of the conductors and minimizing their parallel length. PCB Layout Extreme care must be exercised to minimize additional crosstalk generated by the system circuit board(s). The areas that must be carefully detailed are grounding, shielding, signal routing and supply bypassing. The packaging of the AD8110/AD8111 is designed to help keep the crosstalk to a minimum. Each input is separated from each other input by an analog ground pin. All of these AGNDs should be directly connected to the ground plane of the circuit board. These ground pins provide shielding, low impedance return paths and physical separation for the inputs. All of these help to reduce crosstalk. Each output is separated from its two neighboring outputs by an analog ground pin in addition to an analog supply pin of one polarity or the other. Each of these analog supply pins provides power to the output stages of only the two nearest outputs. These supply pins and analog grounds provide shielding, physical separation and a low impedance supply for the outputs. Individual bypassing of each of these supply pins with a 0.01 µF chip capacitor directly to the ground plane minimizes high frequency output crosstalk via the mechanism of sharing common impedances. Component Layer—Figure 46 Signal Routing Layer—Figure 47 Power Layer—Figure 48 Bottom Layer—Figure 49 The evaluation board package includes the following: • Fully populated board with BNC-type connectors. • Windows™ based software for controlling the board from a PC via the printer port. • Custom cable to connect evaluation board to PC. • Disk containing Gerber files of board layout. Optimized for video applications, all signal inputs and outputs are terminated with 75 Ω resistors. Stripline techniques are used to achieve a characteristic impedance on the signal input and output lines also of 75 Ω. Figure 50 shows a cross-section of one of the input or output tracks along with the arrangement of the PCB layers. It should be noted that unused regions of the four layers are filled up with ground planes. As a result, the input and output traces, in addition to having controlled impedances, are well shielded. Each output also has an on-chip compensation capacitor that is individually tied to the nearby analog ground pins AGND00 through AGND07. This technique reduces crosstalk by preventing the currents that flow in these paths from sharing a common impedance on the IC and in the package pins. These AGNDxx signals should all be directly connected to the ground plane. All trademarks are properties of their respective holders. –20– REV. 0 AD8110/AD8111 DVCC DGND P1-1 P1-2 + NC P1-3 AVEE AGND AVCC P1-4 P1-5 NC P1-7 P1-6 + CR1 CR2 DVCC + 0.1mF 10mF DVCC 0.01mF 0.1mF 10mF 0.1mF 10mF 79 AVCC 0.01mF 63 AVCC 0.01mF AVEE 0.01mF 0.01mF 43 44 45 AVCC AVCC AVEE 75V 64 INPUT 00 65 AGND 75V 66 INPUT 01 67 AGND 75V 68 INPUT 02 69 AGND 75V 70 INPUT 03 71 AGND 75V 72 INPUT 04 73 AGND OUTPUT 02 75V 74 INPUT 05 75 AGND AGND 75V 76 INPUT 06 77 AGND INPUT 00 INPUT 01 AGND AGND OUTPUT 00 AVEE INPUT 02 INPUT 03 INPUT 04 INPUT 05 INPUT 06 78 INPUT 07 AGND OUTPUT 01 AVCC AGND AVEE OUTPUT 03 INPUT 07 AD8110 AD8111 75V 75V 1 INPUT 08 2 AGND 75V 3 INPUT 09 4 AGND 75V 5 INPUT 10 6 AGND 75V 7 INPUT 11 8 AGND INPUT 08 AVCC AGND OUTPUT 04 INPUT 09 INPUT 10 INPUT 11 75V 9 INPUT 12 10 AGND 75V 11 INPUT 13 12 AGND 75V 13 INPUT 14 14 AGND 75V 15 INPUT 15 16 AGND INPUT 12 INPUT 13 AVEE AGND OUTPUT 05 AVCC AGND OUTPUT 06 AVEE AGND P2-2 DATA IN AVEE 40 39 38 AVEE 0.01mF 75V 37 36 35 AVCC 0.01mF 75V 34 33 32 AVEE 0.01mF 75V 31 30 29 AVCC 0.01mF 75V 28 27 26 AVEE 0.01mF 75V 25 24 23 AVCC 0.01mF 75V 22 21 20 AVEE 0.01mF 75V 19 AVCC 18 AVCC 17 AVEE D4 D3 D2 D1 D0 A2 A1 62 61 60 58 56 55 54 53 52 51 50 49 48 47 P2-3 R25 20kV P2-1 DVCC P2-6 –21– P2-4 P2-5 P2-6 P2-1 P2-3 P2-2 P2-4 P2-5 P2-6 P2-1 P2-3 P2-2 P2-4 P2-5 SERIAL MODE JUMP Figure 44. Evaluation Board Schematic REV. 0 75V 0.01mF A0 DGND SER/PAR P2-4 80 41 0.01mF UPDATE P2-5 AVCC DATA OUT CLK 59 42 0.01mF CE 59 AVCC RESET INPUT 15 OUTPUT 07 DGND INPUT 14 46 AD8110/AD8111 Figure 45. Component Side Silkscreen Figure 46. Board Layout (Component Side) –22– REV. 0 AD8110/AD8111 Figure 47. Board Layout (Signal Layer) Figure 48. Board Layout (Power Plane) REV. 0 –23– AD8110/AD8111 Figure 49. Board Layout (Bottom Layer) –24– REV. 0 AD8110/AD8111 w = 0.008" (0.2mm) TOP LAYER b = 0.024" (0.6mm) a = 0.008" (0.2mm) t = 0.00135" (0.0343mm) SIGNAL LAYER h = 0.011325" (0.288mm) POWER LAYER BOTTOM LAYER Controlling the Evaluation Board from a PC Figure 50. Cross Section of Input and Output Traces The evaluation board include Windows-based control software and a custom cable that connects the board’s digital interface to the printer port of the PC. The wiring of this cable is shown in Figure 51. The software requires Windows 3.1 or later to operate. To install the software, insert the disk labeled “Disk #1 of 2” in the PC and run the file called SETUP.EXE. Additional installation instructions will be given on-screen. Before beginning installation, it is important to terminate any other Windows applications that are running. The board has 24 BNC type connectors: 16 inputs and 8 outputs. The connectors are arranged in a crescent around the device. As can be seen from Figure 47, this results in all 16 input signal traces and all eight signal output traces having the same length. This is useful in tests such as All-Hostile Crosstalk where the phase relationship and delay between signals needs to be maintained from input to output. The three power supply pins AVCC, DVCC and AVEE should be connected to good quality, low noise, ±5 V supplies. Where the same ± 5 V power supplies are used for analog and digital, separate cables should be run for the power supply to the evaluation board’s analog and digital power supply pins. RESET As a general rule, each power supply pin (or group of adjacent power supply pins) should be locally decoupled with a 0.01 µF capacitor. If there is a space constraint, it is more important to decouple analog power supply pins before digital power supply pins. A 0.1 µF capacitor, located reasonably close to the pins, can be used to decouple a number of power supply pins. Finally a 10 µF capacitor should be used to decouple power supplies as they come on to the board. When you launch the crosspoint control software, you will be asked to select the printer port you are using. Most modern PCs have only one printer port, usually called LPT1. However some laptop computers use the PRN port. MOLEX 0.100" CENTER CRIMP TERMINAL HOUSING D-SUB 25 PIN (MALE) 14 1 1 CLK CE UPDATE DATA IN 6 DGND MOLEX D-SUB-25 TERMINAL HOUSING 2 3 3 1 4 4 5 5 6 2 6 25 SIGNAL CE RESET UPDATE 25 13 DATA IN CLK DGND EVALUATION BOARD PC Figure 51. Evaluation Board-PC Connection Cable REV. 0 –25– AD8110/AD8111 Figure 52 shows the main screen of the control software in its initial reset state (all outputs off). Using the mouse, any input can be connected with one or more outputs by simply clicking on the appropriate radio buttons in the 16 × 8 on-screen array. Each time a button is clicked on, the software automatically sends and latches the required 40-bit data stream to the evaluation board. An output can be turned off by clicking the appropriate button in the Off column. To turn off all outputs, click on RESET. The software offers volatile and nonvolatile storage of configurations. For volatile storage, up to two configurations can be stored and recalled using the Memory 1 and Memory 2 Buffers. These function in an identical fashion to the memory on a pocket calculator. For nonvolatile storage of a configuration, the Save Setup and Load Setup functions can be used. This stores the configuration as a data file on disk. Overshoot on PC Printer Ports’ Data Lines The data lines on some printer ports have excessive overshoot. Overshoot on the pin that is used as the serial clock (Pin 6 on the D-Sub-25 connector) can cause communication problems. This overshoot can be eliminated by connecting a capacitor from the CLK line on the evaluation board to ground. A pad has been provided on the solder-side of the evaluation board to allow this capacitor to be soldered into place. Depending upon the overshoot from the printer port, this capacitor may need to be as large as 0.01 µF. Figure 52. Evaluation Board Control Panel –26– REV. 0 AD8110/AD8111 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 80-Lead Plastic TQFP (ST-80A) 0.559 (14.20) 0.543 (13.80) 0.476 (12.10) 0.469 (11.90) 0.063 (1.60) MAX 0.030 (0.75) 0.020 (0.50) 80 1 61 60 0.476 (12.10) 0.469 (11.90) 0.559 (14.20) 0.543 (13.80) SEATING PLANE TOP VIEW (PINS DOWN) 0.003 (0.08) MAX 0.006 (0.15) 0.002 (0.05) 20 41 40 21 0.020 (0.50) BSC 0.057 (1.45) 0.053 (1.35) REV. 0 –27– 0.011 (0.27) 0.007 (0.17) –28– PRINTED IN U.S.A. C3221–8–10/97