a FEATURES 1.5 ns Rise/2.0 ns Fall Times Output Current: 180 mA @ 3 V, 200 mA @ 2.5 V Bias Current: 90 mA @ 3 V Modulation Current: 60 mA @ 3 V Offset Current: 30 mA @ 3 V Single +5 V Power Supply Switching Rate: 200 MHz Onboard Light Power Control Loops APPLICATIONS Laser Printers and Copiers Optical Disk Drives FO Datacomm GENERAL DESCRIPTION The AD9660 is a highly integrated driver for laser diode applications such as optical disk drives, printers, and copiers. The AD9660 gets feedback from an external photo detector and includes two analog feedback loops to allow users to set “bias” and “write” (for optical disk drives) power levels of the laser, and switch between the two power levels at up to 200 MHz. Output rise and fall times are typically 1.5 ns and 2.0 ns to complement printer applications that use image enhancing techniques such as pulse width modulation to achieve gray scale, and allow disk drive applications to improve density and take advantage of pulsed write formats. Control signals are TTL/ CMOS compatible. 200 MHz Laser Diode Driver with Light Power Control AD9660 FUNCTIONAL BLOCK DIAGRAM WRITE PULSE WRITE CALIBRATE WRITE LEVEL T/H OUTPUT DRIVER V:1 TRANSIMPEDANCE AMPLIFIER BIAS LEVEL BIAS CAL BIAS T/H V:1 OUTPUT DRIVER OUTPUT SENSE INPUT LASER DIODE PHOTO DETECTOR DIODE AD9660 The driver output provides up to 180 mA of current @ 3 V, 90 mA of BIAS current, 60 mA of modulation current, and 30 mA of offset current. The onboard disable circuit turns off the output drivers and returns the light power control loops to a safe state. The AD9660 can also be used in closed loop applications in which the output power level follows an analog WRITE LEVEL voltage input. By optimizing the external hold capacitor, and the photo detector, the write loop can achieve bandwidths as high as 25 MHz. The AD9660 is offered in a 28-pin plastic SOIC for operation over the commercial temperature range (0°C to +70°C). REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. © Analog Devices, Inc., 1995 One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 (+VS = +5 V, Temperature = +25°C unless otherwise noted. Sourced currents defined AD9660–SPECIFICATIONS as positive.) Parameter Test Level Temp Min AD9660KR Typ Max ANALOG INPUTS (WRITE LEVEL, BIAS LEVEL) Input Voltage Range Input Bias Current Analog Bandwidth IV I V Full +25°C Full VREF –50 OUTPUTS Maximum Output Current, IOUT IOUT Bias Current, IBIAS Modulation Current, IMODULATION Offset Current, IOFFSET Output Compliance Range Idle Current I I I I I I I +25°C +25°C +25°C +25°C +25°C +25°C +25°C 200 180 90 60 30 0 3 SWITCHING PERFORMANCE Maximum Pulse Rate Output Propagation Delay (tPD), Rising1 Output Propagation Delay (tPD), Falling1 Output Current Rise Time2 Output Current Fall Time3 WRITE CAL Aperture Delay4 Disable Time5 IV IV IV IV IV V V +25°C Full Full Full Full +25°C +25°C 200 1.6 1.6 1.1 1.4 HOLD NODES (WRITE HOLD, BIAS HOLD) Input Bias Current Input Voltage Range Minimum External Hold Cap I IV V +25°C Full Full –200 VREF TTL INPUTS6 Logic “1” Voltage Logic “1” Voltage Logic “0” Voltage Logic “0” Voltage Logic “1” Current Logic “0” Current I IV I IV I I +25°C Full +25°C Full +25°C +25°C 2.0 2.0 –10 –1.5 20 BANDGAP REFERENCE Output Voltage VREF Temperature Coefficient Output Current I V V +25°C 1.55 1.75 –0.2 +25°C –0.5 SENSE IN Current Gain Voltage Input Resistance V I V +25°C +25°C +25°C 3.7 POWER SUPPLY (DISABLE = HIGH) +VS Voltage +VS Current Power Dissipation I I I +25°C +25°C +25°C 4.75 75 5.00 110 550 5.25 150 V mA mW DISABLE = HIGH OFFSET CURRENT OFFSET SET Voltage I +25°C 1.1 1.4 1.7 V IMONITOR = 4.0 mA VREF + 1.6 +50 25 3.0 13 250 1.5 2.0 13 5 20 3.0 2.5 1.7 2.8 Conditions V µA MHz External Hold Cap = 20 pF mA mA mA mA mA V mA VOUT = 2.5 V VOUT = 3.0 V VOUT = 3.0 V VOUT = 3.0 V VOUT = 3.0 V MHz ns ns ns ns ns ns 3 dB Reduction in IOUT 200 nA VREF + 1.6 V pF 0.8 0.8 10 1.90 1.0 1.85 4.0 <150 Units 4.3 V V V V µA mA WRITE PULSE = LOW, DISABLE = HIGH VHOLD = 2.5 V Open Loop Application Only DISABLE = LOW While Other TTL Inputs Are Tested V mV/°C mA mA/mA V Ω IMONITOR = 2 mA NOTES 1 Propagation delay measured from the 50% of the rising/falling transition of WRITE PULSE to 50% point of the rising/falling edge of the output modulation current. 2 Rise time measured between the 10% and 90% points of the rising transition of the modulation current. 3 Fall time measured between the 10% and 90% points of the falling transition of the modulation current. 4 Aperture Delay is measured from the 50% point of the rising edge of WRITE PULSE to the time when the output modulation begins to recalibrate, WRITE CAL is held during this test. 5 Disable Time is measured from the 50% point of the rising edge of DISABLE to the 50% point of the falling transition of the output current. Fall time during disable is similar to fall time during normal operation. 6 WRITE PULSE, WRITE CAL, BIAS CAL, OFFSET PULSE are TTL compatible inputs. Specifications subject to change without notice. –2– REV. 0 AD9660 ABSOLUTE MAXIMUM RATINGS 1 EXPLANATION OF TEST LEVELS Test Level +VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V VREF Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 mA WRITE LEVEL, BIAS LEVEL . . . . . . . . . . . . . –0.5 V to +VS TTL INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +VS Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 mA Operating Temperature AD9660KR . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Maximum Junction Temperature2 . . . . . . . . . . . . . . . . +150°C Lead Soldering Temp (10 sec) . . . . . . . . . . . . . . . . . . . +300°C I. 100% Production Tested. II. 100% production tested at +25°C, and sample tested at specified temperatures. AC testing done on sample basis. III. Sample Tested Only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. VI. All devices are 100% production tested at +25°C, sample tested at temperature extremes. 1 Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure of absolute maximum rating conditions for extended periods of time may affect device reliability. 2 Typical thermal impedance is θJA = 45°C/W, θJC = 41°C/W. +VS 50Ω 50Ω WRITE HOLD ORDERING GUIDE Model Temperature Range AD9660KR 0°C to +70°C AD9660KR-REEL 0°C to +70°C BIAS HOLD Package Option SENSE IN R-28 R-28 (1000/reel) T/H PIN ASSIGNMENTS 1mA OFFSET SET WRITE CAL 1 28 OFFSET PULSE WRITE PULSE 2 27 OFFSET SET WRITE LEVEL 3 26 GROUND VREF 4 25 +VS WRITE HOLD 5 AD9660KR TOP VIEW 23 +VS (Not to Scale) 6 +VS 7 22 OUTPUT SENSE IN 8 21 +VS GAIN 9 20 OUTPUT +VS 11 VBANDGAP 24 OUTPUT GROUND POWER MONITOR 10 +VS 100Ω VREF +VS 450Ω 19 +VS 1250Ω 18 OUTPUT GROUND 12 17 GROUND BIAS HOLD 13 16 DISABLE BIAS LEVEL 14 15 BIAS CAL TTL INPUT +VS OUTPUT Equivalent Circuits CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9660 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –3– WARNING! ESD SENSITIVE DEVICE AD9660 PIN DESCRIPTIONS Pin Function OUTPUT Analog laser diode current output. Connect to anode of laser diode, cathode connected to GROUND externally. BIAS LEVEL Analog voltage input, VREF to VREF + 1.6 V. Bias current is set proportional to the BIAS LEVEL during calibration as follows: −V V I MONITOR = BIAS LEVEL REF 1.85 × ( RGAIN + 50 Ω ) BIAS CAL TTL/CMOS compatible, Bias loop T/H control signal. Logic HIGH enables calibration mode, and the bias loop T/H immediately goes into track mode. Logic LOW disables the bias loop T/H and immediately places it in hold mode. WRITE PULSE should be held logic LOW while calibrating. Floats logic HIGH. BIAS HOLD External hold capacitor for the bias loop T/H. Approximate droop in the bias current while BIAS CAL is logic LOW is: ±∆I BIAS = 18 × 10 –9 t BIAS HOLD CBIAS HOLD 1 . Bandwidth of the loop is: BW = 2π (550 Ω) C BIAS HOLD WRITE PULSE TTL/CMOS compatible, current control signal. Logic HIGH supplies IMODULATION to the laser diode. Logic LOW turns IMODULATION off. Floats logic HIGH. WRITE CAL TTL/CMOS compatible, write loop T/H control signal. Logic HIGH enables calibration mode; before enabling calibration the bias loop should be calibrated and OFFSET PULSE driven to an appropriate state. In calibration mode, 13 ns after the WRITE PULSE goes logic HIGH, the write loop T/H goes into track mode (there is no delay if WRITE PULSE is HIGH before WRITE CAL transitions to a HIGH level). The write loop T/H immediately goes into hold mode when the WRITE PULSE goes Logic LOW. WRITE CAL LOW disables the write loop T/H and places it in hold mode. Floats logic HIGH. WRITE LEVEL Analog voltage input, VREF to VREF +1.6 V. Write current is set proportional to the input voltage during calibration as follows: I MONITOR = WRITE HOLD VWRITE LEVEL − V REF 1.85 × (RGAIN + 50 Ω) External hold capacitor for the write loop T/H. Approximate droop in IMODULATION current while WRITE CAL is −9 logic LOW is: ±∆I MODULATED = BW = 18 × 10 tWRITE HOLD CWRITE HOLD . Bandwidth of the loop is: 1 2π (550 Ω) CBIAS HOLD SENSE IN Analog current input, IMONITOR, from PIN photo detector diode. SENSE IN should be connected to the cathode of the PIN diode, with the PIN anode connected to GROUND or a negative voltage. Voltage at SENSE IN varies slightly with temperature and current, but is typically 4.0 V. GAIN External connection for the feedback network of the transimpedance amplifier. External feedback network, RGAIN and CGAIN, should be connected between GAIN and POWER MONITOR. See text for choosing values. POWER MONITOR Output voltage monitor of the internal feedback loop. Voltage is proportional to feedback current from photo diode. OFFSET Set resistor connection for the offset current source. Resistor between OFFSET CURRENT SET and +VS CURRENT SET determines offset current level. The input voltage at this node varies slightly with temperature and current, but is typically 1.4 V. See curves. Can also be driven with a current out DAC. OFFSET PULSE TTL/CMOS compatible, OFFSET current control signal. Logic HIGH adds IOFFSET to IOUT. Logic LOW turns off IOFFSET. Floats logic HIGH. DISABLE TTL/CMOS compatible, current output disable circuit. Logic LOW for normal operation; logic HIGH disables the current outputs to the laser diode, and drives the voltage on the hold capacitors close to VREF (minimizes the output current when the device is re-enabled). DISABLE floats logic HIGH. VREF Analog Voltage Output, internal bandgap voltage reference, ~1.75 V, provided to user for power level offset. +VS Positive Power Supply. Nominally +5 V, pin connections should be tied together externally. GROUND Ground Reference. All grounds should be tied together externally. –4– REV. 0 Typical Performance Characteristics–AD9660 6.25mV 35 30 IOFFSET 25 20mV –193.8mV 2ns 20 15 10 ML64116R OUTPUT TEK 11802 O'SCOPE 50Ω 5 0 AD9660 50Ω 0 5 10 15 ROFFSET – kΩ 20 25 –120V Figure 2. IOFFSET vs. ROFFSET ANTEL ARS1 PHOTO DETECTOR Figure 1. Driving ML64116R Laser @ 30 mW current is proportional to the laser diode light power, the loops effectively control laser power to a level proportional to the analog inputs. The control loops should be periodically calibrated independently (see Choosing CBIAS HOLD and CWRITE HOLD). THEORY OF OPERATION The AD9660 combines a very fast output current switch with onboard analog light power control loops to provide the user with a complete laser diode driver solution. The block diagram illustrates the key internal functions. The control loops of the AD9660, the bias loop and the write loop, adjust the output current level, IOUT, so that the photo diode feedback current, IMONITOR, out of SENSE IN is proportional to the analog input voltage at BIAS LEVEL or WRITE LEVEL. Since the monitor The offset current generator produces an open loop output current, IOFFSET. Its level is controlled by an external set resistor or a current out DAC (see Figure 2). While IOFFSET is not calibrated as the currents from the bias and write loops are, it can be very versatile (see Offset Current below). WRITE HOLD TTL WRITE PULSE WRITE CAL WRITE LEVEL AD9660 DISABLE CIRCUIT DISABLE VOLT REF VREFOUT TTL * TTL DELAY WRITE LOOP ANALOG IMODULATION V:1 5pF IOUT OUTPUT 1:10 LASER DIODE VREF GAIN 50 2* IMONITOR CGAIN RGAIN TZA POWER MONITOR VREF BIAS LEVEL BIAS CAL 4.0V 1.85:1 ANALOG IMONITOR VREF OFFSET PULSE PHOTO DETECTOR IBIAS V:1 1:10 ANALOG 5pF BIAS LOOP TTL 1:10 IOFFSET BIAS HOLD SENSE IN 1.4V TTL OFFSET CURRENT SET +VS * 10ns DELAY ON RISING EDGE; 0ns ON FALLING Figure 3. Functional Block Diagram REV. 0 –5– AD9660 DISABLE POWER-UP OR LASER NOT IN USE RECALIBRATE THE BIAS LOOP BIAS CAL TIME BIAS CAL WRITE LOOP CAL TIME WRITE CAL WRITE LOOP HOLD TIME RECALIBRATE WRITE LOOP WRITE PULSE CALIBRATED WRITE LASER OUTPUT POWER LASER POWER MODULATED BETWEEN BIAS AND WRITE LEVELS CALIBRATED BIAS Figure 4. Normal Operating Mode When the write loop is open (WRITE CAL logic LOW), IMODULATION is proportional to the held voltage at WRITE HOLD. The external hold capacitor (WRITE HOLD) determines the droop error between calibrations. IMODULATION may be switched on and off by WRITE PULSE when the write loop is open. The disable circuit turns off IOUT and returns the hold capacitor voltages to their minimum levels (minimum output current) when DISABLE = logic HIGH. It is used during initial powerup of the AD9660 or during time periods when the laser is inactive. When the AD9660 is re-enabled the control loops must be recalibrated. 4 Normal operation of the AD9660 involves (in order, see figure): 0°C CASE OPTICAL OUTPUT – mW 1. The AD9660 is enabled (DISABLE = logic LOW). 2. The input voltages (BIAS LEVEL and WRITE LEVEL) are driven to the appropriate levels to set the calibrated laser diode output power levels. 3. The bias loop is closed for calibration (BIAS CAL = logic HIGH), and then opened (BIAS CAL = logic LOW). 4. The write loop is closed for calibration (WRITE PULSE and WRITE CAL = logic HIGH) and then opened. 5. While both loops are open, the laser is pulsed between the two calibrated levels by WRITE PULSE. 3 50°C CASE BIAS CALIBRATION POWER 1 0 0 20 6. The bias and write loops are periodically recalibrated as needed. 7. The AD9660 is disabled when the laser will not be pulsed for an indefinite period of time. 120 The sections below discuss choosing the external components in the feedback loops for a particular application. The relationship between IMONITOR and VBIAS LEVEL is VBIAS LEVEL − VREF Choosing RGAIN The gain resistor, RGAIN, allows the user to match the feedback loop’s transfer function to the laser diode/photo diode combination. 1.85 × (RGAIN + 50 Ω) once the bias loop is calibrated. When the bias loop is open (BIAS CAL = logic LOW), its output current, IBIAS, is proportional to the held voltage at BIAS HOLD; the external hold capacitor on this pin determines the droop error in the output bias current between calibrations. The user should define the maximum laser diode output power for the intended application, PLD MAX, and the corresponding photo diode monitor current, IMONITOR MAX. A typical laser diode transfer function is illustrated in Figure 5. RGAIN should be The relationship between IMONITOR and VWRITE LEVEL is I MONITOR = 40 60 80 100 FORWARD CURRENT – mA MOD BIAS Figure 5. Typical Laser Diode Current-to-Optical Power Curve Control Loop Transfer Functions I MONITOR = 25°C CASE CONSTANT WRITE POWER 2 VWRITE LEVEL − VREF chosen as: 1.85 × (RGAIN + 50 Ω) RGAIN = 1.6 V 1.85 × I MONITOR MAX − 50 Ω . The laser diode’s output power will then vary from 0 to PLD MAX for an input range of VREF to VREF +1.6 V @ the BIAS LEVEL and WRITE LEVEL inputs. once the write loop is calibrated. The current supplied by the write loop output is referred to as the modulation current, IMODULATION. –6– REV. 0 AD9660 Minimum specifications for IMONITOR MAX should be used when choosing RGAIN. Users are cautioned that laser diode/photo diode combinations that produce monitor currents that are less than IMONITOR MAX in the equation above will produce higher laser output power than predicted, which may damage the laser diode. Such a condition is possible if RGAIN is calculated using typical instead of minimum monitor current specifications. In that case the input range to the AD9660 BIAS LEVEL and WRITE LEVEL inputs should be limited to avoid damaging laser diodes. Choosing CBIAS HOLD and CWRITE HOLD Choosing values for the hold capacitors, CWRITE and CHOLD, is a tradeoff between output current droop when the control loops are open, and the time it takes to calibrate and recalibrate the laser power when the loops are closed. The amount of output current droop is determined by the value of the hold capacitor and the leakage current at that node. When either of the two control loops are open (WRITE CAL or BIAS CAL logic LOW), the pin connections for the hold capacitors (WRITE HOLD and BIAS HOLD) are high impedance inputs. Leakage currents will range from ± 200 nA; this low current minimizes the droop in the output power level. Assuming the worst case current of ± 200 nA, the output current will change as follows: Although not recommended, another approach would be to use a potentiometer for RGAIN. This allows users to optimize the value of RGAIN for each laser diode/photo diode combination’s monitor current. The drawback to this approach is that potentiometer’s stray inductance and capacitance may cause the transimpedance amplifier to overshoot and degrade its settling, and the value of CGAIN may not be optimized for the entire potentiometer’s range. ±∆I BIAS = CGAIN optimizes the response of the transimpedance amplifier and should be chosen as from the table below. Choosing CGAIN larger than the recommended value will slow the response of the amplifier. Lower values improve TZA bandwidth but may cause the amplifier to oscillate. Recommended CGAIN ≥2.5 kΩ 1.5 kΩ 1 kΩ 500 Ω 2 pF 3 pF 4 pF 8 pF −9 tWRITE HOLD CWRITE HOLD If the same application had a hold time requirement of 250 µs, then the minimum value of the hold capacitor would be: CHOLD = REQ CEQ REQ + 50Ω = (RF + 50Ω) (1+ 18 × 10 −9 × 250 µs 1.0 mA = 4.5 nF When determining the calibration time, the T/H and the external hold capacitor can be modeled using the simple RC circuit illustrated in Figure 7. VREF R2 R1 + ) R1 RF GAIN IMONITOR 18 × 10 mW ∆I MAX = 5 mW × (5%) / 0.25 = 1.0 mA mA RINTERNAL 50Ω SENSE IN 2I PIN t BIAS HOLD To choose a value, the user will need to determine the amount of time the loop will be in hold mode, tWRITE HOLD or tBIAS HOLD, the maximum change in laser output power the application can tolerate, and the laser efficiency (defined as the change in laser output power to the change in laser diode current). As an example, if an application requires 5 mW of laser power ± 5%, and the laser diode efficiency is 0.25 mW/mA, then The circuit in Figure 6 allows an adjustable gain with low variance in bandwidth, but requires several external components. EQUIVALENT CIRCUIT −9 CBIAS HOLD ±∆I MODULATED = Table I. RGAIN 18 × 10 AD9660 RINTERNAL 50Ω C1 RF WRITE LEVEL OR BIAS LEVEL CF 1:2 R WRITE HOLD OR BIAS HOLD T/H CHOLD POWER MONITOR VREF VREF R1 POWER MONITOR TZA R2 Figure 7. Circuit Model for Determining Calibration Times R3 1.7kΩ AD9660 Figure 6. Adjustable Gain Configuration REV. 0 EXTERNAL HOLD CAPACITOR –7– AD9660 Using this model, the voltage at the hold capacitor is Initial calibration is required after power-up or any other time the laser has been disabled. Disabling the AD9660 drives the hold capacitors back down to VREF. In this case, or in any case where the output current is more than 10% out of calibration, R will range from 300 Ω to 550 Ω for the model above; the higher value should be used for calculating the worst case calibration time. Following the example above, if CHOLD were chosen as 4.5 nF, then τ = RC = 550 Ω × 4.5 nF would be 2.5 µs. For an initial calibration error <1%, the initial calibration time should be >5τ = 12.4 µs. −t VCHOLD = Vt = 0 + (V t = ∞ − Vt = 0 ) 1 − e τ where t0 is when the calibration begins (WRITE CAL or BIAS CAL goes logic HIGH), Vt = 0 is the voltage on the hold cap at t = 0, Vt = ∞ is the steady state voltage at the hold cap with the loop closed, and τ = RCHOLD is the time constant. With this model the error in VCHOLD for a finite calibration time, as compared to Vt = ∞ , can be estimated from the following table and chart: Initial calibration time will actually be better than this calculation indicates, as a significant portion of the calibration time will be within 10% of the final value, and the output resistance in the AD9660’s T/H decreases as the hold voltage approaches its final value. Table II. tCALIBRATION % Final Value Error % 7τ 6τ 5τ 4τ 3τ 2τ τ 99.9 99.7 99.2 98.1 95.0 86.5 63.2 0.09 0.25 0.79 1.83 4.97 13.5 36.8 Recalibration is functionally identical to initial calibration, but the loop need only correct for droop. Because droop is assumed to be a small percentage of the initial calibration (<10%), the resistance for the model above will be in the range of 75 Ω to 140 Ω. Again, the higher value should be used to estimate the worst case time needed for recalibration. Continuing with the example above, since the error during hold time was chosen as 5%, we meet the criteria for recalibration and τ = RC = 140 Ω × 4.5 nF = 0.63 µs. To get a final error of 1% after recalibration, the 5% droop must be corrected to within a 20% error (20% × 5% = 1%). A 2τ recalibration time of 1.26 µs is sufficient. 100 % FINAL VALUE – % of Volts 90 80 Continuous Recalibration 70 In applications where the hold capacitor is small (<500 pF) and the WRITE PULSE signals always have a pulse width >25 ns, the user may continuously calibrate the write loop. In such an application, the WRITE CAL signal should be held logic HIGH, and the WRITE PULSE signal will control write loop calibration via the internal AND gate. 60 50 40 30 20 The bias loop may be continuously recalibrated whenever WRITE PULSE is logic LOW. 10 0 0 1 2 3 4 CALIBRATION TIME – Time Constants = 5 Figure 8. Calibration Time Curve –8– REV. 0 AD9660 • From the monitor current specification and the max power specified: Example Calculations The example below (in addition to the one included in the sections above) should guide users in choosing RGAIN, CGAIN, the hold capacitor values, and worst case calibration times. I MONITOR MAX = 25 mW System Requirements: 5 µA = 125 µA mW and • Bias laser power: 4 mW Bias ± 5% RGAIN = • Write laser power: 25 mW ± 0.5% • Bias Hold Time: 1 ms 1.6 V 1.85 × I MONITOR MAX • CGAIN would be chosen as 2 pF (see Table I). • Write Hold Time: 1 µs Driving the Analog Inputs Laser diode/photo diode characteristics: The BIAS LEVEL and WRITE LEVEL inputs of the AD9660 drive the track and hold amplifiers and allow the user to adjust the amount of output current as described above. The input voltage range on both inputs is VREF to VREF + 1.6 V, requiring the user to create an offset of VREF for a ground based signal. The circuit in Figure 9 will perform the level shift and scale the output of a DAC whose output is from ground to a positive voltage. This solution is attractive because both the DAC and the op amp can run off a single +5 V supply, and the op amp doesn’t have to swing rail to rail. • Laser efficiency 0.5 mA/mA • Monitor current: 5 µA/mA • From the laser power requirements and efficiency we can estimate: mW ∆I BIAS MAX = 4 mW × (5%) / 0.5 = 400.0 µA mA and mW ∆IWRITE MAX = 25 mW × (0.5% ) / 0.5 = 250 µA mA VREF + VDAC1 • Choosing hold caps based on these: CBIAS HOLD = 18 × 10 −9 × 1 ms 400 µA R1 VDAC1 = 0.045 µF +5V OP291 R1 AD9660 BIAS LEVEL DAC1 R2 18 × 10 −9 × 1 µs 250 µA VDAC2 = 72 pF VREF R3 R4 DAC2 R3 • The bias loop initial calibration time for a <1% error: 5τ = 5 × RC = 5 × 550 Ω × 0.045 µF = 123.75 µs OP291 WRITE LEVEL R4 • Bias loop recalibration for a 1% error after 5% droop (need to correct within 20%): 2τ = 2 × RC = 2 × 140 Ω × 0.045 µF = 12.6 µs VREF + VDAC2 R4 = VWRITE LEVEL R3 Figure 9. Driving the Analog Inputs • The write loop initial calibration time for <0.1% error: 7τ = 7 × RC = 7 × 550 Ω × 72 pF = 277.2 ns • Write loop re-calibration for a 0.1% error after 0.5% droop (need to correct within 20%): 2τ = RC = 2 × 140 Ω × 72 pF = 20.2 ns REV. 0 R2 = VBIAS LEVEL R1 R2 and CWRITE HOLD = − 50 Ω = 6.9 kΩ –9– AD9660 Offset Current Generator AD9660 Layout Considerations The offset current source allows the user to inject a fixed, uncalibrated current into the laser diode. The offset current source is set by an external resistor connected between OFFSET CURRENT SET and +VS, and is controlled by OFFSET PULSE. See Figure 2 for a transfer function of the offset current source. As in all high speed applications, proper layout is critical; it is particularly important when both analog and digital signals are involved. Analog signal paths should be kept as short as possible, and isolated from digital signals to avoid coupling in noise. In particular, digital lines should be isolated from OUTPUT, PIN SENSE, WRITE LEVEL, and BIAS LEVEL traces. Digital signal paths should also be kept short, and run lengths matched to avoid propagation delay mismatch. The offset current may be used to increase the output current provided by the bias and/or write loops after calibration. Alternatively, the offset current may be added during the calibration of the bias loop and switched off after calibration to drop the bias current below the knee of the laser diode power curve. This is illustrated in Figure 10. 4 OPTICAL OUTPUT – mW 0°C CASE 3 Layout of the ground and power supply circuits is also critical. A single, low impedance ground plane will reduce noise on the circuit ground. Power supplies should be capacitively coupled to the ground plane to reduce noise in the circuit. 0.1 µF surface mount capacitors, placed as close as possible to the AD9660 +VS connections meet this requirement. Multilayer circuit boards allow designers to lay out signal traces without interrupting the ground plane, and provide low impedance power planes to further reduce noise. Minimizing the Impedance of the Output Current Path 25°C CASE CONSTANT WRITE POWER 2 50°C CASE BIAS CALIBRATION POWER 1 OPERATING BIAS LEVEL 0 0 20 40 60 80 FORWARD CURRENT – mA 100 120 BIAS OFFSET2 1 BIAS MOD 1 WITH OFFSET CURRENT TURNED OFF, BIAS CURRENT IS BELOW THE KNEE OF THE LASER DIODE 2 OFFSET CURRENT TURNED ON DURING BIAS-CAL Figure 10. Laser Diode Current-to-Optical Power Curve Illustrating Bias Below Diode Knee Because of the very high current slew that the AD9660 is capable of producing (70+ mA in 1.5 ns), the inductance of the output current path to and from the laser diode is critical. A good layout of the output current path will yield high quality light pulses with rise times of about 1.5 ns and less than 5% overshoot. A poor layout can result in significant overshoot and ringing. The most important guideline for the layout is to minimize the impedance (mostly inductance) of the output current path to the laser. It is important to recognize that the laser current path is a closed loop. The figure illustrates the path that current travels: (1) from the output pins of the AD9660 to the anode of the laser, (2) through the laser to the cathode (ground), (3) through the return path, (4) through the 0.1 µF bypass capacitors back to the +VS pins of the AD9660 where (5) the current travels through the output driver circuitry of the AD9660, and back to the output pins. The inductance of this loop can be minimized by placing the laser as close to the AD9660 as possible to keep the loop short, and by placing the send and return paths on adjacent layers of the PC board to take advantage of mutual coupling of the path inductances. This mutual coupling effect is the most important factor in reducing inductance in the current path. –10– REV. 0 AD9660 The best possible TZA settling will be achieved by using a single carbon surface mount resistor (usually 5% tolerance) for RGAIN and small surface mount capacitor for CGAIN. Because the GAIN pin (Pin 9) is essentially connected to the inverting input of the TZA, it is very sensitive to stray capacitance. RGAIN should be placed between Pin 9 and Pin 10, as close as possible to Pin 9. Small traces should be used, and the ground and +VS planes adjacent to the trace should be removed to further minimize stray capacitance. The trace from the output pins of the AD9660 to the anode of the laser (send trace) should be several millimeters wide and should be as direct as possible. The return current will choose the path of least resistance. If the return path is the ground plane, it should have an unbroken path, under the output trace, from the laser cathode back to the AD9660. If the return path is not the ground plane (such as on a two layer board, or on the +VS plane), it should still be on the board plane adjacent to the plane of the output trace. If the current cannot return along a path that follows the output trace, the inductance will be drastically increased and performance will be degraded. The trace from SENSE IN to the cathode of the PIN photodetector should be thin and routed away from the laser anode trace. Optimizing the Feedback Layout In applications where the dynamic performance of the analog feedback loop is important, it is necessary to optimize the layout of the gain resistor, RGAIN, as well as the monitor current path to SENSE IN. Such applications include MOD systems which recalibrate the write loop on pulses as short as 25 ns, and closed loop applications. PIN ASSIGNMENTS MUTUAL COUPLING REDUCES INDUCTANCE +VS PIN CONNECTIONS 25 LASER DIODE CURRENT PATH SEGMENTS (SEE TEXT) 24 23 1 22 21 5 20 3 2 19 AD9660 4 OUTPUT PIN CONNECTIONS BYPASS CAPS GROUND PIN CONNECTIONS GROUND PLANE Figure 11. Laser Diode Current Loop REV. 0 –11– AD9660 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). C2040–6–7/95 28-Pin Plastic SOIC (R-28) 0.712 (18.08) 0.700 (17.78) 28 15 0.419 (10.64) 0.393 (9.98) 0.300 (7.60) 0.292 (7.40) 1 14 PIN 1 0.104 (2.64) 0.093 (2.36) 0.012 (0.30) 0.004 (0.10) 0.019 (0.48) 0.014 (0.36) SEATING PLANE 0.013 (0.33) 0.009 (0.23) 0.04 (1.02) 0.024 (0.61) PRINTED IN U.S.A. 0.0500 (1.27) BSC –12– REV. 0