ADC0852/ADC0854 Multiplexed Comparator with 8-Bit Reference Divider General Description The ADC0852 and ADC0854 are CMOS devices that combine a versatile analog input multiplexer, voltage comparator, and an 8-bit DAC which provides the comparator’s threshold voltage (VTH). The comparator provides a ‘‘1-bit’’ output as a result of a comparison between the analog input and the DAC’s output. This allows for easy implementation of set-point, on-off or ‘‘bang-bang’’ control systems with several advantages over previous devices. The ADC0854 has a 4 input multiplexer that can be software configured for single ended, pseudo-differential, and full-differential modes of operation. In addition the DAC’s reference input is brought out to allow for reduction of the span. The ADC0852 has a two input multiplexer that can be configured as 2 single-ended or 1 differential input pair. The DAC reference input is internally tied to VCC. The multiplexer and 8-bit DAC are programmed via a serial data input word. Once programmed the output is updated once each clock cycle up to a maximum clock rate of 400 kHz. Features Y Y Y Y Y Y 2 or 4 channel multiplexer Differential or Single-ended input, software controlled Serial digital data interface 256 programmable reference voltage levels Continuous comparison after programming Fixed, ratiometric, or reduced span reference capability (ADC 0854) Key Specifications Y Y Y Accuracy, g (/2 LSB or g 1 LSB of Reference (0.2%) Single 5V power supply Low Power, 15 mW TL/H/5521 – 1 FIGURE 1. ADC0854 Simplified Block Diagram (ADC0852 has 2 input channels, COM tied to GND, VREF tied to VCC, V a omitted, and one GND connection) 2 Channel and 4 Channel Pin Out ADC0854 4-CHANNEL MUX Dual-In-Line Package ADC0852 2-CHANNEL MUX Dual-In-Line Package TL/H/5521 – 10 Top View AGND and COM internally connected to GND VREF internally connected to VCC TL/H/5521 – 11 Order Number ADC0852 See NS Package Number N08E TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/H/5521 Top View Order Number ADC0854 See NS Package Number N14A RRD-B30M75/Printed in U. S. A. ADC0852/ADC0854 Multiplexed Comparator with 8-Bit Reference Divider April 1995 Absolute Maximum Ratings (Notes 1 and 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Current into V a (Note 3) Supply Voltage, VCC (Note 3) Voltage Logic and Analog Inputs Input Current per Pin Input Current per Package Storage Temperature Package Dissipation at TA e 25§ C (Board Mount) 15 mA 6.5V Lead Temp. (Soldering, 10 seconds) Dual-In-Line Package (plastic) 260§ C ESD Susceptibility (Note 14) 2000V Operating Conditions Supply Voltage, VCC b 0.3V to VCC a 0.3V 4.5VDC to 6.3VDC Temperature Range ADC0854CCN, ADC0852CCN g 5 mA TMIN s TA s TMAX 0§ C s TA s 70§ C g 20 mA b 65§ C to a 150§ C 0.8W Electrical Characteristics The following specifications apply for VCC e V a e 5V (no V a on ADC0852), VREF s VCC a 0.1V, fCLK e 250 kHz unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits TA e TJ e 25§ C. ADC0852CCN ADC0854CCN Parameter Conditions Typ (Note 4) Tested Limit (Note 5) Design Limit (Note 6) Units g1 g1 LSB 20 mV CONVERTER AND MULTIPLEXER CHARACTERISTICS Total Unadjusted Error (Note 7) ADC0852/4/CCN VREF Forced to 5.000 VDC Comparator Offset ADC0852/4/CCN 2.5 Minimum Total Ladder Resistance ADC0854 (Note 15) 3.5 1.3 1.3 kX Maximum Total Ladder Resistance ADC0854 (Note 15) 3.5 5.4 5.9 kX Minimum Common-Mode Input (Note 8) All MUX Inputs and COM Input GND – 0.05 GND – 0.05 V Maximum Common-Mode Input (Note 8) All MUX Inputs and COM Input DC Common-Mode Error Power Supply Sensitivity VCC e 5V g 5% VZ, Internal diode breakdown at V a (Note 3) 15 mA into V a VCC a 0.05 VCC a 0.05 V g (/16 g (/4 g (/4 LSB g (/16 g (/4 g (/4 LSB MIN MAX IOFF, Off Channel Leakage Current (Note 9) 6.3 8.5 On Channel e 5V, Off Channel e 0V b 200 On Channel e 0V, Off Channel e 5V a 200 2 V V b1 mA nA a1 mA nA Electrical Characteristics (Continued) The following specifications apply for VCC e V a e 5V (no V a on ADC0852), fCLK e 250 kHz unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits TA e TJ e 25§ C. ADC0852CCN ADC0854CCN Parameter Conditions Typ (Note 4) Tested Limit (Note 5) Design Limit (Note 6) Units a1 mA nA b1 mA nA CONVERTER AND MULTIPLEXER CHARACTERISTICS (Continued) ION, On Channel Leakage Current (Note 9) On Channel e 5V, Off Channel e 0V a 200 On Channel e 0V, Off Channel e 5V b 200 DIGITAL AND DC CHARACTERISTICS VIN(1), Logical ‘‘1’’ Input Voltage VCC e 5.25V 2.0 2.0 V VIN(0), Logical ‘‘0’’ Input Voltage VCC e 4.75V 0.8 0.8 V IIN(1), Logical ‘‘1’’ Input Current VIN e VCC 0.005 1 1 mA IIN(0), Logical ‘‘0’’ Input Current VIN e 0V b 0.005 b1 b1 mA VOUT(1), Logical ‘‘1’’ Output Voltage VCC e 4.75V IOUT e b360 mA IOUT e b10 mA 2.4 4.5 2.4 4.5 V V VOUT(0), Logical ‘‘0’’ Output Voltage IOUT e 1.6 mA, VCC e 4.75V 0.4 0.4 V IOUT, TRI-STATEÉ Output Current (DO) CS e Logical ‘‘1’’ VOUT e 0.4V VOUT e 5V b 0.1 b3 b3 0.1 3 3 mA mA ISOURCE VOUT Short to GND b 14 b 7.5 b 6.5 mA ISINK VOUT Short to VCC 16 9.0 8.0 mA ICC Supply Current ADC0852 Includes DAC Ladder Current 2.7 6.5 6.5 mA ICC Supply Current ADC0854 (Note 3) Does not Include DAC Ladder Current 0.9 2.5 2.5 mA 3 AC Characteristics tr e tf e 20 ns, TA e 25§ C Symbol fCLK Parameter Clock Frequency (Note 12) Conditions Typ (Note 4) MIN MAX Tested Limit (Note 5) Design Limit (Note 6) 10 tD1 Rising Edge of Clock to ‘‘DO’’ Enabled CL e 100 pF 650 tr Comparator Response Time (Note 13) Not Including Addressing Time Units 400 kHz kHz 1000 ns 2 a 1 ms 1/fCLK Clock Duty Cycle (Note 10) MIN MAX 40 60 tSET-UP CS Falling Edge or Data Input Valid to CLK Rising Edge MAX 250 ns tHOLD Data Input Valid after CLK Rising Edge MIN 90 ns tpd1, tpd0 CLK Falling Edge to Output Data Valid (Note 11) MAX CL e 100 pF 650 1000 ns t1H, t0H Rising Edge of CS to Data Output Hi-Z MAX CL e 10 pF, RL e 10k CL e 100 pF, RL e 2k (see TRI-STATE Test Circuits) 125 250 500 ns ns 500 % % CIN Capacitance of Logic Input 5 pF COUT Capacitance of Logic Outputs 5 pF Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. Note 2: All voltages are measured with respect to ground. Note 3: Internal zener diodes (approx. 7V) are connected from V a to GND and VCC to GND. The zener at V a can operate as a shunt regulator and is connected to VCC via a conventional diode. Since the zener voltage equals the A/D’s breakdown voltage, the diode ensures that VCC will be below breakdown when the device is powered from V a . Functionality is therefore guaranteed for V a operation even though the resultant voltage at VCC may exceed the specified Absolute Max of 6.5V. It is recommended that a resistor be used to limit the max current into V a . Note 4: Typicals are at 25§ C and represent most likely parametric norm. Note 5: Tested and guaranteed to National AOQL (Average Outgoing Quality Level). Note 6: Guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels. Note 7: Total unadjusted error includes comparator offset, DAC linearity, and multiplexer error. It is expressed in LSBs of the threshold DAC’s input code. Note 8: For VIN( b ) t VIN( a ) the output will be 0. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the VCC supply. Be careful, during testing at low VCC levels (4.5V), as high level analog inputs (5V) can cause this input diode to conductÐespecially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode. This means that as long as the analog VIN or VREF does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial tolerance and loading. Note 9: Leakage current is measured with the clock not switching. Note 10: A 40% to 60% clock duty cycle range ensures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits then 1.6 mS s CLK Low s 60 mS and 1.6 mS s CLK HIGH s % . Note 11: With CS low and programming complete, D0 is updated on each falling CLK edge. However, each new output is based on the comparison completed 0.5 clock cycles prior (see Figure 5 ). Note 12: Error specs are not guaranteed at 400 kHz (see graph: Comparator Error vs. fCLK). Note 13: See text, section 1.2. Note 14: Human body model, 100 pF discharged through a 1.5 kX resistor. Note 15: Because the reference ladder of the ADC0852 is internally connected to VCC, ladder resistance cannot be directly tested for the ADC0852. Ladder current is included in the ADC0852’s supply current specification. 4 Typical Performance Characteristics Internal DAC Linearity Error vs VREF Voltage Internal DAC Linearity Error vs Temperature Comparator Error vs fCLK Output Current vs Temperature Comparator Offset vs Temperature IREF, Reference Current vs. Temp. ADC0854 ICC, Power Supply Current vs. Temperature, ADC0854* ICC, Power Supply Current vs. fCLK, ADC0854* TL/H/5521 – 2 *For ADC0852 add IREF 5 Timing Diagrams Data Input Timing Data Output Timing TL/H/5521 – 4 TL/H/5521–3 TRI-STATE Test Circuits and Waveforms TL/H/5521 – 5 Leakage Test Circuit TL/H/5521 – 6 6 7 FIGURE 2. Detailed Block Diagram Note 1: For ADC0852; DI is input directly to the D input of ODD/SIGN, select: is forced to a ‘‘1’’, AGND and COM are internally tied to DGND, only VCC is brought out, VREF is internally tied to VCC, only CH2 and CH3 are brought out. TL/H/5521 – 7 8 Note: Valid Output can change only on Falling Edge of CLK. FIGURE 3. Timing Diagram TL/H/5521 – 12 Functional Description In the first cycle (Figure 4a ), one input switch and the inverter’s feedback switch are closed. In this interval, the input capacitor (C) is charged to the connected input (V1) less the inverter’s bias voltage (VB, approx. 1.2 volts). In the second cycle (Figure 4b ) these two switches are opened and the other (V2) input’s switch is closed. The input capacitor now subtracts its stored voltage from the second input and the difference is amplified by the inverter’s open loop gain. The C inverter input (VB’) becomes VB b (V1 b V2) and C a CS the output will go high or low depending on the sign of VB’VB. 1. 1 The Sampled-data Comparator The ADC0852 and ADC0854 utilize a sampled-data comparator structure to compare the analog difference between a selected ‘‘ a ’’ and ‘‘b’’ input to an 8-bit programmable threshold. This comparator consists of a CMOS inverter with a capacitively coupled input (Figure 4 ). Analog switches connect the two comparator inputs to the input capacitor and also connect the inverter’s input and output. This device in effect now has one differential input pair. A comparison requires two cycles, one for zeroing the comparator and another for making the comparison. FIGURE 4. Sampled-Data Comparator # # # # V0 e VB V on C e V1 –VB CS e Stray Input Node Cap. VB e Inverter Input Bias Voltage TL/H/5521 – 8 FIGURE 4a. Zeroing Phase # VBÊ bVB e (V2bV1) C C a CS bA [CV2bCV1] C a CS # V0 is dependent on V2bV1 # V0 e TL/H/5521 – 9 FIGURE 4b. Compare Phase V0 e bA [C1 (V2 b V1) a C2 (V4 b V3)] C1 a C2 a CS e bA [D Q C1 a D Q C2] C1 a C2 a CS * Comparator Reads VTH from Internal DAC Differentially TL/H/5521 – 14 FIGURE 4c. Multiple Differential Inputs 9 Functional Description (Continued) vide multiple analog channels with software-configurable single-ended, differential, or pseudo-differential operation. The analog signal conditioning required in transducer-input and other types of data acquisition systems is significantly simplified with this type of input flexibility. One device package can now handle ground referenced inputs as well as signals with some arbitrary reference voltage. On the ADC0854, the ‘‘common’’ pin (pin 6) is used as the ‘‘b’’ input for all channels in single-ended mode. Since this input need not be at analog ground, it can be used as the common line for pseudo-differential operation. It may be tied to a reference potential that is common to all inputs and within the input range of the comparator. This feature is especially useful in single-supply applications where the analog circuitry is biased to a potential other than ground. A particular input configuration is assigned during the MUX addressing sequence which occurs prior to the start of a comparison. The MUX address selects which of the analog channels is to be enabled, what the input mode will be, and the input channel polarity. One limitation is that differential inputs are restricted to adjacent channel pairs. For example, channel 0 and 1 may be selected as a differential pair but they cannot act differentially with any other channel. The channel and polarity selection is done serially via the DI input. A complete listing of the input configurations and corresponding MUX addresses for the ADC0852 and ADC0854 is shown in tables I and II. Figure 6 illustrates the analog connections for the various input options. The analog input voltage for each channel can range from 50 mV below ground to 50 mV above VCC (typically 5V) without degrading accuracy. In actual practice, the devices used in the ADC0852/4 are a simple but important expansion of the basic comparator described above. As shown in Figure 4c , multiple differential comparisons can be made. In this circuit, the feedback switch and one input switch on each capacitor (A switches) are closed in the first cycle. Then the other input on each capacitor is connected while all of the first switches are opened. The change in voltage at the inverter’s input, as a result of the change in charge on each input capacitor (C1, C2), will now depend on both input signal differences. 1.2 Input Sampling and Response Time The input phases of the comparator relate to the device clock (CLK) as shown in Figure 5. Because the comparator is a sampling device, its response characteristics are somewhat different from those of linear comparators. The VIN( a ) input is sampled first (CLK high) followed by VIN(b) (CLK low). The output responds to those inputs, one half cycle later, on CLK’s falling edge. The comparator’s response time to an input step is dependent on the step’s phase relation to the CLK signal. If an input step occurs too late to influence the most imminent comparator decision, one more CLK cycle will pass before the output is correct. In effect, the response time for the VIN( a ) input has a minimum of 1 CLK cycle a 1 mS and a maximum of 2 CLK cycles a 1 mS. The VIN(b) input’s delay will range from 1/2 CLK cycle a 1 mS to 1.5 CLK cycles a 1 mS since it is sampled after VIN( a ). The sampled inputs also affect the device’s response to pulsed signals. As shown in the shaded areas in Figure 5, pulses that rise and/or fall near the latter part of a CLK halfcycle may be ignored. 1.3 Input Multiplexer A unique input multiplexing scheme has been utilized to pro- TL/H/5521 – 13 FIGURE 5. Analog Input Timing 10 Functional Description (Continued) TABLE I. MUX Addressing: ADC0854 Single-Ended MUX Mode MUX Address TABLE II. MUX Addressing: ADC0852 Single Ended MUX Mode Channel SGL/ DIF ODD/ SIGN SELECT 0 1 0 0 a 1 0 1 1 1 0 1 1 1 1 2 MUX Address 3 a a COM SGL/ DIF ODD/ SIGN 0 b 1 0 a b 1 1 b a Channel a COM is internally tied to A GND Differential MUX Mode b MUX Address Differential MUX Mode MUX Address Channel SGL/ DIF ODD/ SIGN SELECT 0 1 0 0 0 a b 0 0 1 0 1 0 0 1 1 b 2 3 a b b a 1 Channel SGL/ DIF ODD/ SIGN 0 1 0 0 a b 0 1 b a a 4 Single-Ended 4 Pseudo-Differential 2 Differential Mixed Mode TL/H/5521 – 15 FIGURE 6. Analog Input Multiplexer Options for the ADC0854 11 Functional Description (Continued) be done indefinitely, without reprogramming the device, as long as CS remains low. Each new comparator decision will be shifted to the output on the falling edge of the clock. However, the output will, in effect, ‘‘lag’’ the analog input by 0.5 to 1.5 clock cycles because of the time required to make the comparison and latch the output (see Figure 5 ). 8. All internal registers are cleared when the CS line is brought high. If another comparison is desired CS must make a high to low transition followed by new address and threshold programming. 2.0 THE DIGITAL INTERFACE An important characteristic of the ADC0852 and ADC0854 is their serial data link with the controlling processor. A serial communication format eliminates the transmission of low level analog signals by locating the comparator close to the signal source. Thus only highly noise immune digital signals need to be transmitted back to the host processor. To understand the operation of these devices it is best to refer to the timing diagrams (Figure 3 ) and functional block diagram (Figure 2 ) while following a complete comparison sequence. 1. A comparison is initiated by first pulling the CS (chip select) line low. This line must be held low for the entire addressing sequence and comparison. The comparator then waits for a start bit, its MUX assignment word, and an 8-bit code to set the internal DAC which supplies the comparator’s threshold voltage (VTH). 2. An external clock is applied to the CLK input. This clock can be applied continuously and need not be gated on and off. 3. On each rising edge of the clock, the level present on the DI line is clocked into the MUX address shift register. The start bit is the first logic ‘‘1’’ that appears on this line. All leading zeroes are ignored. After the start bit, the ADC0852 expects the next 2 bits to be the MUX assignment word while the ADC0854, with more MUX configurations, looks for 3 bits. 4. Immediately after the MUX assignment word has been clocked in, the shift register then reads the next eight bits as the input code to the internal DAC. This eight bit word is read LSB first and is used to set the voltage applied to the comparator’s threshold input (internal). 5. After the rising edge of the 11th or 12th clock (ADC0852 or ADC0854 respectively) following the start bit, the comparator and DAC programming is complete. At this point the DI line is disabled and ignores further inputs. Also at this time the data out (DO) line comes out of TRI-STATE and enters a don’t care state (undefined output) for 1.5 clock cycles. 6. The result of the comparison between the programmed threshold voltage and the difference between the two selected inputs (VIN ( a )bVIN (b)) is output to the DO line on each subsequent high to low clock transition. 7. After programming, continuous comparison on the same selected channel with the same programmed threshold can 3.0 REFERENCE CONSIDERATIONS / RATIOMETRIC OPERATION The voltage applied to the ‘‘VREF’’ input of the DAC defines the voltage span that can be programmed to appear at the threshold input of the comparator. The ADC0854 can be used in either ratiometric applications or in systems with absolute references. The VREF pin must be connected to a source capable of driving the DAC ladder resistance (typ. 2.4 kX) with a stable voltage. In ratiometric systems, the analog input voltage is normally a proportion of the DAC’s or A/D’s reference voltage. For example, a mechanical position servo using a potentiometer to indicate rotation, could use the same voltage to drive the reference as well as the potentiometer. Changes in the value of VREF would not affect system accuracy since only the relative value of these signals to each other is important. This technique relaxes the stability requirements of the system reference since the analog input and DAC reference move together, thus maintaining the same comparator output for a given input condition. In the absolute case, the VREF input can be driven with a stable voltage source whose output is insensitive to time and temperature changes. The LM385 and LM336 are good low current devices for this purpose. The maximum value of VREF is limited to the VCC supply voltage. The minimum value can be quite small (see typical performance curves) allowing the effective resolution of the comparator threshold DAC to also be small (VREF e 0.5V, DAC resolution e 2.0 mV). This in turn lets the designer have finer control over the comparator trip point. In such instances however, more care must be taken with regard to noise pickup, grounding, and system error sources. TL/H/5521 – 16 a) Ratiometric b) Absolute with a Reduced Span FIGURE 7. Referencing Examples 12 Functional Description (Continued) resistance. An op-amp RC active low pass filter can provide both impedance buffering and noise filtering should a high impedance source be required. 4.0 ANALOG INPUTS 4. 1 Differential Inputs The serial interface of the ADC0852 and ADC0854 allows them to be located right at the analog signal source and to communicate with a controlling processor via a few fairly noise immune digital lines. This feature in itself greatly reduces the analog front end circuitry often needed to maintain signal integrity. Nevertheless, a few words are in order with regard to the analog inputs should the input be noisy to begin with or possibly riding on a large common mode voltage. The differential input of the comparator actually reduces the effect of common-mode input noise, i.e. signals common to both selected ‘‘ a ’’ and ‘‘b’’ inputs such as 60 Hz line noise. The time interval between sampling the ‘‘ a ’’ input and then the ‘‘b’’ input is (/2 of a clock period (see Figure 5). 4. 3 Arbitrary Analog Input/Reference Range The total span of the DAC output and hence the comparator’s threshold voltage is determined by the DAC reference. For example, if VREF is set to 1 volt then the comparator’s threshold can be programmed over a 0 to 1 volt range with 8 bits of resolution. From the analog input’s point of view, this span can also be shifted by applying an offset potential to one of the comparator’s selected analog input lines (usually ‘‘b’’). This gives the designer greater control of the ADC0852/4’s input range and resolution and can help simplify or eliminate expensive signal conditioning electronics. An example of this capability is shown in the ‘‘Load Cell Limit Comparator’’ of Figure 15 . In this circuit, the ADC0852 allows the load-cell signal conditioning to be done with only one dual op-amp and without complex, multiple resistor matching. The change in the common-mode voltage during this short time interval can cause comparator errors. For a sinusoidal common-mode signal this error is: VERROR (MAX) e VPEAK (2q fCM/2 fCLK) 5.0 POWER SUPPLY A unique feature of the ADC0854 is the inclusion of a 7 volt zener diode connected from the ‘‘V a ’’ terminal to ground (Figures 2 and 8 ) ‘‘V a ’’ also connects to ‘‘VCC’’ via a silicon diode. The zener is intended for use as a shunt voltage regulator to eliminate the need for additional regulating components. This is especially useful if the ADC0854 is to be remotely located from the system power source. An important use of the interconnecting diode between V a and VCC is shown in Figures 10 and 11 . Here this diode is used as a rectifier to allow the VCC supply for the converter to be derived from the comparator clock. The low device current requirements and the relatively high clock frequencies used (10 kHz – 400 kHz) allows use of the small value filter capacitor shown. The shunt zener regulator can also be used in this mode however this requires a clock voltage swing in excess of 7 volts. Current limiting for the zener is also needed, either built into the clock generator or through a resistor connected from the clock to V a . where fCM is the frequency of the common-mode signal, Vpeak is its peak voltage value, and fCLK is the DAC clock frequency. For example, 1 VPP 60 Hz noise superimposed on both sides of a differential input signal would cause an error (referred to the input) of 0.75 mV. This amounts to less than (/25 of an LSB referred to the threshold DAC, (assuming VREF e 5V and fCLK e 250 kHz). 4. 2 Input Currents and Filtering Due to the sampling nature of the analog inputs, short spikes of current enter the ‘‘ a ’’ input and leave the ‘‘b’’ at the clock edges during a comparison. These currents decay rapidly and do not cause errors as the comparator is strobed at the end of the clock period (see Figure 5 ). The source resistance of the analog input is important with regard to the DC leakage currents of the input multiplexer. The worst-case leakage currents of g 1 mA over temperature will create a 1 mV input error with a 1 kX source Typical Applications TL/H/5521 – 17 FIGURE 8. An On-Chip Shunt Regulator Diode TL/H/5521 – 18 FIGURE 9. Using the ADC0854 as the System Supply Regulator 13 Typical Applications (Continued) TL/H/5521–19 FIGURE 10. Generating VCC from the Comparator Clock TL/H/5521 – 20 FIGURE 11. Remote SensingÐClock and Power on One Wire TL/H/5521 – 21 FIGURE 12. Protecting the Analog Input TL/H/5521 – 22 FIGURE 13. One Component Window Comparator Requires no additional parts. Window comparisons can be accomplished by inputting the upper and lower window limits into DI on successive comparisons and observing the two outputs: x input l window x input k window One low and one high x input is within window Two high outputs Two low outputs 14 Typical Applications (Continued) TL/H/5521 – 23 FIGURE 14. Serial Input Temperature Controller Note 1: ADC0854 does not require constant service from computer. Self controlled after one write to DI if CS remains low. Note 2: U1: Solid State Relay, Potter Brumfield ÝEOM1DB22 Note 3: Set Temp via. DI. Range: 0 to 125§ C TL/H/5521 – 24 FIGURE 15. Load Cell Limit Comparator # Differential Input elliminates need for instrumentation amplifier # A total of 4 load cells can be monitored by ADC0854 15 Typical Applications (Continued) TL/H/5521 – 26 * Q1 used in inverted mode for low VSAT TL/H/5521–29 Hysteresis band e 50 mV FIGURE 16. Adding Comparator Hysteresis TL/H/5521 – 27 FIGURE 17. Pulse-Width Modulator # Range of pulse-widths controlled via R1, C1 16 Typical Applications (Continued) TL/H/5521 – 28 FIGURE 18. Serial Input 8-Bit DAC Ordering Information Part Number Analog Input Channels Total Unadjusted Error Package Temperature Range ADC0852CCN 2 g1 N08E 0§ C to 70§ C ADC0854CCN 4 g1 N14A 0§ C to 70§ C 17 18 Physical Dimensions inches (millimeters) Dual-In-Line Package Order Number ADC0852CCN NS Package Number N08E 19 ADC0852/ADC0854 Multiplexed Comparator with 8-Bit Reference Divider Physical Dimensions inches (millimeters) (Continued) Dual-In-Line Package Order Number ADC0854CCN NS Package Number N14A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 2900 Semiconductor Drive P.O. Box 58090 Santa Clara, CA 95052-8090 Tel: 1(800) 272-9959 TWX: (910) 339-9240 National Semiconductor GmbH Livry-Gargan-Str. 10 D-82256 F4urstenfeldbruck Germany Tel: (81-41) 35-0 Telex: 527649 Fax: (81-41) 35-1 National Semiconductor Japan Ltd. Sumitomo Chemical Engineering Center Bldg. 7F 1-7-1, Nakase, Mihama-Ku Chiba-City, Ciba Prefecture 261 Tel: (043) 299-2300 Fax: (043) 299-2500 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductores Do Brazil Ltda. Rue Deputado Lacorda Franco 120-3A Sao Paulo-SP Brazil 05418-000 Tel: (55-11) 212-5066 Telex: 391-1131931 NSBR BR Fax: (55-11) 212-1181 National Semiconductor (Australia) Pty, Ltd. Building 16 Business Park Drive Monash Business Park Nottinghill, Melbourne Victoria 3168 Australia Tel: (3) 558-9999 Fax: (3) 558-9998 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.