ADP3290 8-Bit, Programmable 2- to 4-Phase Synchronous Buck Controller The ADP3290 is a highly efficient, multi−phase, synchronous buck switching regulator controller optimized for converting a 12 V main supply voltage into the core supply voltage of high performance Intel processors. It uses an internal 8−bit DAC to read a Voltage Identification (VID) code directly from the processor, to set the output voltage between 0.5 V and 1.6 V. This device uses a multi−mode control architecture to drive the logic−level PWM outputs. The switching frequency can be programmed according to VR size and efficiency. The chip can provide 2−, 3− or 4−phase operation, allowing for the construction of up to four complementary buck switching stages. The ADP3290 also includes programmable no load offset and load line slope setting function that adjusts the output voltage as a function of the load current, optimally positioning it for a system transient. The ADP3290 also provides accurate and reliable short−circuit protection, adjustable current limit, and a delayed power−good output that accommodates On−The−Fly (OTF) output voltage changes requested by the CPU. http://onsemi.com MARKING DIAGRAM Package Name LFCSP40 CASE Number 932AC ADP3290 #_YYYYYY ZZZZZZZZ CCCCC ADP3290 # YY ZZ CC = Device Code = Pb−Free Package = Date Code = Assembly Lot Number = Country of Origin Features PIN ASSIGNMENT • • • Typical Applications • Desktop PC Power Supplies for: ♦ ♦ Next Generation Intel® Processors VRM Modules © Semiconductor Components Industries, LLC, 2009 July, 2009 − Rev. 2 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 ADP3290 TOP VIEW PWM1 PWM2 PWM3 PWM4 ODN SW1 SW2 SW3 SW4 IMON 11 12 13 14 15 16 17 18 19 20 • • • PIN 1 INDICATOR EN 1 PWRGD 2 FBRTN 3 FB 4 COMP 5 SS 6 DELAY 7 TRDET 8 VRHOT 9 TTSNS 10 ILIM RT RAMP LLINE CSREF CSSUM CSCOMP GND OD IREF • Drivers Fast−Enhanced PWM FlexModet for Excellent Load Transient Performance TRDET to Improve Load Release Active Current Balancing Between All Output Phases Built−In Power−Good/Crowbar Blanking Supports Dynamic VID Code Changes Digitally Programmable 0.5 V to 1.6 V Output Supports VR11.1 Specification Programmable Overcurrent Protection with Programmable Latchoff Delay This is a Pb−Free Device PSI VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 VCC • Selectable 2−, 3−, or 4−Phase Operation at Up to 1 MHz Per Phase • ±7 mV Worse−Case Differential Sensing Error • Logic−Level PWM Outputs for Interface to External High Power ORDERING INFORMATION Device Package Shipping† ADP3290JCPZ−RL LFCSP40 (Pb−Free) 2500/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 1 Publication Order Number: ADP3290/D ADP3290 VCC RT RAMP 31 12 13 SHUNT REGULATOR OSCILLATOR UVLO SHUTDOWN + GND 18 CMP + 1 DAC + 150mV PWRGD VRHOT CSREF + DAC – 350mV – 9 7 TRDET 8 + CMP – + CMP – 30 PWM1 RESET 29 PWM2 28 PWM3 27 PWM4 RESET 2/3/4−PHASE DRIVER LOGIC RESET CURRENT LIMIT CROWBAR THERMAL THROTTLING CONTROL ILIM 11 DELAY – DELAY 2 TTSNS 10 – + + CMP OD CURRENT MEASUREMENT AND LIMIT – + EN – CURRENT BALANCING CIRCUIT – 800mV 19 SET EN RESET TRDET GENERATOR 26 ODN 40 PSI 25 SW1 24 SW2 23 SW3 22 SW4 17 CSCOMP 15 CSREF 16 CSSUM 21 IMON 4 FB 14 LLINE 6 SS IREF 20 + – 5 + COMP PRECISION REFERENCE – FBRTN 3 BOOT VOLTAGE AND SOFT START CONTROL VID DAC ADP3290 32 33 34 35 36 37 38 39 VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Figure 1. Simplified Block Diagram http://onsemi.com 2 3 http://onsemi.com Figure 2. Application Schematic − 4−Phase Operation C8 R3 1nF 1 1% C TRDT 560pF C7 1nF RREF 100k 1% C22 1F D5 1N4148 C18 1F D4 1N4148 18nF C17 C21 18nF Q9 Q7 Q5 Q15 Q13 Q11 IPD09N03LA 27nF U5 C23 ADP3120A 1 8 BST DRVH 2 7 IN SW 3 6 OD PGND 4 VCC DRVL 5 2.2 R7 27nF U4 ADP3120A C19 1 8 BST DRVH 7 2 IN SW 6 3 OD PGND 4 VCC DRVL 5 2.2 R6 27nF U3 C15 ADP3120A 1 8 BST DRVH 2 7 IN SW 6 3 OD PGND 4 VCC DRVL 5 L2 Q8 Q12 Q16 L5 CE1 102 C3 4.7F 102 C9 4.7F 102 C6 4.7F RTH2 100k 5% NTC BSC100N03LS 220nH/0.57m 4.7F C2 C1 4.7F L4 220nH/0.57m BSC100N03LS 4.7F C8 C7 4.7F L3 BSC100N03LS 220nH/0.57m 4.7F C5 C4 4.7F IPD09N03LA RT 113k 1% RSW41 RSW31 RSW21 RSW11 RPH4 68.1k 35.7k 82.5k 68.1k RPH2 1% 1% CCS2 RCS1 RCS2 RPH1 1% RPH3 1.8nF 1.5nF 1% 68.1k 68.1k 5% NPO CCS1 IRFE OD GND CSCOMP CSSUM CSREF LLINE RAMP RT ILIM RLIM 7.5k 1% CIMON 0.1F C14 1F C13 18nF Q4 220nH/0.57m C3 4.7F CIN3 680F CE8 VSS(SENSE) VCC(SENSE) VCC(CORE) RTN 22Fx18 MLCC IN SOCKET 560F/4V/4Vx8 SANYO SEPC SERIES V CC(CORE) 5m Each 0.5V TO 1.6V + + 102 115A TDC, 130A PK C2 4.7F CIN2 680F BSC100N03LS IPD09N03LA RTRDT2 RTRDT1 4.99k 69.8k 1% PWM1 EN PWM2 PWRGD PWM3 FBRTN U1 PWM4 FB ODN COMP ADP3290 SS FROM CPU SW1 SW2 DELAY SW3 TRDET SW4 VRHOT IMON TTSNS 4.99 1% RIMON VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 VCC PSI# CSS 120pF RA 28.0k 8.2nF C6 CDLY 18nF RTH1 0.1F 100k 5% NTC 3.3pF CA CFB PROCHOT 1 40 C4 1F R5 2.2 Q3 Q1 C1 4.7F IPD09N03LA RB 1.21k CB 120pF 1. For a Description of Optional RSW Resistors, See the Theory of Operation Section. 2. Connect Near Each Inductor. IPD09N03LA POWER GOOD C5 1nF C3 100F (C3 OPTIONAL) D3 1N4148 C10 1F D2 1N4148 27nF U2 C11 ADP3120A 8 1 BST DRVH 2 7 IN SW 3 6 OD PGND 4 VCC DRVL 5 R4 2.2 CIN1 680F IPD09N03LA R1 10 D1 1N4148 2700F/16V/3.3 Ax2 SANYO MV−WX SERIES + + C1 C2 C9 18nF IPD09N03LA VTT I/O VIN 12V VIN RTN L1 370nH 18A ADP3290 IPD09N03LA ADP3290 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit VCC −0.3 to +6 V VFBRTN −0.3 to +0.3 V −0.3 to VCC +0.3 V SW1 to SW4 −5 to +25 V SW1 to SW4 <200 ns −10 to +25 V −0.3 to VCC +0.3 V Supply Voltage FBRTN PWM3 to PWM4, Rampadj All other Inputs and Outputs Storage Temperature Range Tstg −65 to +150 °C Operating Ambient Temperature Range TA 0 to 85 °C Operating Junction Temperature TJ 125 °C Thermal Impedance JA 100 °C/W Lead Temperature Soldering (10 sec) Infrared (15 sec) 300 260 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. NOTE: This device is ESD sensitive. Use standard ESD precautions when handling. http://onsemi.com 4 ADP3290 PIN ASSIGNMENT Pin No. Mnemonic Description 1 EN Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low. 2 PWRGD Power−Good Output. Open−drain output that signals when the output voltage is outside of the proper operating range. 3 FBRTN Feedback Return. VID DAC and error amplifier input for remote sensing of the output voltage. 4 FB 5 COMP 6 SS 7 DELAY Delay Timer Setting Input. An external capacitor connected between this pin and GND sets the overcurrent latchoff delay time, boot voltage hold time, EN delay time, and PWRGD delay time. 8 TRDET Transient detection output. This pin is pulled low when a load release transient is detected. 9 VRHOT VR Hot Output. Active high open−drain output that signals when the temperature of the temperature sensor connected to TTSNS exceeds the programmed VRHOT temperature threshold. 10 TTSNS VR Hot Thermal Throttling Sense Input. An NTC thermistor between this pin and GND is used to remotely sense the temperature at the desired thermal monitoring point. 11 ILIM 12 RT 13 RAMP PWM Ramp Slope Setting Input. An external resistor from the converter input voltage to this pin sets the slope of the internal PWM ramp. 14 LLINE Output Load Line Programming Input. This pin can be directly connected to CSCOMP, or it can be connected to the center point of a resistor divider between CSCOMP and CSREF. Connecting LLINE to CSREF disables positioning. 15 CSREF Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense amplifier and the power−good and crowbar functions. This pin should be connected to the common point of the output inductors. 16 CSSUM Current Sense Summing Node. External resistors from each switch node to this pin sum the inductor currents together to measure the total output current. 17 CSCOMP 18 GND 19 OD 20 IREF Current Reference Input. An external resistor from this pin to ground sets the internal reference current used to generate IFB, IDELAY, ISS, ICL, and ITTSNS. 21 IMON IMON Total Current Output Pin. A resistor/capacitor from this pin to FBRTN/VSS Sense sets the IMON signal. 22 to 25 SW4 to SW1 Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases should be left open. 26 ODN 27 to 30 PWM4 to PMW1 31 VCC 32 to 39 VID7 to VID0 40 PSI NOTE: Feedback Input. Error amplifier reference for remote sensing of the output voltage. An external resistor between this pin and the output voltage sets the no−load offset point. Error Amplifier Output and Compensation Point. Soft−Start Delay Setting Input. An external capacitor connected between this pin and GND sets the soft−start ramp−up time. After startup, pin used to control DVID slew−rate. Current Sense and Limit Pin. Connecting a resistor from this pin to CSCOMP sets the internal current sensing signal for current limit and IMON. Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the PWM oscillator frequency. Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determines the gain of the current sense amplifier and the positioning loop response time. Ground. All internal biasing and the logic output signals of the device are referenced to this ground. Output Disable Logic Output for phase 1. This pin is actively pulled low when the EN input is low or when VCC is below its UVLO threshold to signal to the Driver IC that the driver high−side and low−side outputs should go low. Output Disable Logic output for PSI Operation. This pin is pulled low when PSI is low, otherwise it functions the same as OD. Logic−Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the ADP3121. Connecting the PWM4, and/or PWM3 output to VCC causes that phase to turn off, allowing the ADP3290 to operate as a 2−, 3−, or 4−phase controller. Supply Voltage for the Device. A 340 resistor should be placed between the 12 V system supply and the VCC pin. The internal shunt regulator maintains VCC = 5.0 V. Voltage Identification DAC Inputs. These eight pins are pulled down to GND, providing a Logic 0 if left open. When in normal operation mode, the DAC output programs the FB regulation voltage from 0.5 V to 1.6 V. Power State Indicator Input. Pulling this pin low places controller in lower power state operation. True no connect. Printed circuit board traces are allowable. http://onsemi.com 5 ADP3290 ELECTRICAL CHARACTERISTICS (VCC = 12 V, FBRTN = GND, TA = 0°C to 85°C unless otherwise noted) (Note 1) Parameter Symbol Conditions Min Typ Max Unit Reference Current Reference Bias Voltage VIREF Reference Bias Current IIREF 1.5 RIREF = 100 k 14.25 15 V 15.75 A 0 4.4 V −8.0 −7.0 −0.5 +8.0 +7.0 +0.5 mV mV % 1.108 −78.3 V mV Error Amplifier Output Voltage Range (Note 2) Accuracy Load Line Positioning Accuracy VCOMP VFB VFB(BOOT) Relative to nominal DAC output, Referenced to FBRTN, LLINE = CSREF, Temperature Range: 0 °C to 60 °C DAC Code: 0.5 V to 0.99375 V 1.0 V to 1.39375 V 1.4 V to 1.6 V In startup CSREF - LLINE = 80 mV, Temperature Range: 0 °C to 60 °C, DAC = 1.000 V Differential Non−linearity Input Bias Current FBRTN Current Output Current Gain Bandwidth Product 1.092 −81.7 1.1 −80 −1.0 IFB IFB = IIREF 13.5 IFBRTN ICOMP GBW(ERR) Slew Rate +1.0 LSB 15 16.5 A 125 200 A FB forced to VOUT - 3% 500 A COMP = FB 20 MHz COMP = FB 25 V/s LLINE Input Voltage Range VLLINE Relative to CSREF −250 +250 mV LLINE Input Bias Current ILLINE Temperature Range: 0 °C to 60 °C −7.5 +7.5 nA BOOT Voltage Hold Time tBOOT CDELAY = 10 nF 2.0 ms VID Inputs Input Low Voltage VIL(VID) VID(X) Input High Voltage VIH(VID) VID(X) Input Current IIN(VID) 0.3 0.8 V V −1.0 A VID Transition Delay Time (Note 3) VID code change to FB change 400 ns No CPU Detection Turn−Off Delay Time (Note 2) VID code change to PWM going low 5.0 s PSI Input Input Low Voltage VIL(PSI) Input High Voltage VIH(PSI) Input Current IIN(PSI) PSI = HIGH Assertion time tast(PSI) Fsw= 400 kHz, 4−phase, measuring from PSI falling edge to ODN falling edge 1.0 3.0 s tdeast(PSI) Fsw= 400 kHz, 4−phase, measuring from PSI falling edge to ODN falling edge 260 760 ns VIL(TRDET) ITRDET(sink) = −4 mA 300 mV 4.0 MHz De−assertion time 0.3 0.8 V V 1.0 A TRDET Output Low Voltage 150 Oscillator Frequency Range Frequency Variation Output Voltage fOSC fPHASE VRT RAMP Output Voltage VRAMP RAMP Input Current Range IRAMP 0.25 360 200 400 800 440 RT = 130 k to GND 1.9 2.0 2.1 V RAMP - FB −50 +50 mV 1.0 200 A TA = 25 °C, RT = 277 k, 4−phase TA = 25 °C, RT = 130 k, 4−phase TA = 25 °C, RT = 57 k, 4−phase 1. All limits at temperature extremes are guaranteed via correction using standard quality control (SQC). 2. Guaranteed by characterization, not tested in production. 3. Guaranteed by design, not tested in production. http://onsemi.com 6 kHz ADP3290 ELECTRICAL CHARACTERISTICS (VCC = 12 V, FBRTN = GND, TA = 0°C to 85°C unless otherwise noted) (Note 1) Parameter Symbol Conditions Min VOS(CSA) CSSUM - CSREF, CSREF = 0.8V ~1.6V, Temperature Range: 0 °C to 60 °C −0.5 Temperature Range: 0 °C to 60 °C −7.5 Typ Max Unit +0.5 mV Current Sense Amplifier Offset Voltage Input Bias Current Gain Bandwidth Product IBIAS(CSSUM) GBW(CSA) CSSUM = CSCOMP Slew Rate CCSCOMP = 10 pF Input Common−Mode Range CSSUM and CSREF Output Voltage Range Output Current Current Limit Latchoff Delay Time +7.5 10 10 0 tOC(DELAY) CDELAY = 10 nF V/s 3.5 0.05 ICSCOMP nA MHz 3.5 V V 500 A 8.0 ms Current Balance Amplifier Common−Mode Range (Note 3) VSW(X)CM −600 +200 mV Input Resistance RSW(X) SW(X) = 0 V 10 17 26 k Input Current ISW(X) SW(X) = 0 V 8.0 12 20 A ISW(X) SW(X) = 0 V −4.0 +4.0 % 1.0 1.15 V Input Current Matching IMON Output Clamp Voltage Current Gain (IMONCURRENT) / (ILIMITCURRENT), RILIM = RIMON = 8.0 k, PSI = High, Temperature Range: 0 °C to 60 °C 9.5 10 Output Current 10.5 800 Offset VCSREF − VILIMIT 1.2 A mV Current Limit Comparator Current Limit Threshold Current ICL 4/3 x IIREF, PSI = High 17.7 20 22.3 A Delay Timer Normal Mode Output Current IDELAY Output Current in Current Limit IDELAY(CL) Threshold Voltage VDELAY(TH) IDELAY = IIREF 12 15 18 A IDELAY(CL) = 0.25 x IIREF 3.0 3.75 4.5 A 1.6 1.7 1.8 V 13.5 17.5 21.5 Soft−Start Output Current ISS During startup Soft Start slew rate dv/dt Css = 8.2 nF 2.0 mV/s DVID slew rate dv/dt Css = 8.2 nF 10 mV/s A Enable Input Input Low Voltage VIL(EN) Input High Voltage VIH(EN) Input Current IIN(EN) Delay Time 300 800 mV mV 1.0 A ms tDELAY(EN) EN > 800 mV, CDELAY = 10 nF 2.0 Output Low Voltage VOL(OD) VOL(ODN) IOD(SINK) = −400 A IODN(SINK) = −400 A 160 Output High Voltage VOH(OD) VOH(ODN) IOD(SOURCE) = 400 A, IODN (SOURCE) = 400 A OD and ODN Output 4.0 OD Pulldown Resistor 500 mV 5.0 V 60 k Thermal Throttling Control TTSNS Voltage Range Internally limited TTSNS Bias Current 0 −133 1. All limits at temperature extremes are guaranteed via correction using standard quality control (SQC). 2. Guaranteed by characterization, not tested in production. 3. Guaranteed by design, not tested in production. http://onsemi.com 7 −123 5.0 V −113 A ADP3290 ELECTRICAL CHARACTERISTICS (VCC = 12 V, FBRTN = GND, TA = 0°C to 85°C unless otherwise noted) (Note 1) Parameter Symbol Conditions Min Typ Max Unit 715 760 805 mV Thermal Throttling Control cont. TTSNS VRHOT Threshold Voltage TTSNS Hysteresis 50 VRHOT Output Low Voltage VOL(VRHOT) IVRHOT(SINK) = −4 mA, TTSNS = 5.0 V mV 150 300 mV Power−Good Comparator Undervoltage Threshold VPWRGD(UV) Relative to nominal DAC output −400 −350 −300 mV Overvoltage Threshold VPWRGD(OV) Relative to nominal DAC output 100 150 200 mV Output Low Voltage VOL(PWRGD) IPWRGD(SINK) = −4 mA 150 300 mV CDELAY = 10 nF 2.0 Power−Good Delay Time During Soft−Start VID Code Changing 100 VID Code Static Crowbar Trip Point VCB(CSREF) Crowbar Reset Threshold Crowbar Delay Time VID Code Changing tCROWBAR ms 250 s 200 ns Relative to nominal DAC output 100 150 200 mV Relative to FBRTN 305 360 415 mV Overvoltage to PWM going low 100 250 s 400 ns VID Code Static PWM OUTPUTS Output Low Voltage VOL(PWM) IPWM(SINK) = −400 A Output High Voltage VOH(PWM) IPWM(SOURCE) = 400 A 4.0 160 5.0 4.65 5.0 500 mV V Supply VCC VCC VSYSTEM = 12 V, RSHUNT = 340 DC Supply Current IVCC VSYSTEM = 13.2 V, RSHUNT = 340 Shunt Turn−On Current Shunt Turn−On Threshold Voltage Shunt Turn−Off Voltage VSYSTEM 5.55 V 25 mA 6.5 mA VSYSTEM rising 6 V VSYSTEM falling 4.1 V 1. All limits at temperature extremes are guaranteed via correction using standard quality control (SQC). 2. Guaranteed by characterization, not tested in production. 3. Guaranteed by design, not tested in production. TYPICAL CHARACTERISTICS 5000 OSCILLATOR FREQUENCY (kHz) 5000 4500 4000 3500 3000 2500 2000 1500 1000 500 0 0 4500 4000 3500 3000 2500 2000 1500 1000 500 5.8 100 200 300 400 500 600 700 800 900 1000 6.0 6.2 6.4 6.6 RT (k) SUPPLY CURRENT (A) Figure 3. Oscillator Frequency vs. RT Figure 4. Oscillator Frequency vs. Supply Current http://onsemi.com 8 0 ADP3290 Theory of Operation 12V SUPPLY The ADP3290 combines a multi−mode, fixed frequency PWM control with multiphase logic outputs for use in 2−, 3−, or 4−phase synchronous buck CPU core supply power converters. The internal VID DAC is designed to interface with Intel 8−bit VRD/VRM 11.1 and compatible CPUs. Multiphase operation is important for producing the high currents and low voltages demanded by today’s microprocessors. Handling the high currents in a single−phase converter places high thermal demands on the components in the system, such as the inductors and MOSFETs. The multi−mode control of the ADP3290 ensures a stable, high performance topology for the following: • Balancing currents and thermals between phases for both static and dynamic operation • High speed response at the lowest possible switching frequency and output decoupling • FEPWM and TRDET functions for improved load step and load release transient response • Minimizing thermal switching losses by using lower frequency operation • Tight load line regulation and accuracy • Reduced output ripple due to multiphase cancellation • PC board layout noise immunity • Ease of use and design due to independent component selection • Flexibility in operation for tailoring design to low cost or high performance VTT I/O (ADP3290 EN) UVLO THRESHOLD 0.8V VDELAY(TH) (1.7V) DELAY 1.0V SS VBOOT (1.1V) VVID TD3 VCC_CORE VBOOT (1.1V) TD1 VVID TD4 TD2 VR READY (ADP3290 PWRGD) TD5 50ms CPU VID INPUTS VID INVALID VID VALID Figure 5. System Startup Sequence Phase Detection Sequence During startup, the number of operational phases and their phase relationship is determined by the internal circuitry monitoring the PWM outputs. Normally, the ADP3290 operates as a 4−phase PWM controller. Connecting PWM4 pin to VCC programs a 3−phase operation. For 2−phase operation, connect PWM4 and PWM3 pins to VCC. Prior to soft−start, while EN is low, the PWM3 and PWM4 pins sink approximately 100 A. An internal comparator checks the voltage of each pin versus a threshold of 3.15 V. If the pin is tied to VCC, its voltage is above the threshold. Otherwise, an internal current sink pulls the pin to GND, which is below the threshold. PWM1 and PWM2 are low during the phase detection interval that occurs during the first four clock cycles of the internal oscillator. After this time, if the remaining PWM outputs are not pulled to VCC, the 100 A current sink is removed, and they function as normal PWM outputs. If they are pulled to VCC, the 100 A current source is removed, and the outputs are driven into a high impedance state. The PWM outputs are logic−level devices intended for driving fast response external gate drivers such as the ADP3121 and ADP3122. Because each phase is monitored independently, operation approaching 100% duty cycle is possible. In addition, more than one PWM output can be on at the same time to allow overlapping phases. Startup Sequence The ADP3290 follows the VR11.1 startup sequence shown in Figure 5. After both the EN and UVLO conditions are met, the DELAY pin goes through one cycle (TD1). After this cycle, the internal oscillator is enabled. The first four clock cycles are blanked from the PWM outputs and used for phase detection as explained in the Phase Detection Sequence section. Then, the soft−start ramp is enabled (TD2), and the output comes up to the boot voltage of 1.1 V. The boot hold time is determined by the DELAY pin as it goes through a third cycle (TD3). During TD3, the processor VID pins settle to the required VID code. When TD3 is over, the ADP3290 reads the VID inputs and soft−starts either up or down to the final VID voltage (TD4).When TD4 and the PWRGD masking time (equal to VID OTF masking) is completed, a third ramp on the DELAY pin sets the PWRGD blanking (TD5). http://onsemi.com 9 ADP3290 Master Clock Frequency be used to set the load line required by the microprocessor. The current information is then given as CSREF − LLINE. This difference signal is used internally to offset the VID DAC for voltage positioning. The difference between CSREF and CSCOMP is then used as a differential input for the current limit comparator. This allows the load line to be set independently of the current limit threshold. In the event that the current limit threshold and load line are not independent, the resistor divider between CSREF and CSCOMP can be removed and the CSCOMP pin can be directly connected to LLINE. To disable voltage positioning entirely (that is, no load line) connect LLINE to CSREF. To provide the best accuracy for sensing current, the CSA is designed to have a low offset input voltage. Also, the sensing gain is determined by external resistors to make it extremely accurate. The clock frequency of the ADP3290 is set with an external resistor connected from the RT pin to ground. The frequency follows the graph in Figure 3. To determine the frequency per phase, the clock is divided by the number of phases in use. If all phases are in use, divide by 4. If PWM4 is tied to VCC, divide by 3. If PWM4 and PWM3 are tied to VCC, divide by 2. NOTE: Single−Phase operation is also possible; contact ON Semiconductor for more details. Output Voltage Differential Sensing The ADP3290 combines differential sensing with a high accuracy VID DAC and reference, and a low offset error amplifier. This maintains a worst−case specification of ±7.0 mV differential sensing error over its full operating output voltage and with tighter accuracy over a 0 °C to 60 °C temperature range. The output voltage is sensed between the FB pin and FBRTN pin. FB is connected through a resistor to the regulation point, usually the remote sense pin of the microprocessor. FBRTN is connected directly to the remote sense ground point. The internal VID DAC and precision reference are referenced to FBRTN, which has a minimal current of 125 A to allow accurate remote sensing. The internal error amplifier compares the output of the DAC to the FB pin to regulate the output voltage. Active Impedance Control Mode For controlling the dynamic output voltage droop as a function of output current, a signal proportional to the total output current at the LLINE pin can be scaled to equal the regulator droop impedance multiplied by the output current. This droop voltage is then used to set the input control voltage to the system. The droop voltage is subtracted from the DAC reference input voltage to tell the error amplifier where the output voltage should be. This allows enhanced feed−forward response. Output Current Sensing The ADP3290 provides a dedicated current sense amplifier (CSA) to monitor the total output current for proper voltage positioning versus load current, for the IMON output, and for current limit detection. Sensing the load current at the output gives the total real−time current being delivered to the load, which is an inherently more accurate method than peak current detection or sampling the current across a sense element such as the low−side MOSFET. This amplifier can be configured several ways, depending on the objectives of the system, as follows: • Output inductor DCR sensing without a thermistor for lowest cost. • Output inductor DCR sensing with a thermistor for improved accuracy with tracking of inductor temperature. • Sense resistors for highest accuracy measurements. The positive input of the CSA is connected to the CSREF pin, which is connected to the average output voltage. The inputs to the amplifier are summed together through resistors from the sensing element, such as the switch node side of the output inductors, to the inverting input CSSUM. The feedback resistor between CSCOMP and CSSUM sets the gain of the amplifier and a filter capacitor is placed in parallel with this resistor. The gain of the amplifier is programmable by adjusting the input summing resistor. An additional resistor divider connected between CSREF and CSCOMP (with the midpoint connected to LLINE) can Current Control Mode and Thermal Balance The ADP3290 has individual inputs (SW1 to SW4) for each phase that are used for monitoring the current of each phase. This information is combined with an internal ramp to create a current balancing feedback system that has been optimized for initial current balance accuracy and dynamic thermal balancing during operation. This current balance information is independent of the average output current information used for positioning as described in the Load Line Setting section. The magnitude of the internal ramp can be set to optimize the transient response of the system. It also monitors the supply voltage for feed−forward control for changes in the supply. A resistor connected from the power input voltage to the RAMP pin determines the slope of the internal PWM ramp. External resistors can be placed in series with individual phases to create an intentional current imbalance if desired, such as when one phase has better cooling and can support higher currents. Resistor RSW1 through RSW4 can be used for adjusting thermal balance. It is best to have the ability to add these resistors during the initial design, therefore, ensure that placeholders are provided in the layout. To increase the current in any given phase, enlarge RSW for that phase (make RSW = 0 for the hottest phase and do not change it during balancing). Increasing RSW by 1 k can make an increase in phase current. Increase each RSW value by small amounts to achieve balance, starting with the coolest phase first. http://onsemi.com 10 ADP3290 Voltage Control Mode GND, and the capacitor is charged up to the 1.1 V boot voltage by the SS amplifier, which has a limited output current of 15 A. The voltage at the FB pin follows the ramping voltage on the SS pin, limiting the inrush current during startup. The soft−start time depends on the value of the boot voltage and CSS. Once the SS voltage is within 100 mV of the boot voltage, the boot voltage delay time (TD3 in Figure 5) is started. The end of the boot voltage delay time signals the beginning of the second soft−start time (TD4 in Figure 5). The SS voltage now changes from the boot voltage to the programmed VID DAC voltage (either higher or lower) using the SS amplifier with the limited 15 A output current. The voltage of the FB pin follows the ramping voltage of the SS pin, limiting the inrush current during the transition from the boot voltage to the final DAC voltage. The second soft−start time depends on the boot voltage, the programmed VID DAC voltage, and CSS. Once TD5 has finished, the SS pin is then used to limit the slew−rate of DVID steps. The current source is changed to 75 A and the DVID slew−rate becomes 5 X the soft−start slew−rate. Typically, the SS slew−rate is 2 mV/S, so the DVID becomes 10 mV/S. If EN is taken low or if VCC drops below UVLO, DELAY and SS are reset to ground to be ready for another soft−start cycle. Figure 6 shows typical startup waveforms for the ADP3290. A high gain, bandwidth voltage mode error amplifier is used for the voltage mode control loop. The control input voltage to the positive input is set via the VID logic according to the voltages listed. This voltage is also offset by the droop voltage for active positioning of the output voltage as a function of current, commonly known as active voltage positioning. The output of the amplifier is the COMP pin, which sets the termination voltage for the internal PWM ramps. The negative input (FB) is tied to the output sense location with Resistor RB and is used for sensing and controlling the output voltage at this point. A current source from the FB pin flowing through RB is used for setting the no load offset voltage from the VID voltage. The no load voltage is negative with respect to the VID DAC. The main loop compensation is incorporated into the feedback network between FB and COMP. Fast Enhanced Transient Modes SINGLE−PHASE OPERATION The ADP3290 incorporates enhanced transient response for both load steps and load release. For load steps, it senses the error amp to determine if a load step has occurred and sequences the proper number of phases on to ramp up the output current. For load release, it also senses the error amp and uses the load release information to trigger the TRDET pin, which is then used to adjust the feedback for optimal positioning especially during high frequency load steps. Additional information is used during load transients to ensure proper sequencing and balancing of phases during high frequency load steps as well as minimizing stress on the components such as the input filter and MOSFETs. Delay Timer 4−PHASE OPERATION The delay times for the startup timing sequence are set with a capacitor from the DELAY pin to ground. In UVLO, or when EN is logic low, the DELAY pin is held at ground. After the UVLO and EN signals are asserted, the first delay time (TD1 in Figure 5) is initiated. A 15 A current flows out of the DELAY pin to charge CDLY. A comparator monitors the DELAY voltage with a threshold of 1.7 V. The delay time is therefore set by the 15 A charging a capacitor from 0 V to 1.7 V. This DELAY pin is used for multiple delay timings (TD1, TD3, and TD5) during the startup sequence. Also, DELAY is used for timing the current limit latchoff, as explained in the Current Limit, Short−Circuit, and Latchoff Protection section. Soft−Start The soft−start times for the output voltage are set with a capacitor from the SS pin to ground. After TD1 and the phase detection cycle have been completed, the SS time (TD2 in Figure 5) starts. The SS pin is disconnected from Figure 6. Typical Startup Waveform 1-Vo, 2-EN, 3-SS, 4-DELAY, D0−D3-PWM1~4 http://onsemi.com 11 ADP3290 Current Limit, Short−Circuit, and Latchoff Protection The ADP3290 compares a programmable current limit set point to the voltage from the output of the current sense amplifier. The level of current limit is set with the resistor from the ILIM pin to CSCOMP. During operation, the voltage on ILIM is equal to the voltage on CSREF. The current through the external resistor connected between ILIM and CSCOMP is then compared to the internal current limit current Icl. If the current generated through this register into the ILIM pin(ILIM) exceeds the internal current limit threshold current (Icl), the internal current limit amplifier controls the internal COMP voltage to maintain the average output at the limit. If the limit is reached and TD5 in Figure 5 has completed, a latchoff delay time starts, and the controller shuts down if the fault is not removed. The current limit delay time shares the DELAY pin timing capacitor with the startup sequence timing. However, during current limit, the DELAY pin current is reduced to 3.75 A. A comparator monitors the DELAY voltage and shuts off the controller when the voltage reaches 1.7 V. Therefore, the current limit latchoff delay time is set by the current of 3.75 A, charging the delay capacitor from 0 V to 1.7 V. This delay is four times longer than the delay time during the startup sequence. The current limit delay time starts only after the TD5 is complete. If there is a current limit during startup, the ADP3290 goes through TD1 to TD5, and then starts the latchoff time. Because the controller continues to cycle the phases during the latchoff delay time, the controller returns to normal operation and the DELAY capacitor is reset to GND if the short is removed before the 1.7 V threshold is reached. The latchoff function can be reset by either removing and reapplying the supply voltage to the ADP3290, or by toggling the EN pin low for a short time. To disable the short circuit latchoff function, an external resistor should be placed in parallel with CDLY. This prevents the DELAY capacitor from charging up to the 1.7 V threshold. The addition of this resistor causes a slight increase in the delay times. During startup, when the output voltage is below 200 mV, a secondary current limit is active. This is necessary because the voltage swing of CSCOMP cannot go below ground. This secondary current limit controls the internal COMP voltage to the PWM comparators to 1.5 V. This limits the voltage drop across the low−side MOSFETs through the current balance circuitry. An inherent per−phase current limit protects individual phases if one or more phases stop functioning because of a faulty component. This limit is based on the maximum normal mode COMP voltage. Typical overcurrent latchoff waveforms are shown in Figure 7. Figure 7. Dynamic (Load Transient) Overcurrent Latchoff Waveform 1-Vo, 2-Io(from VTT), 3-DELAY, D0~D3-PWM1~4 Output Current Monitor The IMON pin is used to output an analog voltage representing the total output current being delivered to the load. It outputs an accurate current that is directly proportional to the current set by the ILIM resistor. This current is then run through a parallel RC connected from the IMON pin to the FBRTN pin to generate an accurately scaled and filtered voltage per the VR11.1 specification. The size of the resistor is used to set the IMON scaling. If the IMON and OCP are then desired to be changed based on the TDC of the CPU, the ILIM resistor is the only component that needs to be changed. If the IMON scaling is the only desired change, then just changing the IMON resistor accomplishes this. The IMON pin also includes an active clamp to limit the IMON voltage to 1.15 V MAX yet maintaining 900 mV MIN full−scale accurate reporting. Dynamic VID The ADP3290 has the ability to dynamically change the VID inputs while the controller is running. This allows the output voltage to change while the supply is running and supplying current to the load. This is commonly referred to as dynamic VID (DVID). A DVID can occur under light or heavy load conditions. The processor signals the controller by changing the VID inputs in multiple steps from the start code to the finish code. This change can be positive or negative. When a VID input changes state, the ADP3290 detects the change and ignores the DAC inputs for a minimum of 400 ns. This time prevents a false code due to logic skew while the eight VID inputs are changing. Additionally, the first VID change initiates the PWRGD and crowbar blanking functions for a minimum of 100 s to prevent a false PWRGD or crowbar event. Each VID change resets the internal timer. If an OFF VID code is detected, the ADP3290 waits 5 S to ensure this code is correct before initiating a shutdown of the controller. http://onsemi.com 12 ADP3290 providing full−power load transients immediately following exit from a low−power state. One additional feature of the ADP3290 is the internal current limit threshold is changed when PSI is pulled low. The current limit threshold is reduced by 1/N such that the same per phase average current limit is maintained to protect the components in the system. PSI ASSERTION The ADP3290 also adds the use of the SS pin to limit DVID slew−rates. These can be encountered when the system does a large single VID step for power state changes, thus the DVID slew−rate needs to be limited to prevent large in−rush currents. The SS pin uses a 75 A current source into the SS capacitor to do this limiting and typical slew−rates of 10mV/S are set with the design. PSI DE−ASSERTION Figure 8. DVID Waveform (by VTT, 0.5 V-1.5V) 1-Vo D0~D2-PWM1~3 Power−Good Monitoring The power−good comparator monitors the output voltage via the CSREF pin. The PWRGD pin is an open−drain output whose high level, when connected to a pullup resistor, indicates that the output voltage is within the nominal limits specified based on the VID voltage setting. PWRGD goes low if the output voltage is outside of this specified range, if the VID DAC inputs are in no CPU mode, or if the EN pin is pulled low. PWRGD is blanked during a DVID event for a period of 250 s to prevent false signals during the time the output is changing. The PWRGD circuitry also incorporates an initial turn−on delay time (TD5), based on the DELAY timer. Prior to the SS voltage reaching the programmed VID DAC voltage and the PWRGD masking−time finishing, the PWRGD pin is held low. Once the SS pin is within 100 mV of the programmed DAC voltage, the capacitor on the DELAY pin begins to charge. A comparator monitors the DELAY voltage and enables PWRGD when the voltage reaches 1.7 V. The PWRGD delay time is, therefore, set by a current of 15 A, charging a capacitor from 0 V to 1.7 V. Figure 9. PSI Mode Transition Waveform (Io = 25A) 1-Vo, 2-PSI, 3-COMP, 4-TRDET, D0~D2-PWM1~3 Output Crowbar To protect the load and output components of the supply, the PWM outputs are driven low, which turns on the low−side MOSFETs when the output voltage exceeds the upper crowbar threshold. This crowbar action stops once the output voltage falls below the release threshold of approximately 375 mV. Turning on the low−side MOSFETs pulls down the output as the reverse current builds up in the inductors. If the output overvoltage is due to a short in the high−side MOSFET, this action current limits the input supply or blows its fuse, protecting the microprocessor from being destroyed. Power State Indicator The PSI pin is used as an input to determine the operating power state of the load. If this pin is pulled low, the controller knows the load is in a low power state and it takes the ODN signal low, which can be used to disable phases for increased efficiency. The sequencing into and out of low−power operation is maintained to minimize output voltage deviations as well as Output Enable and UVLO For the ADP3290 to begin switching, the input supply current to the controller must be higher than the UVLO threshold and the EN pin must be higher than its 0.8 V threshold. This initiates a system startup sequence. If either http://onsemi.com 13 ADP3290 Thermal Monitoring UVLO or EN is less than their respective thresholds, the ADP3290 is disabled. This holds the PWM outputs at ground, shorts the DELAY capacitor to ground, and the forces PWRGD and OD signals low. In the application circuit, the OD pin should be connected to the OD input of the external driver for the phase that is always on while the ODN pin should be connected to the OD input on the external drivers of the phases that are shut off during low−power operation. Grounding OD and ODN disable the drivers such that both DRVH and DRVL are grounded. This feature is important in preventing the discharge of the output capacitors when the controller is shut off. If the driver outputs are not disabled, a negative voltage can be generated during output due to the high current discharge of the output capacitors through the inductors. The ADP3290 includes a thermal monitoring circuit to detect when a point on the VR has exceeded a user−defined temperature. The thermal monitoring circuit requires an NTC thermistor to be placed between TTSNS and GND. A fixed current of 120 A is sourced out of the TTSNS pin and into the thermistor. The current source is internally limited to 5.0 V. An internal circuit compares the TTSNS voltage to a 0.81 V threshold, and outputs an open−drain signal at the VRHOT output. Once the voltage on the TTSNS pin drops below its threshold, the open−drain output asserts high to signal the system that an overtemperature event has occurred. Because the TTSNS voltage changes slowly with respect to time, 55 mV of hysteresis is built into this comparator. The thermal monitoring circuitry does not depend on EN and is active when UVLO is above its threshold. When UVLO is below its threshold, VRHOT is forced low. VR11.1 VID Codes OUTPUT(V) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 OFF 0 0 0 0 0 0 0 0 OFF 0 0 0 0 0 0 0 1 1.60000 0 0 0 0 0 0 1 0 1.59375 0 0 0 0 0 0 1 1 1.58750 0 0 0 0 0 1 0 0 1.58125 0 0 0 0 0 1 0 1 1.57500 0 0 0 0 0 1 1 0 1.56875 0 0 0 0 0 1 1 1 1.56250 0 0 0 0 1 0 0 0 1.55625 0 0 0 0 1 0 0 1 1.55000 0 0 0 0 1 0 1 0 1.54375 0 0 0 0 1 0 1 1 1.53750 0 0 0 0 1 1 0 0 1.53125 0 0 0 0 1 1 0 1 1.52500 0 0 0 0 1 1 1 0 1.51875 0 0 0 0 1 1 1 1 1.51250 0 0 0 1 0 0 0 0 1.50625 0 0 0 1 0 0 0 1 1.50000 0 0 0 1 0 0 1 0 1.49375 0 0 0 1 0 0 1 1 1.48750 0 0 0 1 0 1 0 0 1.48125 0 0 0 1 0 1 0 1 1.47500 0 0 0 1 0 1 1 0 1.46875 0 0 0 1 0 1 1 1 1.46250 0 0 0 1 1 0 0 0 1.45625 0 0 0 1 1 0 0 1 1.45000 0 0 0 1 1 0 1 0 1.44375 0 0 0 1 1 0 1 1 1.43750 0 0 0 1 1 1 0 0 1.43125 0 0 0 1 1 1 0 1 1.42500 0 0 0 1 1 1 1 0 1.41875 0 0 0 1 1 1 1 1 1.41250 0 0 1 0 0 0 0 0 http://onsemi.com 14 ADP3290 VR11.1 VID Codes OUTPUT(V) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 1.40625 0 0 1 0 0 0 0 1 1.40000 0 0 1 0 0 0 1 0 1.39375 0 0 1 0 0 0 1 1 1.38750 0 0 1 0 0 1 0 0 1.38125 0 0 1 0 0 1 0 1 1.37500 0 0 1 0 0 1 1 0 1.36875 0 0 1 0 0 1 1 1 1.36250 0 0 1 0 1 0 0 0 1.35625 0 0 1 0 1 0 0 1 1.35000 0 0 1 0 1 0 1 0 1.34375 0 0 1 0 1 0 1 1 1.33750 0 0 1 0 1 1 0 0 1.33125 0 0 1 0 1 1 0 1 1.32500 0 0 1 0 1 1 1 0 1.31875 0 0 1 0 1 1 1 1 1.31250 0 0 1 1 0 0 0 0 1.30625 0 0 1 1 0 0 0 1 1.30000 0 0 1 1 0 0 1 0 1.29375 0 0 1 1 0 0 1 1 1.28750 0 0 1 1 0 1 0 0 1.28125 0 0 1 1 0 1 0 1 1.27500 0 0 1 1 0 1 1 0 1.26875 0 0 1 1 0 1 1 1 1.26250 0 0 1 1 1 0 0 0 1.25625 0 0 1 1 1 0 0 1 1.25000 0 0 1 1 1 0 1 0 1.24375 0 0 1 1 1 0 1 1 1.23750 0 0 1 1 1 1 0 0 1.23125 0 0 1 1 1 1 0 1 1.22500 0 0 1 1 1 1 1 0 1.21875 0 0 1 1 1 1 1 1 1.21250 0 1 0 0 0 0 0 0 1.20625 0 1 0 0 0 0 0 1 1.20000 0 1 0 0 0 0 1 0 1.19375 0 1 0 0 0 0 1 1 1.18750 0 1 0 0 0 1 0 0 1.18125 0 1 0 0 0 1 0 1 1.17500 0 1 0 0 0 1 1 0 1.16875 0 1 0 0 0 1 1 1 1.16250 0 1 0 0 1 0 0 0 1.15625 0 1 0 0 1 0 0 1 1.15000 0 1 0 0 1 0 1 0 1.14375 0 1 0 0 1 0 1 1 1.13750 0 1 0 0 1 1 0 0 1.13125 0 1 0 0 1 1 0 1 1.12500 0 1 0 0 1 1 1 0 1.11875 0 1 0 0 1 1 1 1 1.11250 0 1 0 1 0 0 0 0 1.10625 0 1 0 1 0 0 0 1 1.10000 0 1 0 1 0 0 1 0 http://onsemi.com 15 ADP3290 VR11.1 VID Codes OUTPUT(V) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 1.09375 0 1 0 1 0 0 1 1 1.08750 0 1 0 1 0 1 0 0 1.08125 0 1 0 1 0 1 0 1 1.07500 0 1 0 1 0 1 1 0 1.06875 0 1 0 1 0 1 1 1 1.06250 0 1 0 1 1 0 0 0 1.05625 0 1 0 1 1 0 0 1 1.05000 0 1 0 1 1 0 1 0 1.04375 0 1 0 1 1 0 1 1 1.03750 0 1 0 1 1 1 0 0 1.03125 0 1 0 1 1 1 0 1 1.02500 0 1 0 1 1 1 1 0 1.01875 0 1 0 1 1 1 1 1 1.01250 0 1 1 0 0 0 0 0 1.00625 0 1 1 0 0 0 0 1 1.00000 0 1 1 0 0 0 1 0 0.99375 0 1 1 0 0 0 1 1 0.98750 0 1 1 0 0 1 0 0 0.98125 0 1 1 0 0 1 0 1 0.97500 0 1 1 0 0 1 1 0 0.96875 0 1 1 0 0 1 1 1 0.96250 0 1 1 0 1 0 0 0 0.95625 0 1 1 0 1 0 0 1 0.95000 0 1 1 0 1 0 1 0 0.94375 0 1 1 0 1 0 1 1 0.93750 0 1 1 0 1 1 0 0 0.93125 0 1 1 0 1 1 0 1 0.92500 0 1 1 0 1 1 1 0 0.91875 0 1 1 0 1 1 1 1 0.91250 0 1 1 1 0 0 0 0 0.90625 0 1 1 1 0 0 0 1 0.90000 0 1 1 1 0 0 1 0 0.89375 0 1 1 1 0 0 1 1 0.88750 0 1 1 1 0 1 0 0 0.88125 0 1 1 1 0 1 0 1 0.87500 0 1 1 1 0 1 1 0 0.86875 0 1 1 1 0 1 1 1 0.86250 0 1 1 1 1 0 0 0 0.85625 0 1 1 1 1 0 0 1 0.85000 0 1 1 1 1 0 1 0 0.84375 0 1 1 1 1 0 1 1 0.83750 0 1 1 1 1 1 0 0 0.83125 0 1 1 1 1 1 0 1 0.82500 0 1 1 1 1 1 1 0 0.81875 0 1 1 1 1 1 1 1 0.81250 1 0 0 0 0 0 0 0 0.80625 1 0 0 0 0 0 0 1 0.80000 1 0 0 0 0 0 1 0 0.79375 1 0 0 0 0 0 1 1 0.78750 1 0 0 0 0 1 0 0 http://onsemi.com 16 ADP3290 VR11.1 VID Codes OUTPUT(V) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 0.78125 1 0 0 0 0 1 0 1 0.77500 1 0 0 0 0 1 1 0 0.76875 1 0 0 0 0 1 1 1 0.76250 1 0 0 0 1 0 0 0 0.75625 1 0 0 0 1 0 0 1 0.75000 1 0 0 0 1 0 1 0 0.74375 1 0 0 0 1 0 1 1 0.73750 1 0 0 0 1 1 0 0 0.73125 1 0 0 0 1 1 0 1 0.72500 1 0 0 0 1 1 1 0 0.71875 1 0 0 0 1 1 1 1 0.71250 1 0 0 1 0 0 0 0 0.70625 1 0 0 1 0 0 0 1 0.70000 1 0 0 1 0 0 1 0 0.69375 1 0 0 1 0 0 1 1 0.68750 1 0 0 1 0 1 0 0 0.68125 1 0 0 1 0 1 0 1 0.67500 1 0 0 1 0 1 1 0 0.66875 1 0 0 1 0 1 1 1 0.66250 1 0 0 1 1 0 0 0 0.65625 1 0 0 1 1 0 0 1 0.65000 1 0 0 1 1 0 1 0 0.64375 1 0 0 1 1 0 1 1 0.63750 1 0 0 1 1 1 0 0 0.63125 1 0 0 1 1 1 0 1 0.62500 1 0 0 1 1 1 1 0 0.61875 1 0 0 1 1 1 1 1 0.61250 1 0 1 0 0 0 0 0 0.60625 1 0 1 0 0 0 0 1 0.60000 1 0 1 0 0 0 1 0 0.59375 1 0 1 0 0 0 1 1 0.58750 1 0 1 0 0 1 0 0 0.58125 1 0 1 0 0 1 0 1 0.57500 1 0 1 0 0 1 1 0 0.56875 1 0 1 0 0 1 1 1 0.56250 1 0 1 0 1 0 0 0 0.55625 1 0 1 0 1 0 0 1 0.55000 1 0 1 0 1 0 1 0 0.54375 1 0 1 0 1 0 1 1 0.53750 1 0 1 0 1 1 0 0 0.53125 1 0 1 0 1 1 0 1 0.52500 1 0 1 0 1 1 1 0 0.51875 1 0 1 0 1 1 1 1 0.51250 1 0 1 1 0 0 0 0 0.50625 1 0 1 1 0 0 0 1 0.50000 1 0 1 1 0 0 1 0 OFF 1 1 1 1 1 1 1 0 OFF 1 1 1 1 1 1 1 1 http://onsemi.com 17 ADP3290 Application Information The design parameters for a typical Intel VRD 11.1 compliant CPU application are as follows: • Input voltage (VIN) = 12 V • VID setting voltage (VVID) = 1.400 V • Duty cycle (D) = 0.117 • Nominal output voltage at no load (VONL) = 1.381 V • Nominal output voltage at 115 A load (VOFL) = 1.266 V • Static output voltage drop based on a 1.0 m load line (RO) from no load to full load (VD) = VONL − VOFL = 1.381 V − 1.266 V = 115 mV • Maximum output current (IO) = 130 A • Maximum output current step (IO) = 95 A • Maximum output current slew rate (SR) = 200 A/s • Number of phases (n) = 4 • Switching frequency per phase (fSW) = 450 kHz Current Limit Latchoff Delay Times The startup and current limit delay times are determined by the capacitor connected to the DELAY pin. The first step is to set CDLY for the TD1, TD3, and TD5 delay times (see Figure 5). The DELAY ramp (IDELAY) is generated using a 15 A internal current source. The value for CDLY can be approximated using: C DLY + I DELAY The ADP3290 uses a fixed frequency control architecture. The frequency is set by an external timing resistor (RT). The clock frequency and the number of phases determine the switching frequency per phase, which relates directly to switching losses as well as the sizes of the inductors, the input capacitors, and output capacitors. With n = 4 for four phases, a clock frequency of 18 MHz sets the switching frequency (fSW) of each phase to 450 kHz, which represents a practical trade off between the switching losses and the sizes of the output filter components. Figure 3 shows that to achieve a 1.32 MHz oscillator frequency, the correct value for RT is 130 k. Alternatively, the value for RT can be calculated using: n f SW 1 4.3 pF * 17 k Inductor Selection The choice of inductance for the inductor determines the ripple current in the inductor. Less inductance leads to more ripple current, which increases the output ripple voltage and conduction losses in the MOSFETs. However, using smaller inductors allows the converter to meet a specified peak−to−peak transient deviation with less total output capacitance. Conversely, a higher inductance means lower ripple current and reduced conduction losses, but more output capacitance is required to meet the same peak−to−peak transient deviation. In any multiphase converter, a practical value for the peak−to−peak inductor ripple current is less than 50% of the maximum dc current in the same inductor. Equation 4 shows the relationship between the inductance, oscillator frequency, and peak−to−peak ripple current in the inductor. (eq. 1) where 4.3 pF is the internal IC component values. For good initial accuracy and frequency stability, a 1% resistor is recommended. IR + Soft−Start Delay Time C SS + 15 A V VID (1 * D) f SW L (eq. 4) Equation 5 can be used to determine the minimum inductance based on a given output ripple voltage. The value of CSS sets the soft-start time. The ramp is generated with a 15 A internal current source. The value for CSS can be found using: TD2 V BOOT (eq. 3) where TD(x) is the desired delay time for TD1, TD3, and TD5. The DELAY threshold voltage (VDELAY(TH)) is given as 1.7 V. In this example, 2 ms is chosen for all three delay times, which meets Intel specifications. Solving for CDLY gives a value of 17.6 nF. The closest standard value for CDLY is 18 nF. When the ADP3290 enters current limit, the internal current source changes from 15 A to 3.75 A. This makes the latchoff delay time four times longer than the startup delay time. Longer latchoff delay times can be achieved by placing a resistor in parallel with CDLY. Setting the Clock Frequency RT + TD(x) V DELAY(TH) Lw (eq. 2) V VID RO f SW (1 * (n V RIPPLE D)) (eq. 5) Solving Equation 5 for an 8 mV p−p output ripple voltage yields: where TD2 is the desired soft−start time, and VBOOT is internally set to 1.0 V. Assuming a desired TD2 time of 2.5 ms, CSS is 37.5 nF. The closest standard value for CSS is 39 nF. Although CSS also controls the time delay for TD4 (determined by the final VID voltage), the minimum specification for TD4 is 0 ns. This means that as long as the TD2 time requirement is met, TD4 is within the specification. Lw 1.4 V 1.0 m (1 * 0.468) + 166 nH 450 kHz 10 mV If the resulting ripple voltage is less than what is designed for, the inductor can be made smaller until the ripple value is met. This allows optimal transient response and minimum output decoupling. http://onsemi.com 18 ADP3290 increases. The specified voltage drop corresponds to a dc output resistance (RO), also referred to as a load line. The ADP3290 has the flexibility of adjusting RO, independent of current limit or compensation components, and it can also support CPUs that do not require a load line. For designs requiring a load line, the impedance gain of the CS amplifier (RCSA) must be to be greater than or equal to the load line. All designs, whether they have a load line or not, should keep RCSA ≥ 1 m. The output current is measured by summing the voltage across each inductor and passing the signal through a low−pass filter. This summer filter is the CS amplifier configured with resistors RPH(X) (summers), and RCS and CCS (filter). The impedance gain of the regulator is set by the following equations, where RL is the DCR of the output inductors: The smallest possible inductor should be used to minimize the number of output capacitors. For this example, choosing a 220 nH inductor is a good starting point and gives a calculated ripple current of 12.5 A. The inductor should not saturate at the peak current of 38.7 A and should be able to handle the sum of the power dissipation caused by the average current of 32.5 A in the winding and core loss. Another important factor in the inductor design is the dc resistance (DCR), which is used for measuring the phase currents. A large DCR can cause excessive power losses, though too small a value can lead to increased measurement error. A good rule is to have the DCR (RL) be about 1 to 1.5 times the droop resistance (RO). This example uses an inductor with a DCR of 0.57 m. Designing an Inductor Once the inductance and DCR are known, the next step is to either design an inductor or to find a standard inductor that comes as close as possible to meeting the overall design goals. It is also important to have the inductance and DCR tolerance specified to control the accuracy of the system. Reasonable tolerances most manufacturers can meet are 15% inductance and 7% DCR at room temperature. The first decision in designing the inductor is choosing the core material. Several possibilities for providing low core loss at high frequencies include the powder cores (from Micrometals, Inc., for example, or Kool Mu® from Magnetics®) and the gapped soft ferrite cores (for example, 3F3 or 3F4 from Philips®). Low frequency powdered iron cores should be avoided due to their high core loss, especially when the inductor value is relatively low and the ripple current is high. The best choice for a core geometry is a closed−loop type such as a potentiometer core (PQ, U, or E core) or toroid. A good compromise between price and performance is a core with a toroidal shape. Many useful magnetics design references are available for quickly designing a power inductor, such as: • Intusoft Magnetic Designer Software • Designing Magnetic Components for High Frequency DC to DC Converters, by William T. McLyman, Kg Magnetics, Inc., ISBN 1883107008 R CSA + C CS + R CS R PH(x) RL L RL R CS (eq. 6) (eq. 7) The user has the flexibility to choose either RCS or RPH(X). However, it is best to select RCS equal to 110 k, and then solve for RPH(X) by rearranging Equation 6. Here, RCSA = RO = 1 m because this is equal to the design load line. R PH(x) + RL R CSA R PH(x) + 0.57 m 1.0 m R CS 110 k + 63 k Next, use Equation 7 to solve for CCS. C CS + 220 nH + 35 nF 0.57 m 110 m It is best to have a dual location for CCS in the layout so that standard values can be used in parallel to get as close to the desired value. For best accuracy, CCS should be a 5% or 10% NPO capacitor. This example uses a 5% combination for CCS of one 1.8 nF capacitor and one 1.5nF capacitor in parallel. Recalculating RCS and RPH(X) using this capacitor combination yields 108.8 k and 62 k. The closest standard 1% value for RPH(X) is 61.9 k. When the inductor DCR is used as the sense element and copper wire is used as the source of the DCR, the user needs to compensate for temperature changes of the inductor’s winding. Fortunately, copper has a well known temperature coefficient (TC) of 0.39%/°C. If RCS is designed to have an opposite and equal percentage change in resistance to that of the wire, it cancels the temperature variation of the inductor DCR. Due to the nonlinear nature of NTC thermistors, Resistor RCS1 and Resistor RCS2 are needed. See Figure 10 to linearize the NTC and produce the desired temperature tracking. Selecting a Standard Inductor The following power inductor manufacturers can provide design consultation and deliver power inductors optimized for high power applications upon request. • Coilcraft® • Coiltronics® • Sumida Corporation® Current Sense Amplifier Most designs require the regulator output voltage, measured at the CPU pins, to drop when the output current http://onsemi.com 19 ADP3290 PLACE AS CLOSE AS POSSIBLE TO NEAREST INDUCTOR OR LOW−SIDE MOSFET 5. Calculate values for RCS1 and RCS2 using Equation 12 and 13. R TH R PH1 R PH2 R PH3 R PH4 ADP3290 CSCOMP CSSUM CSREF R CS1 R CS2 KEEP THIS PATH AS SHORT AS POSSIBLE AND WELL AWAY FROM SWITCH NODE LINES C CS2 16 15 Figure 10. Temperature Compensation Circuit Values The following procedure and equations yield values to use for RCS1, RCS2, and RTH (the thermistor value at 25°C) for a given RCS value. 1. Select an NTC based on type and value. Because the value is unknown, use a thermistor with a value close to RCS. The NTC should also have an initial tolerance of better than 5%. 2. Based on the type of NTC, find its relative resistance value at two temperatures. The temperatures that work well are 50°C and 90°C. These resistance values are called A (RTH(50°C))/RTH(25°C)) and B (RTH(90°C))/RTH(25°C)). The relative value of the NTC is always 1 at 25°C. 3. Find the relative value of RCS required for each of these temperatures. This is based on the percentage change needed, which in this example is initially 0.39%/°C. These temperatures are called r1 (1/(1 + TC × (T1 − 25°C))) and r2 (1/(1 + TC × (T2 − 25°C))), where TC = 0.0039 for copper, T1 = 50°C, and T2 = 90°C. From this, r1 = 0.9112 and r2 = 0.7978. 4. Compute the relative values for RCS1, RCS2, and RTH using: r TH + 1 1 * 1 1*r CS2 r CS1 CSCOMP CSSUM CSREF k+ R TH(CALCULATED) r CS2ǓǓ (eq. 13) 17 16 15 R LL1 R LL2 OPTIONAL LOAD LINE SELECT SWITCH LLINE 14 Q LL Figure 11. Load Line Setting Resistors The two resistors RLL1 and RLL2 set up a divider between the CSCOMP pin and CSREF pin. This resistor divider is input into the LLSET pin to set the load line slope RO of the VR according to the following equation: RO + (eq. 9) R LL2 R LL1 ) R LL2 R CSA (eq. 14) The resistor values for RLL1 and RLL2 are limited by two factors. • The minimum value is based upon the loading of the CSCOMP pin. This pin’s drive capability is 500 A and the majority of this should be allocated to the CSA feedback. If the current through RLL1 and RLL2 is limited to 10% of this (50 A), the following limit can be placed for the minimum value for RLL1 and RLL2: (eq. 10) Calculate RTH = rTH × RCS, then select the closest value of thermistor available. Also, compute a scaling factor (k) based on the ratio of the actual thermistor value used relative to the computed one. R TH(ACTUAL) ǒ(1 * k) ) ǒk ADP3290 (eq. 8) 1 A * 1*r CS2 r 1*r CS2 R CS2 + R CS (eq. 12) For load line values greater than 1 m, RCSA can be set equal to RO, and the LLSET pin can be directly connected to the CSCOMP pin. When the load line value needs to be less than 1 m, two additional resistors are required. Figure 11 shows the placement of these resistors. (A * B)xr 1xr 2 * A (1 * B)xr 2 ) B (1 * A) xr 1 A (1 * B)xr 1 * B (1 * A)xr 2 * (A * B) r CS1 + r CS1 Load Line Setting r CS2 + (1 * A) k In this example, RCS is calculated to be 114 k. Look for an available 100 k thermistor, 0603 size. One such thermistor is the Vishay NTHS0603N01N1003JR NTC thermistor with A = 0.3602 and B = 0.09174. From these values, rCS1 = 0.3795, rCS2 = 0.7195, and rTH = 1.075. Solving for RTH yields 122.55 k, so 100 k is chosen, making k = 0.816. Next, find RCS1 and RCS2 to be 35.3 k and 87.9 k. Finally, choose the closest 1% resistor values, which yield a choice of 35.7 k and 88.7 k. 17 C CS1 R CS1 + R CS R LL1 ) R LL2 w (eq. 11) http://onsemi.com 20 I LIM 50 R CSA 10 *6 (eq. 15) ADP3290 To determine the minimum amount of ceramic capacitance required, start with a worst case load step occurring right after a switching cycle has stopped. The ceramic capacitance then delivers the charge to the load while the load is ramping up and until the VR has responded with the next switching cycle. Equation 19 gives the designer a rough approximation for determining the minimum ceramic capacitance. Due to the complexity of the PCB parasitics and bulk capacitors, the actual amount of ceramic capacitance required can vary. Here, ILIM is the current limit current, which is the maximum signal level that the CSA responds to. It is best to select the resistor values to minimize their values to reduce the noise and parasitic susceptibility of the feedback path. By combining Equation 14 with Equation 15 and selecting minimum values for the resistors, the following equations result: R LL2 + I LIM R O 50 A R LL1 + ǒ (eq. 16) Ǔ R CSA *1 RO R LL2 C Z(MIN) w 1 RO (eq. 17) Another useful feature for some VR applications is the ability to select different load lines. Figure 11 shows an optional MOSFET switch that allows this feature. Here, design for RCSA = RO(MAX) (selected with QLL on) and then use Equation 14 to set RO = RO(MIN) (selected with QLL off). For this design, RCSA = RO = 1 m. As a result, connect LLSET directly to CSCOMP; the RLL1 and RLL2 resistors are not needed. The Intel specification requires that at no load the nominal output voltage of the regulator be offset to a value lower than the nominal voltage corresponding to the VID code. The offset is set by a constant current source flowing out of the FB pin (IFB) and flowing through RB. The value of RB can be found using Equation 18. V VID * V ONL I FB 1 f SW ǒ1n * DǓ * 2SIO ƫ (eq. 19) R The typical ceramic capacitors consist of multiple 10 F or 22 F capacitors. For this example, Equation 19 yields 180.8 F, so eighteen, 22 F ceramic capacitors suffice. Next, there is an upper limit imposed on the total amount of bulk capacitance (CX) when the user considers the VID OTF voltage stepping of the output (voltage step VV in time tV with error of VERR). A lower limit is based on meeting the capacitance for load release for a given maximum load step (IO) and a maximum allowable overshoot. The total amount of load release voltage is given as VO = IO × RO + Vrl, where Vrl is the maximum allowable overshoot voltage. Output Offset RB + ƪ C X(MAX) v L nK 2R 2O (eq. 18) VV V VID Ǹ ȡ ȧ Ȣ 1 ) tV VV ǒ Ǔ where : K + * 1n 1.4 V * 1.381 V RB + + 1.27 k 15 A ǒ V VID V ERR VV Ǔ ȣȧ nKR O L 2 * 1 * CZ Ȥ (eq. 20) To meet the conditions of these equations and transient response, the ESR of the bulk capacitor bank (RX) should be less than two times the droop resistance (RO). If the CX(MIN) is larger than CX(MAX), the system cannot meet the VID OTF specification and can require the use of a smaller inductor or more phases (and may have to increase the switching frequency to keep the output ripple the same). This example uses 18, 22 F 1206 MLC capacitors (CZ = 396 F). The VID OTF step change is 1.1V in 233.75 s with a settling error of 5 mV. The maximum allowable load release overshoot for this example is 50 mV, therefore, solving for the bulk capacitance yields. The closest standard 1% resistor value is 1.21 k. The required output decoupling for the regulator is typically recommended by Intel for various processors and platforms. Use some simple design guidelines to determine the requirements. These guidelines are based on having both bulk capacitors and ceramic capacitors in the system. First, select the total amount of ceramic capacitance. This is based on the number and type of capacitor to be used. The best location for ceramic capacitors is inside the socket, with 12 to 18, 1206 size being the physical limit. Other capacitors can be placed along the outer edge of the socket as well. http://onsemi.com 21 ADP3290 C X(MIN) C X(MIN) ȡ wȧ ȧn Ȣ ǒ ȡ wȧ ȧ Ȣ4 C X(MAX) v L IO Ǔ ǒ 4 V VID 95 A 50 mV 1.0 m ) 95 A 220 nH 5.39 2 (eq. 21) Z V rl RO ) IO 220 nH ȣ *C ȧ ȧ Ȥ Ǔ ȣ * 396 Fȧ+ 2.08mF ȧ 1.4 V Ȥ 1.1 V ǒ1.0 mǓ 2 1.4 V Ǹ ȡ ȧ Ȣ 1) ǒ233.75 s (eq. 22) 1.4 V 1.1 V 4 5.39 220 nH 1.0 m Ǔ * 1ȣȧ 2 Ȥ (eq. 23) * 396 F + 41.5 mF current divided by the total number of MOSFETs (nSF). With conduction losses being dominant, Equation 25 shows the total power that is dissipated in each synchronous MOSFET in terms of the ripple current per phase (IR) and average total output current (IO). where K = 5.39. Using 8, 560 F Al−Poly capacitors with a typical ESR of 5 m each yields CX = 4.48 mF with an RX = 0.6 m. One last check should be made to ensure that the ESL of the bulk capacitors (LX) is low enough to limit the high frequency ringing during a load change. This is tested using: LX v CZ R 2O L Z v 396 F Q2 ǒ1 mǓ P SF + (1 * D) (eq. 24) 2 ƪǒ Ǔ IO n SF 2 ) 1 12 ǒ Ǔƫ nI R n SF 2 R DS(SF) (eq. 25) 4 + 528 pH 3 Knowing the maximum output current being designed for and the maximum allowed power dissipation, the user can find the required RDS(ON) for the MOSFET. For D−PAK MOSFETs up to an ambient temperature of 50°C, a safe limit for PSF is 1 W to 1.5 W at 120°C junction temperature. Thus, for this example (115 A maximum), RDS(SF) (per MOSFET) < 8.5 m. This RDS(SF) is also at a junction temperature of about 120°C. As a result, users need to account for this when making this selection. This example uses two lower−side MOSFETs at 10.5 m, each at 120°C. Another important factor for the synchronous MOSFET is the input capacitance and feedback capacitance. The ratio of the feedback to input needs to be small (less than 10% is recommended) to prevent accidental turn−on of the synchronous MOSFETs when the switch node goes high. Also, the time to switch the synchronous MOSFETs off should not exceed the non−overlap dead time of the MOSFET driver (40 ns typical for the ADP3120A). The output impedance of the driver is approximately 2 , and the typical MOSFET input gate resistances are about 1 to 2 . Therefore, a total gate capacitance of less than 6000 pF should be adhered to. Because two MOSFETs are in parallel, the input capacitance for each synchronous MOSFET should be limited to 3000 pF. The high−side (main) MOSFET has to be able to handle two main power dissipation components: conduction and switching losses. The switching loss is related to the amount where Q2 is limited to 4/3 to ensure a critically damped system. In this example, LX is approximately 250 pH for the 8, Al−Poly capacitors, which satisfies this limitation. If the LX of the chosen bulk capacitor bank is too large, the number of ceramic capacitors needs to be increased, or lower ESL bulks need to be used if there is excessive undershoot during a load transient. For this multi−mode control technique, all ceramic designs can be used providing the conditions of Equation 19 through Equation 24 are satisfied. Power MOSFETs For this example, the N−channel power MOSFETs have been selected for one high−side switch and two low−side switches per phase. The main selection parameters for the power MOSFETs are VGS(TH), QG, CISS, CRSS, and RDS(ON). The minimum gate drive voltage (the supply voltage to the ADP3120A dictates whether standard threshold or logic−level threshold MOSFETs must be used. With VGATE ~10 V, logic−level threshold MOSFETs (VGS(TH) < 2.5 V) are recommended. The maximum output current (IO) determines the RDS(ON) requirement for the low−side (synchronous) MOSFETs. With the ADP3290, currents are balanced between phases, thus, the current in each low−side MOSFET is the output http://onsemi.com 22 ADP3290 dissipation limit. See the ADP3120A data sheet for more details. of time it takes for the main MOSFET to turn on and off, and to the current and voltage that are being switched. Basing the switching speed on the rise and fall time of the gate driver impedance and MOSFET input capacitance, Equation 26 provides an approximate value for the switching loss per main MOSFET, where nMF is the total number of main MOSFETs. P S(MF) + 2 f SW V CC I O n MF RG n MF n Ramp Resistor Selection The ramp resistor (RR) is used for setting the size of the internal PWM ramp. The value of this resistor is chosen to provide the best combination of thermal balance, stability, and transient response. Equation 29 is used for determining the optimum value. C ISS (eq. 26) RR + where RG is the total gate resistance (2 for the ADP3120A and about 1 for typical high speed switching MOSFETs, making RG = 3 ), and CISS is the input capacitance of the main MOSFET. Adding more main MOSFETs (nMF) does not help the switching loss per MOSFET because the additional gate capacitance slows switching. Use lower gate capacitance devices to reduce switching loss. The conduction loss of the main MOSFET is given by the following, where RDS(MF) is the on resistance of the MOSFET: P C(MF) + D ƪǒ Ǔ IO n MF 2 ) 1 12 ǒ n Ǔƫ IR n MF RR + 3 AR L A D R DS 3 0.5 220 nH + 367 k 5 4 m 5 pF CR where: AR is the internal ramp amplifier gain. AD is the current balancing amplifier gain. RDS is the total low−side MOSFET on resistance. CR is the internal ramp capacitor value. Another requirement also needs to be satisfied: IRAMP < ICLAMP (200A/3), thus: 2 R DS(MF) RR w AR ǒVCC * VVIDǓ I CLAMP + 0.5 (12 * 1.4) V + 79 K 66.7 A (eq. 27) (eq. 30) Typically, for main MOSFETs, the highest speed (low CISS) device is preferred, but these usually have higher on resistance. Select a device that meets the total power dissipation (about 1.5 W for a single D−PAK) when combining the switching and conduction losses. For this example, an BSC100N03L is selected as the main MOSFET (eight total; nMF = 4), with CISS = 1000 pF (maximum) and RDS(MF) = 11 m (maximum at TJ = 120°C). An IPD09N03L is selected as the synchronous MOSFET (eight total; nSF = 8), with CISS = 1600 pF (maximum) and RDS(SF) = 10.5 m (maximum at TJ = 120°C). The synchronous MOSFET CISS is less than 3000 pF, satisfying this requirement. Solving for the power dissipation per MOSFET at IO = 115 A and IR = 7.5 A yields 1.9 W for each synchronous MOSFET and 2.0 W for each main MOSFET. Finally, consider the power dissipation in the driver for each phase. This is best expressed as QG for the MOSFETs and is given by Equation 28, where QGMF is the total gate charge for each main MOSFET and QGSF is the total gate charge for each synchronous MOSFET. P DRV + ƪ f SW 2 n ǒn MF Q GMF ) n SF ƫ Q GSFǓ ) I CC (eq. 29) Since above RR value is bigger than 79 k, it keeps the value of The internal ramp voltage magnitude can be calculated by using: VR + A R (1 * D) V VID R R C R f SW (eq. 31) 0.5 (1 * 0.117) 1.4 V VR + + 748 mV 367 k 5 pF 450 kHz The size of the internal ramp can be made larger or smaller. If it is made larger, stability and noise rejection improves, but transient degrades. Likewise, if the ramp is made smaller, transient response improves at the sacrifice of noise rejection and stability. The factor of 3 in the denominator of Equation 29 sets a ramp size that gives an optimal balance for good stability, transient response, and thermal balance. Comp Pin Ramp A ramp signal on the COMP pin is due to the droop voltage and output voltage ramps. This ramp amplitude adds to the internal ramp to produce the following overall ramp signal at the PWM input: V CC V RT + (eq. 28) Also shown is the standby dissipation factor (ICC × VCC) of the driver. For the ADP3120A, the maximum dissipation should be less than 400 mW. In this example, with ICC = 7 mA, QGMF = 13 nC, and QGSF = 15 nC, there is 200 mW in each driver, which is below the 400 mW ǒ VR 1* Ǔ 2 ǒ1*n DǓ n f SW C X R O (eq. 32) In this example, the overall ramp signal is 0.862 V. If the ramp size is smaller than 0.5 V, increase the ramp size to be at least 0.5 V by decreasing the ramp resistor for noise immunity. http://onsemi.com 23 ADP3290 Current Limit Setpoint IMON Setpoint To select the current limit setpoint, first find the resistor value for RLIM. The current limit threshold for the ADP3290 is set with a constant current source (IILIM = 4/3*IREF) flowing out of the ILIM pin, which sets up a voltage (VLIM) across RLIM. Thus, increasing RLIM now increases the current limit. RLIM can be found using: R LIM + I R CS V LIM + LIM 4 I ILIM V REF 3 DCR R REF R PH According to the function definition, IMON output voltage should represent the load condition within the whole load current range. The formula below will result RIMON in need: R IMON + I PHMAX + V COMP(MAX) * V BIAS V RT D MAX f SW ǒV IN * V VIDǓ L Feedback Loop Compensation Design Optimized compensation of the ADP3290 allows the best possible response of the regulator output to a load change. The basis for determining the optimum compensation is to make the regulator and output decoupling appear as an output impedance that is entirely resistive over the widest possible frequency range, including dc, and equal to the droop resistance (RO). With the resistive output impedance, the output voltage droops in proportion to the load current at any load current slew rate. This ensures optimal positioning and minimizes the output decoupling. Because of the multi−mode feedback structure of the ADP3290, the feedback compensation must be set to make the converter output impedance work in parallel with the output decoupling to make the load look entirely resistive. Compensation is needed for several poles and zeros created by the output inductor and the decoupling capacitors (output filter). A type−three compensator on the voltage feedback is adequate for proper compensation of the output filter. Equation 38 to Equation42 are intended to yield an optimal starting point for the design; some adjustments may be necessary to account for PCB and component parasitic effects (see the Tuning the ADP3290 section). (eq. 34) (eq. 35) For the ADP3290, the maximum COMP voltage (VCOMP(MAX)) is 4.4 V and the COMP pin bias voltage (VBIAS) is 1.2 V. In this example, the maximum duty cycle is 0.433 and the peak current is 46.4 A. The limit of the peak per−phase current described earlier during the secondary current limit is determined by: I PHLIM + V COMP(CLAMPED) * V BIAS AD R DS(MAX) (eq. 37) Here, IL is the total load current, M =10 is the current gain for IMON. Since IMON output clamp voltage is around 1.1 V, VIMON is selected as 0.8V when IL = IMAX (130A). While RLIM = 7.5 k, RIMON is calculated as 5 k, for which 4.99 k is chosen as the nearest 1% value. There is a capacitor (CIMON) in parallel with RIMON, in order to filter output current ripple. The time constant of RIMON * CIMON should be much bigger (> 10 x) than circuit switching period. In this example, CIMON is selected as 0.1 F. (eq. 33) Here, ILIM is the peak average current limit for the supply output. The peak average current is the dc current limit plus the output ripple current. In this example, choose ILIM_DC =150 A (130% * TDC ) and having a ripple current of 10 A gives an ILIM of 160 A. RCS is selected as 110 k in this example, RPH is 68.1 k, DCR is 0.57 m (Delta THCBR1290−221−R). This results in an RLIM = 7.4 k, for which 7.5 k is chosen as the nearest 1% value. The per−phase initial duty cycle limit and peak current during a load step are determined by: D MAX + D V IMON V R LIM + IMON I IMON M RO IL (eq. 36) For the ADP3290, the current balancing amplifier gain (AD) is 5 and the clamped COMP pin voltage is 3.3 V. Using an RDS(MAX) of 4.5 m (low−side on resistance at 150°C) results in a per−phase peak current limit of 93.3 A. This current level can be reached only with an absolute short at the output, and the current limit latchoff function shuts down the regulator before overheating can occur. First, compute the time constants for all the poles and zeros in the system using Equation 38 to Equation 42. RE + n RO ) AD RE + 4 1 m ) 5 TA + CX R DS ) 5.25 m ) ǒR O * R 1Ǔ ) L X T B + ǒR X ) R 1 * R OǓ R L V RT 2 L (1 * n D) V RT ) V VID n C X R O V VID RO 220 nH (1 * 0.467) 0.862 V + 38.7 m 4 4.48 mF 1 m 1.4 V 0.57 m 0.862 V 2 ) 1.4 V RO * R1 + 4.48 mF RX ǒ1 m * 0.5 mǓ ) 250 pH 1 m C X + ǒ0.6 m ) 0.5 m * 1 mǓ 4.48 mf + 448 ns http://onsemi.com 24 1 m * 0.5 m + 2.45 s 0.6 m (eq. 38) (eq. 39) (eq. 40) ADP3290 V RT TC + TD + ǒ Ǔ AD RDS 2 f SW L* V VID CX CX RE CZ 0.862 V + R 2O ǒR O * R 1Ǔ ) C Z RO ǒ220 nH * 52 1.4 V + 38.7 m 4.48 mF 4.48 mF 5.25 m 450 kHz 396 F Ǔ + 3.04 s ǒ1 mǓ (eq. 41) 2 ǒ1 m * 0.5 mǓ ) 396 F 1 m + 673 ns (eq. 42) where: R’ is the PCB resistance from the bulk capacitors to the ceramics. RDS is the total low−side MOSFET on resistance per phase. In this example, AD is 5, VRT equals 0.862 V, R’ is approximately 0.5 m (assuming a 4−layer, 1 ounce motherboard), and LX is 250 pH for the 8 Al−Poly capacitors. The compensation values can then be solved using: CA + n RO TA 4 1 m + RE RB 38.7 m 2.45 s 1.21 k 209 pF (eq. 43) RA + TC 3.04 s + + 14.5 k CA 209 pF (eq. 44) CB + TB 448 ns + + 370 pF RB 1.21 k (eq. 45) C FB + TD 673 ns + + 46.4 pF RA 14.5 k (eq. 46) Figure 13. Typical Transient Response for Design Example Load Release 1-Vo, 3-COMP, 4-TRDET, D0~D2-PWM1~3 These are the starting values prior to tuning the design that account for layout and other parasitic effects (see the Tuning the ADP3290 section). The final values selected after tuning are: CA = 120 pF CIN Selection and Input Current di/dt Reduction In continuous inductor current mode, the source current of the highside MOSFET is approximately a square wave with a duty ratio equal to n × VOUT/VIN and an amplitude of onenth the maximum output current. To prevent large voltage transients, a low ESR input capacitor, sized for the maximum rms current, must be used. The maximum rms capacitor current is given by: RA = 28 k CB = 120 pF CFB = 3.3 pF Figure 12 and Figure 13 show the typical transient response using these compensation values. I CRMS + D I CRMS + 0.117 IO 115 A ǸN 1 D * 1 Ǹ4 (eq. 47) 1 * 1 + 14.3 A 0.117 The capacitor manufacturer’s ripple−current ratings are often based on only 2000 hours of life. As a result, it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors can be placed in parallel to meet size or height requirements in the design. In this example, the input capacitor bank is formed by three 680 F, 16 V aluminum electrolytic capacitors and twelve 4.7 F ceramic capacitors. To reduce the input current di/dt to a level below the recommended maximum of 0.1 A/s, an additional small inductor (L > 370 nH at 18 A) should be inserted between the converter and the supply bus. This inductor also acts as a filter between the converter and the primary power source. Figure 12. Typical Transient Response for Design Example Load Step http://onsemi.com 25 ADP3290 Thermal Monitor Design RTTSENSE values of 8.98 k for VRFAN and 6.58 k for VRHOT. These values correspond to a thermistor temperature of ~100°C and ~110°C when using the same type of 100 k NTC thermistor used in the current sense amplifier. An additional fixed resistor in parallel with the thermistor allows tuning of the trip point temperatures to match the hottest temperature in the VR, when the thermistor itself is directly sensing a proportionately lower temperature. Setting this resistor value is best accomplished with a variable resistor during thermal validation and then fixing this value for the final design. Additionally, a 0.1 F capacitor should be used for filtering noise. The thermistor is used on the TTSENSE input of the ADP3290 for monitoring the temperature of the VR. A constant current of 123 A is sourced out of this pin and runs through a thermistor network such as the one shown in Figure 14. ADP3290 9 VRHOT 10 TTSNS OPTIONAL TEMPERATURE 0.1mF ADJUST Shunt Resistor Design RESISTOR NEAR CLOSEST PHASE The ADP3290 uses a shunt to generate 5.0 V from the 12 V supply range. A trade off can be made between the power dissipated in the shunt resistor and the UVLO threshold. Figure 15 shows the typical resistor value needed to realize certain UVLO voltages. It also gives the maximum power dissipated in the shunt resistor for these UVLO voltages. R TTSENSE Figure 14. VR Thermal Monitor Circuit A voltage is generated from this current through the thermistor and sensed inside the IC. When the voltage reaches 1.105V, the VRFAN output gets set. When the voltage reaches 0.81 V, the VRHOT gets set. This corresponds to 550 0.50 500 0.45 RSHUNT () 450 400 0.40 PSHUNT RSHUNT 0.35 350 0.30 300 0.25 250 0.20 200 0.15 150 7.0 8.0 7.5 9.0 8.5 10.0 9.5 10.5 PSHUNT (W) PLACE THERMISTOR 0.10 11.0 VIN (UVLO) Figure 15. Typical Shunt Resistor Value and Power Dissipation for Different UVLO Voltage The maximum power dissipated is calculated using Equation 48. P MAX + ǒVIN(MAX) * VCC(MIN)Ǔ R SHUNT The CECC standard specification for power rating in surface mount resistors is: 0603 = 0.1 W, 0805 = 0.125 W, 1206 = 0.25 W. 2 (eq. 48) Tuning the ADP3290 1. Build a circuit based on the compensation values computed from the design spreadsheet. 2. Hook up the dc load to the circuit, turn it on, and verify its operation. Also, check for jitter at no load and full load. where: VIN(MAX) is the maximum voltage from the 12 V input supply (if the 12 V input supply is 12 V ± 5%, VIN(MAX) = 12.6 V; if the 12 V input supply is 12 V ± 10%, VIN(MAX) = 13.2 V). VCC(MIN) is the minimum VCC voltage of the ADP3290. This is specified as 4.75 V. RSHUNT is the shunt resistor value. http://onsemi.com 26 ADP3290 DC Load Line Setting for each change, and then average to get the overall load line slope (ROMEAS). 7. If ROMEAS is off from RO by more than 0.05 m, use Equation 50 to adjust the RPH values. 3. Measure the output voltage at no load (VNL). Verify that it is within tolerance. 4. Measure the output voltage at full load cold (VFLCOLD). Let the board sit for ~10 minutes at full load, and then measure the output (VFLHOT). If there is a change of more than a few mV, adjust RCS1 and RCS2 using Equation 49 and Equation 51. R CS2(NEW) + R CS2(OLD) V NL * V FLCOLD V NL * V FLHOT R CS2(NEW) + R CS2(OLD) (eq. 49) 1 R CS1(OLD))R TH(25oC) R CS1(OLD) (eq. 50) 8. Repeat Step 6 and Step 7 to check the load line. Repeat adjustments if necessary. 9. When the dc load line adjustment is complete, do not change RPH, RCS1, RCS2, or RTH for the remainder of the procedure. 10. Measure the output ripple at no load and full load with a scope, and make sure it is within specifications. 5. Repeat Step 4 until the cold and hot voltage measurements remain the same. 6. Measure the output voltage from no load to full load using 5 A steps. Compute the load line slope R CS1(NEW) + R OMEAS RO R TH(25oC))ǒR CS1(OLD)*R CS1(NEW)Ǔ ǒRCS1(OLD)*RTH(25 C)Ǔ * o AC Load Line Setting 1 R TH(25oC) (eq. 51) values are available. It is a good idea to have locations for two capacitors in the layout for this. 11. Remove the dc load from the circuit and hook up the dynamic load. 12. Hook up the scope to the output voltage and set it to dc coupling with the time scale at 100 s/div. 13. Set the dynamic load for a transient step of about 40 A at 1 kHz with 50% duty cycle. 14. Measure the output waveform (use dc offset on scope to see the waveform). Try to use a vertical scale of 100 mV/div or finer. This waveform should look similar to Figure 16. R CS(NEW) + R CS(OLD) V ACDRP V DCDRP (eq. 52) 17. Repeat Step 11 to Step 13 and repeat the adjustments, if necessary. Once complete, do not change CCS for the remainder of the procedure. Set the dynamic load step to maximum step size. Do not use a step size larger than needed. Verify that the output waveform is square, which means that VACDRP and VDCDRP are equal. Initial Transient Setting 18. With the dynamic load still set at the maximum step size, expand the scope time scale to either 2 s/div or 5 s/div. The waveform can have two overshoots and one minor undershoot (see Figure 17). Here, VDROOP is the final desired value. VACDRP VDCDRP VDROOP Figure 16. AC Load Line Waveform 15. Use the horizontal cursors to measure VACDRP and VDCDRP as shown in Figure 16. Do not measure the undershoot or overshoot that happens immediately after this step. 16. If VACDRP and VDCDRP are different by more than a few millivolts, use Equation 51 to adjust CCS. Users may need to parallel different values to get the right one because limited standard capacitor VTRAN1 VTRAN2 Figure 17. Transient Setting Waveform http://onsemi.com 27 ADP3290 interconnection traces in the remainder of the power delivery current paths. Keep in mind that each square unit of 1 ounce copper trace has a resistance of ~0.53 m at room temperature. Whenever high currents must be routed between PCB layers, use vias liberally to create several parallel current paths, so the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. If critical signal lines (including the output voltage sense lines of the ADP3290) must cross through power circuitry, it is best to interpose a signal ground plane between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier. An analog ground plane should be used around and under the ADP3290 as a reference for the components associated with the controller. This plane should be tied to the nearest output decoupling capacitor ground and should not be tied to any other power circuitry to prevent power currents from flowing into it. The components around the ADP3290 should be located close to the controller with short traces. The most important traces to keep short and away from other traces are the FB pin and CSSUM pin. The output capacitors should be connected as close as possible to the load (or connector), for example, a microprocessor core, that receives the power. If the load is distributed, the capacitors should also be distributed and generally be in proportion to where the load tends to be more dynamic. Avoid crossing any signal lines over the switching power path loop described in the Power Circuitry Recommendations sections. 19. If both overshoots are larger than desired, try making the adjustments using the following suggestions: • Make the ramp resistor larger by 25% (RRAMP) • For VTRAN1, increase CB or increase the switching frequency • For VTRAN2, increase RA and decrease CA by 25% If these adjustments do not change the response, the design is limited by the output decoupling. Check the output response every time a change is made, and check the switching nodes to ensure that the response is still stable. 20. For load release (see Figure 18), if VTRANREL is larger than the allowed overshoot, there is not enough output capacitance. Either more capacitance is needed, or the inductor values need to be made smaller. When changing inductors, start the design again using a spreadsheet and this tuning procedure. VTRANREL VDROOP Power Circuitry Recommendations The switching power path should be routed on the PCB to encompass the shortest possible length to minimize radiated switching noise energy (EMI) and conduction losses in the board. Failure to take proper precautions often results in EMI problems for the entire PC system and noise−related operational problems in the power converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors and the power MOSFETs, including all interconnecting PCB traces and planes. Using short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing; and it accommodates the high current demand with minimal voltage loss. When a power dissipating component, for example, a power MOSFET, is soldered to a PCB, it is recommended to liberally use the vias, both directly on the mounting pad and immediately surrounding it. Two important reasons for this are improved current rating through the vias and improved thermal performance from vias extended to the opposite side of the PCB, where a plane can more readily transfer the heat Figure 18. Transient Setting Waveform Because the ADP3290 turns off all of the phases (switches inductors to ground), no ripple voltage is present during load release. Therefore, the user does not have to add headroom for ripple. This allows load release VTRANREL to be larger than VTRAN1 by the amount of ripple, and still meet specifications. If VTRAN1 and VTRANREL are less than the desired final droop, this implies that capacitors can be removed. When removing capacitors, also check the output ripple voltage to make sure it is still within specifications. Layout and Component Placement The following guidelines are recommended for optimal performance of a switching regulator in a PC system. General Requirements For good results, a PCB with at least four layers is recommended. This provides the needed versatility for control circuitry interconnections with optimal placement, power planes for ground, input and output power, and wide http://onsemi.com 28 ADP3290 Signal Circuitry Recommendations to the air. Make a mirror image of any pad being used to heatsink the MOSFETs on the opposite side of the PCB to achieve the best thermal dissipation in the air around the board. To further improve thermal performance, use the largest possible pad area. The output power path should also be routed to encompass a short distance. The output power path is formed by the current path through the inductor, the output capacitors, and the load. For best EMI containment, a solid power ground plane should be used as one of the inner layers extending fully under all the power components. The output voltage is sensed and regulated between the FB pin and the FBRTN pin, which connect to the signal ground at the load. To avoid differential mode noise pickup in the sensed signal, the loop area should be small. Thus, the FB trace and FBRTN trace should be routed adjacent to each other on top of the power ground plane back to the controller. The feedback traces from the switch nodes should be connected as close as possible to the inductor. The CSREF signal should be connected to the output voltage at the nearest inductor to the controller. http://onsemi.com 29 ADP3290 PACKAGE DIMENSIONS LFCSP40 6x6, 0.5P CASE 932AC−01 ISSUE A D NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSIONS: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. A B D1 PIN ONE REFERENCE E1 E DIM A A1 A3 b D D1 D2 E E1 E2 e H K L M 0.20 C TOP VIEW 0.20 C H (A3) 0.10 C A NOTE 4 0.08 C SIDE VIEW A1 C 4X SEATING PLANE MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 6.00 BSC 5.75 BSC 3.95 4.25 6.00 BSC 5.75 BSC 3.95 4.25 0.50 BSC −−− 12 ° 0.20 −−− 0.30 0.50 −−− 0.60 SOLDERING FOOTPRINT* 6.30 M 11 K D2 4X 4.14 M 1 21 PIN 1 INDICATOR 40X 0.63 E2 4.14 40X 6.30 L 1 40 31 e BOTTOM VIEW 40X b 0.10 C A B 0.05 C PACKAGE OUTLINE 40X 0.50 PITCH NOTE 3 0.28 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. FlexMode is a trademark of Analog Devices, Inc. All brand names and product names appearing in this document are registered trademarks or trademarks of their respective holders. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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