BB ADS7810UBE4

ADS7810
®
ADS
781
0
12-Bit 800kHz Sampling CMOS
ANALOG-to-DIGITAL CONVERTER
FEATURES
DESCRIPTION
● 1.25µs THROUGHPUT TIME
● STANDARD ±10V INPUT RANGE
The ADS7810 is a complete 12-bit sampling A/D
using state-of-the-art CMOS structures. It contains a
complete 12-bit capacitor-based SAR A/D with inherent S/H, reference, clock, interface for microprocessor
use, and three-state output drivers.
● 69dB min SINAD WITH 250kHz INPUT
● ±3/4 LSB max INL AND ±1 LSB max DNL
● INTERNAL REFERENCE
● COMPLETE WITH S/H, REF, CLOCK, ETC.
● PARALLEL DATA w/LATCHES
● 28-PIN SOIC
The ADS7810 is specified at an 800kHz sampling
rate, and guaranteed over the full temperature range.
Laser-trimmed scaling resistors provide the industrystandard ±10V input range, while an innovative design
allows operation from ±5V supplies.
The 28-pin ADS7810 is available in a plastic SOIC
fully specified for operation over the industrial –40°C
to +85°C range.
Successive Approximation Register and Control Logic
Clock
CDAC
2450Ω
±10V Input
625Ω
Comparator
Output
Latches
and
Three
State
Drivers
BUSY
Three
State
Parallel
Data
Bus
Cap
18kΩ
Buffer
4.8kΩ
Internal
Ref
2.5V Ref Out/In
8.6kΩ
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1992 Burr-Brown Corporation
PDS-1138E
Printed in U.S.A. March, 1998
SPECIFICATIONS
ELECTRICAL
At TA = –40°C to +85°C, fS = 800kHz, +VDIG = +VANA = +5V, –VANA = –5V, using internal reference and the 50Ω input resistor shown in Figure 4b, unless otherwise specified.
ADS7810U
PARAMETER
CONDITIONS
MIN
TYP
RESOLUTION
ADS7810UB
MAX
MIN
TYP
12
ANALOG INPUT
Voltage Range
Impedance
Capacitance
±10
3.1
5
THROUGHPUT SPEED
Conversion Cycle
Complete Cycle
Throughput Rate
DC ACCURACY
Integral Linearity Error
Differential Linearity Error
No Missing Codes
Transition Noise(2)
Full Scale Error(3, 4)
Full Scale Error Drift
Full Scale Error(3, 4)
Full Scale Error Drift
Bipolar Zero Error(3)
Bipolar Zero Error Drift
Power Supply Sensitivity
(+VDIG = +VANA = VD)
AC ACCURACY
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise+Distortion)
Signal-to-Noise
Usable Bandwidth(6)
SAMPLING DYNAMICS
Aperture Delay
Aperture Jitter
Transient Response
Overvoltage Recovery(7)
REFERENCE
Internal Reference Voltage
Internal Reference DC Source Current
(External load should be static)
Internal Reference Drift
External Reference Voltage Range
For Specified Linearity
External Reference Current Drain
DIGITAL INPUTS
Logic Levels
VIL
VIH
IIL
IIH
t3 + t4
Acquire & Convert
±12
±12
±2
FS Step
2.48
2.3
Ext. 2.5000V Ref
Output Capacitance
ISINK = 1.6mA
ISOURCE = 500µA
High-Z State,
VOUT = 0V to VDIG
High-Z State
+2.8
DIGITAL TIMING
Bus Access Time
Bus Relinquish Time
±0.75
✻
LSB(1)
LSB
✻
±0.5
✻
✻
±8
±4
✻
82
–80
71
71
1.5
✻
✻
77
–74
69
70
84
–82
✻
✻
✻
2.5
100
8
2.5
–77
✻
✻
✻
✻
LSB
%
ppm/°C
%
ppm/°C
LSB
ppm/°C
LSB
LSB
dB(5)
dB
dB
dB
MHz
ns
ps
ns
ns
2.52
✻
✻
✻
✻
2.7
✻
✻
✻
ppm/°C
V
✻
µA
✻
✻
✻
✻
V
V
µA
µA
✻
✻
V
V
µA
15
15
pF
62
83
✻
✻
ns
ns
100
VIL = 0V
VIH = 5V
ns
ns
kHz
±0.25
20
10
200
250
–0.3
+2.4
DIGITAL OUTPUTS
Data Format
Data Coding
VOL
VOH
Leakage Current
±0.5
±5
±0.5
+4.75V < VD < +5.25V
–5.25V < –VANA < –4.75V
67
68
✻
✻
✻
Guaranteed
0.1
74
V
kΩ
pF
✻
±1
±1
250kHz
250kHz
250kHz
250kHz
Bits
✻
1250
800
fIN =
fIN =
fIN =
fIN =
UNITS
✻
✻
✻
✻
1020
Ext. 2.5000V Ref
Ext. 2.5000V Ref
MAX
+0.8
VD + 0.3
±10
±10
✻
✻
Parallel 12 Bits
Binary Two’s Complement
+0.4
✻
±5
V
µA
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
ADS7810
2
SPECIFICATIONS
(CONT)
ELECTRICAL
At TA = –40°C to +85°C, fS = 800kHz, +VDIG = +VANA = +5V, –VANA = –5V, using internal reference and the 50Ω input resistor shown in Figure 4b, unless otherwise specified.
ADS7810U
PARAMETER
CONDITIONS
POWER SUPPLIES
Specified Performance
+VDIG = +VANA
–VANA
+IDIG
+IANA
–I ANA
Derated Performance
+VDIG = +VANA
–VANA
Power Dissipation
TYP
MAX
MIN
TYP
MAX
UNITS
+4.75
–5.25
+5
–5
+16
+16
–13
+5.25
–4.75
✻
✻
✻
✻
✻
✻
✻
✻
✻
V
V
mA
mA
mA
+4.5
–5.5
+5
–5
225
+5.5
–4.5
275
✻
✻
✻
✻
✻
✻
✻
V
V
mW
+85
+125
+150
✻
✻
✻
✻
°C
°C
°C
fS = 800kHz
TEMPERATURE RANGE
Specified Performance
Derated Performance
Storage
Thermal Resistance (θJA)
Plastic DIP
SOIC
ADS7810UB
MIN
–40
–55
–65
°C/W
°C/W
✻
✻
75
75
✻ Specification same as ADS7810U.
NOTES: (1) LSB means Least Significant Bit. For the 12-bit, ±10V input ADS7810, one LSB is 4.88mV. (2) Typical rms noise at worst case transitions and
temperatures. (3) Measured with 50Ω in series with analog input. Adjustable to zero with external potentiometer. (4) Full scale error is the worst case of –Full Scale
or +Full Scale untrimmed deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the
effect of offset error. (5) All specifications in dB are referred to a full-scale ±10V input. (6) Usable Bandwidth defined as Full-Scale input frequency at which Signalto-(Noise+Distortion) degrades to 60dB, or 10 bits of accuracy. (7) Recovers to specified performance after 2 x FS input over voltage.
ELECTROSTATIC
DISCHARGE SENSITIVITY
ABSOLUTE MAXIMUM RATINGS
Analog Inputs: VIN .............................................................................. ±25V
REF .................................... +VANA +0.3V to AGND2 –0.3V
CAP ........................................... Indefinite Short to AGND2
Momentary Short to +VANA
Ground Voltage Differences: DGND, AGND1, AGND2 ................... ±0.3V
+VANA ................................................................................................... +7V
+VDIG to +VANA ................................................................................. +0.3V
+VDIG ..................................................................................................... 7V
–VANA ................................................................................................... –7V
Digital Inputs ............................................................ –0.3V to +VDIG +0.3V
Maximum Junction Temperature ................................................... +165°C
Internal Power Dissipation ............................................................. 825mW
Lead Temperature (soldering, 10s) ................................................ +300°C
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
ORDERING/PACKAGE INFORMATION
PRODUCT
ADS7810U
ADS7810UB
MAXIMUM
INTEGRAL
LINEARITY
ERROR (LSB)
MINIMUM
SIGNAL-TO(NOISE +
DISTORTION)
RATIO (dB)
SPECIFICATION
TEMPERATURE
RANGE
PACKAGE
PACKAGE DRAWING
NUMBER(1)
±1
±0.75
67
69
–40°C to +85°C
–40°C to +85°C
28-Pin SOIC
28-Pin SOIC
217
217
NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book.
®
3
ADS7810
PIN ASSIGNMENTS
DIGITAL
I/O
PIN #
NAME
1
2
3
VIN
AGND1
REF
4
5
6
CAP
AGND2
D11 (MSB)
7
8
9
10
11
12
13
14
15
16
17
18
D10
D9
D8
D7
D6
D5
D4
DGND
D3
D2
D1
D0 (LSB)
19
20
21
22
23
+VANA
+VDIG
DGND
R/C
I
24
CS
I
25
BUSY
O
26
–VANA
27
28
+VDIG
+VANA
O
O
O
O
O
O
O
O
O
O
O
O
DESCRIPTION
Analog Input. Connect via 50Ω to analog input. Full-scale input range is ±10V.
Analog Ground. Used internally as ground reference point. Minimal current flow.
Reference Input/Output. Outputs internal reference of +2.5V nominal. Can also be driven by external system
reference. In both cases, decouple to ground with a 0.1µF ceramic capacitor.
Reference Buffer Output. 10µF tantalum capacitor to ground. Nominally +2V.
Analog Ground.
Data Bit 11. Most Significant Bit (MSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is
LOW, or when a conversion is in progress.
Data Bit 10. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Data Bit 9. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Data Bit 8. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Data Bit 7. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Data Bit 6. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Data Bit 5. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Data Bit 4. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Digital Ground.
Data Bit 3. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Data Bit 2. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Data Bit 1. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Data Bit 0. Least Significant Bit (LSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is
LOW, or when a conversion is in progress.
Not internally connected.
Analog Positive Supply Input. Nominally +5V. Connect directly to pins 21, 27 and 28.
Digital Supply Input. Nominally +5V. Connect directly to pins 20, 27 and 28.
Digital ground.
Read/Convert Input. With CS LOW, a falling edge on R/C puts the internal sample/hold into the hold state and
starts a conversion. With CS LOW and no conversion in progress, a rising edge on R/C enables the output
data bits.
Chip Select. With R/C LOW, a falling edge on CS will initiate a conversion. With
R/C HIGH and no conversion in progress, a falling edge on CS will enable the output data bits.
Busy Output. Falls when a conversion is started, and remains LOW until the conversion is completed and the
data is latched into the output register. With CS LOW and R/C HIGH, output data will be valid when BUSY
rises, so that the rising edge can be used to latch the data.
Analog Negative Supply Input. Nominally –5V. Decouple to ground with 0.1µF ceramic and 10µF tantulum
capacitors.
Digital Supply Input. Nominally +5V. Connect directly to pins 20, 21 and 28.
Analog Positive Supply Input. Nominally +5V. Connect directly to pins 20, 21 and 27, and decouple to ground
with 0.1µF ceramic and 10µF tantulum capacitors.
PIN CONFIGURATION
VIN
1
28
+VANA
AGND1
2
27
+VDIG
REF
3
26
–VANA
CAP
4
25
BUSY
AGND2
5
24
CS
D11 (MSB)
6
23
R/C
D10
7
22
DGND
ADS7810
D9
8
21
+VDIG
D8
9
20
+VANA
D7
10
19
NC(1)
D6
11
18
D0 (LSB)
D5
12
17
D1
D4
13
16
D2
DGND
14
15
D3
NOTE: (1) Not Internally Connected.
®
ADS7810
4
TYPICAL PERFORMANCE CURVES
T = +25°C, fS =800kHz, +VDIG = +VANA = +5V, –VANA = –5V, using internal reference and the input 50Ω resistors as shown in Figure 4b, unless otherwise specified.
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 502kHz, –0.5dB)
0
0
–20
–20
–40
–40
Amplitude (dB)
–60
–80
–100
–80
–100
–120
–120
0
100
200
300
400
0
100
200
400
Frequency (kHz)
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 1.002MHz, –0.5dB)
FREQUENCY SPECTRUM
(4096 Point FFT; f1IN = 232kHz, –6.5dB;
f2IN = 272kHz, –6.5dB)
0
0
–20
–20
–40
–40
–60
–80
–100
–60
–80
–100
–120
–120
0
100
200
300
400
0
100
200
Frequency (kHz)
300
400
Frequency (kHz)
A.C. PARAMETERS vs TEMPERATURE
(fIN = 250kHz, –0.5dB)
SIGNAL-TO-(NOISE + DISTORTION)
vs INPUT FREQUENCY (fIN = –0.5dB)
100
80
95
SFDR, SNR, and SINAD (dB)
90
70
SINAD (dB)
300
Frequency (kHz)
Amplitude (dB)
Amplitude (dB)
–60
60
50
40
30
20
–100
–95
SFDR
90
–90
85
–85
80
–80
THD
SNR
75
–75
70
–70
SINAD
65
–65
60
10
1k
10k
100k
1M
–60
–50
10M
–25
0
25
50
75
100
Temperature (°C)
Input Signal Frequency (Hz)
®
5
ADS7810
THD (dB)
Amplitude (dB)
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 252kHz, –0.5dB)
TYPICAL PERFORMANCE CURVES (CONT)
T = +25°C, fS =800kHz, +VDIG = +VANA = +5V, –VANA = –5V, using internal reference and the 50Ω input resistors as shown in Figure 4b, unless otherwise specified.
CODE TRANSITION NOISE
Conversions Yielding Expected Code (%)
12-Bit LSBs
1
0.5
0
–0.5
All Codes INL
–1
0
512
1024
1536
2048
2560
3072
3584
4095
Decimal Code
12-Bit LSBs
1
0.5
0
100
75
50
25
0
0
–0.5
0.25
0.5
1
0.75
Analog Input Voltage – Expected Code Center (LSBs)
All Codes DNL
–1
0
512
1024
1536
2048
2560
3072
3584
4095
Decimal Code
D.C. PARAMETERS vs. TEMPERATURE
INTERNAL REFERENCE VOLTAGE vs TEMPERATURE
LSBs
From Ideal
Percent
From Ideal
0.2
0.1
0
–0.1
–0.2
Percent
From Ideal
2.520
2
1
0
–1
–2
0.2
0.1
0
–FS Error
–0.1
–0.2
–75 –50
–25
Offset Error
+FS Error
Conversion Time (ns)
2.495
2.490
–50
0
25
50
75
100
125
1100
1050
1000
950
900
850
800
750
0
25
50
75
100
Temperature (°C)
®
ADS7810
–25
0
25
50
Temperature (°C)
150
1150
–25
2.500
2.480
CONVERSION TIME (t7) vs TEMPERATURE
–50
2.505
2.485
Temperature (°C)
1200
2.510
THD (dB)
Internal Reference (V)
2.515
6
75
100
BASIC OPERATION
STARTING A CONVERSION
Figure 1 shows a basic circuit to operate the ADS7810.
Taking R/C (pin 23) LOW for a minimum of 40ns will
initiate a conversion. BUSY (pin 25) will go LOW and stay
LOW until the conversion is completed and the output
registers are updated. Data will be output in Binary Two’s
Complement with the MSB on D11 (pin 6). BUSY going
HIGH can be used to latch the data. All convert commands
will be ignored while BUSY is LOW.
The combination of CS (pin 24) and R/C (pin 23) LOW for
a minimum of 40ns puts the sample/hold of the ADS7810 in
the hold state and starts a conversion. BUSY (pin 25) will go
LOW and stay LOW until the conversion is completed and
the internal output register has been updated. All new
convert commands during BUSY LOW will be ignored.
The ADS7810 will begin tracking the input signal at the end
of the conversion. Allowing 1.25µs between convert commands assures accurate acquisition of a new signal. Refer to
Table I for a summary of CS, R/C, and BUSY states and
Figures 2 and 3 for timing parameters.
The ADS7810 will begin tracking the input signal at the end
of the conversion. Allowing 1.25µs between convert commands assures accurate acquisition of a new signal.
CS
R/C
BUSY
1
X
X
None. Databus in Hi-Z state.
↓
0
1
Initiates conversion. Databus remains in
Hi-Z state.
0
↓
1
Initiates conversion. Databus enters Hi-Z
state.
0
1
↑
Conversion completed. Valid data from
the most recent conversion on the databus.
CS and R/C are internally OR’d and level triggered. There
is not a requirement which input goes LOW first when
initiating a conversion. If it is critical that CS or R/C initiate
the conversion, be sure the less critical input is LOW at least
10ns prior to the initiating input.
OPERATION
DESCRIPTION
ANALOG VALUE
DIGITAL OUTPUT
Full Scale Range
±10V
BINARY TWO'S COMPLEMENT
↓
1
1
Enables databus with valid data from the
most recent conversion.
Least Significant
Bit (LSB)
4.88mV
↓
1
0
Conversion in progress. Databus in Hi-Z
state, enabled when the conversion is
completed
+Full Scale
(10V – 1LSB)
9.995V
0
↑
0
Conversion in progress. Databus in Hi-Z
state, enabled when the conversion is
completed
One LSB below
Midscale
0
↑
0
X
X
0
Midscale
–Full Scale
Conversion completed. Valid data from the
most recent conversion in the output
register, but output pins D11-D0 are tri-stated.
BINARY CODE
HEX CODE
0111 1111 1111
7FF
0V
0000 0000 0000
000
–4.88mV
1111 1111 1111
FFF
–10V
1000 0000 0000
800
TABLE II. Ideal Input Voltages and Output Codes.
New convert commands ignored. Conversion
in progress.
Table I. Control Line Functions for ‘read’ and ‘convert’.
0.1µF 10µF
+
+
50Ω
±10V
1
28
2
27
3
26
4
25
5
24
D11 (MSB)
6
23
D10
7
0.1µF
10µF
+
0.1µF 10µF
+
+5V
–5V
+
BUSY
Convert Pulse
22
ADS7810
D9
8
21
D8
9
20
D7
10
19
D6
11
18
D0 (LSB)
D5
12
17
D1
D4
13
16
D2
14
15
D3
40ns min
NC
FIGURE 1. Basic Operation
®
7
ADS7810
To reduce the number of control pins, CS can be tied LOW
using R/C to control the read and convert modes. Note that
the parallel output will be active whenever R/C is HIGH and
no conversion is in progress. See the Reading Data section
and refer to Table I for control line functions for ‘read’ and
‘convert’ modes.
The nominal input impedance of 3.125kΩ results from the
combination of the internal resistor network shown on the
front page of the product data sheet and external 50Ω
resistor. The input resistor divider network provides inherent
overvoltage protection guaranteed to at least ±25V. The
50Ω, 1% resistor does not compromise the accuracy or drift
of the converter. It has little influence relative to the internal
resistors, and tighter tolerances are not required.
READING DATA
Note: The values shown for the internal resistors are for
reference only. The exact values can vary by ±30%. This is
true of all resistors internal to the ADS7810. Each resistive
divider is trimmed so that the proper division is achieved.
The ADS7810 outputs full parallel data in Binary Two’s
Complement data format. The parallel output will be active
when R/C (pin 23) is HIGH, CS (pin 24) is LOW, and no
conversion is in progress. Any other combination will tristate the parallel output. Valid conversion data can be read
in a full parallel, 12-bit word on D11-D0 (pins 6-13 and 1518). Refer to Table II for ideal output codes.
NOTE: (1) Full scale error includes offset and gain errors measured at both
+FS and –FS.
After the conversion is completed and the output registers
have been updated, BUSY (pin 25) will go HIGH. Valid data
from the most recent conversion will be available on
D11-D0 (pins 6-13 and 15-18). BUSY going HIGH can be
used to latch the data. Refer to Table III and Figures 2
and 3.
SYMBOL
Note: For the best performance, the external data bus connected to D11-D0 should not be active during a conversion.
The switching noise of the external asynchronous data
signals can cause digital feedthrough degrading the
converter’s performance.
The number of control lines can be reduced by tieing CS
LOW while using R/C to initiate conversions and activate
the output mode of the converter. See Figure 2.
INPUT RANGES
The ADS7810 offers a standard ±10V input range. Figures
4a and 4b show the necessary circuit connections for the
ADS7810 with and without external trim. Offset and full
scale error(1) specifications are tested and guaranteed with
the 50Ω resistor shown in Figure 4b. This external resistor
makes it possible to trim the offset ±50mV using a trim pot
or trim DAC. This resistor may be left out if the offset and
gain errors will be corrected in software or if they are
negligible in regards to the particular application. See the
Calibration section of the data sheet for details.
MIN
Convert Pulse Width
40
TYP
MAX
t2
Data Valid Delay
After R/C LOW
955
1095
t3
8
UNITS
ns
BUSY Delay
From R/C LOW
70
125
ns
t4
BUSY LOW
950
1080
t5
BUSY Delay After
End of Conversion
90
ns
t6
Aperture Delay
20
ns
ns
ns
t7
Conversion Time
910
1020
t8
Acquisition Time
200
230
ns
t7 & t 8
Throughput Time
1110
1250
ns
ns
t9
Bus Relinquish Time
10
50
83
ns
t10
BUSY Delay
After Data Valid
20
65
120
ns
t11
R/C to CS
Setup Time
10
ns
t12
Time Between
Conversions
1250
ns
t13
Bus Access Time
10
25
62
TABLE III. Timing Specifications (TMIN to TMAX).
®
ADS7810
DESCRIPTION
t1
ns
t1
R/C
t12
t2
t3
t5
t4
BUSY
t6
MODE
DATA BUS
Acquire
Convert
Acquire
t7
t8
Hi-Z State
Data Valid
Convert
Data Valid
t9
HI Z State
t10
FIGURE 2. Conversion Timing with Outputs Enabled After Conversion (CS Tied Low).
t11
t11
t11
t11
R/C
t1
CS
t3
t5
t4
BUSY
t6
MODE
Convert
Acquire
Acquire
t7
t2
DATA
BUS
Hi-Z State
Data Valid
HI Z State
t9
t13
FIGURE 3. Using CS to Control Conversion and Read Timing.
50Ω
VIN
VIN
+5V
P1
5kΩ
5V
50Ω
VIN
R1
5kΩ
VIN
AGND1
R2
604kΩ
AGND1
REF
–5V
REF
P2
5kΩ
0.1µF
10µF
0.1µF
CAP
+
CAP
10µF
AGND2
+
AGND2
NOTE: Use 1% metal film resistors. Trim offset at 0V first, then trim
gain at 10V.
FIGURE 4a. Circuit Diagram With External Hardware Trim.
FIGURE 4b. Circuit Diagram Without External Hardware
Trim.
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9
ADS7810
CALIBRATION
The external 50Ω resistor shown in Figure 4b may not be
necessary in some applications. This resistor provides trim
capability for the offset and compensates for a slight gain
adjustment internal to the ADS7810. Not using the 50Ω
resistor will cause a small gain error but will have no effect
on the inherent offset error. Figure 5 shows typical transfer
function characteristics with and without the 50Ω resistor in
the circuit.
The ADS7810 can be trimmed in hardware or software. The
offset should be trimmed before the gain since the offset
directly affects the gain.
Hardware Calibration
To calibrate the offset and gain of the ADS7810, install the
proper resistors and potentiometers as shown in Figure 4a.
The calibration range is ±50mV for bipolar zero and ±120mV
for full scale.
REFERENCE
Potentiometer P1 and resistor R1 form the offset adjust
circuit and P2 and R2 the gain adjust circuit. The exact values
are not critical. R1 and R2 should not be made any larger than
the value shown. They can easily be made smaller to provide
increased adjustment range. Reducing these below 15% of
the indicated values could begin to adversely affect the
operation of the converter.
The ADS7810 can operate with its internal 2.5V reference or an
external reference. By applying an external reference to pin 3,
the internal reference can be bypassed. The reference voltage at
REF is buffered internally and output on CAP (pin 4).
REF
P1 and P2 can also be made larger to reduce power dissipation. However, larger resistances will push the useful adjustment range to the edges of the potentiometer. P1 should
probably not exceed 20kΩ and P2 100kΩ in order to maintain reasonable sensitivity.
REF (pin 3) is an input for an external reference or the
output for the internal 2.5V reference. A 0.1µF capacitor
should be connected as close to the REF pin as possible. The
capacitor and the output resistance of REF create a low pass
filter to band limit noise on the reference. Using a smaller
value capacitor will introduce more noise to the reference
degrading the SNR and SINAD. The internal reference
should not be used to sink or source currents greater than
100µA. In addition, all external loads should be static.
Software Calibration
To calibrate the offset and gain of the ADS7810, no external
resistors are required. See the No Calibration section for
details on the effects of the external resistor.
The range for the external reference is 2.3V to 2.7V and
determines the actual LSB size. Increasing the reference
voltage will increase the full scale range and the LSB size
of the converter which can improve the SNR.
No Calibration
See Figure 4b for circuit connections. Note that the actual
voltage dropped across the 50Ω resistor is nearly two orders
of magnitude lower than the voltage dropped across the
internal resistor divider network. This should be taken into
consideration when choosing the accuracy and drift specifications of the external resistors. In most applications, 1%
metal-film resistors will be sufficient.
Digital
Output
+ Full Scale
–10.0V –9.84V
9.84V
10.0V
Analog
Input
Typical Transfer Function
with 50Ω Resistor
Typical Transfer Function
without 50Ω Resistor
– Full Scale
FIGURE 5. Comparison of the ADS7810 Transfer Function With and Without the 50Ω Series Resistor on VIN.
®
ADS7810
10
CAP
CAP (pin 4) is the output of the internal reference buffer. A
10µF tantalum capacitor should be placed as close to the
CAP as possible to provide optimum switching currents for
the CDAC throughout the conversion cycle and compensation for the output of the buffer. Using a capacitor any
smaller than 1µF can cause the output buffer to oscillate and
may not have sufficient charge for the CDAC. Capacitor
values larger than 10µF will have little effect on improving
performance. The voltage on the CAP pin is approximately
2V when using the internal reference, or 80% of an externally supplied reference.
SIGNAL CONDITIONING
The FET switches used for the sample hold on many CMOS
A/D converters release a significant amount of charge injection which can cause the driving op amp to oscillate. The
resistive front end of the ADS7810 attenuates this charge
and reduces its magnitude significantly—reducing the burden on the external input amplifier or buffer.
LAYOUT
However, keep in mind that maintaining signal integrity at
voltage swings of ±10V and frequencies of several hundred
kilohertz is extremely challenging. In addition, the external
input amplifier must drive the ADS7810 mainly during its
sample period—roughly 200ns. This will require a highspeed, precision amplifier which can swing to greater than
±10V.
POWER
The ADS7810 uses the majority of its power for analog and
static circuitry, and it should be considered as an analog
component. For optimum performance, tie the analog and
digital +5V power pins to the same +5V power supply and
tie the analog and digital grounds together.
For signals where the predominant frequencies are below
200kHz, the OPA671 operational amplifier should be adequate for most applications. In some cases or where input
frequencies are higher, a composite configuration of the
OPA671 and BUF634 (in its wide bandwidth mode) may be
the best choice. See the BUF634 data sheet for more information.
For best performance, the ±5V supplies can be produced
from whatever analog supply is used for the rest of the
analog signal conditioning. If ±12V or ±15V supplies are
present, simple regulators can be used. The +5V power for
the A/D should be separate from the +5V used for the
system’s digital logic. Connecting +VDIG (pin 27) directly to
a digital supply can reduce converter performance due to
switching noise from the digital logic.
The resistive front end of the ADS7810 also provides a
guaranteed ±25V over voltage protection. In most cases, this
eliminates the need for external input protection circuitry.
INTERMEDIATE LATCHES
The ADS7810 does have tri-state outputs for the parallel
port, but intermediate latches should be used if the bus will
be active during conversions. If the bus is not active during
conversions, the tri-state outputs can be used to isolate the
A/D from other peripherals on the same bus.
Although it is not suggested, if the digital supply must be
used to power the converter, be sure to properly filter the
supply. Either using a filtered digital supply or a regulated
analog supply, both VDIG and VANA should be tied to the
same +5V source.
Intermediate latches are beneficial on any monolithic A/D
converter. The ADS7810 has an internal LSB size of 610µV.
Transients from fast switching signals on the parallel port,
even when the A/D is tri-stated, can be coupled through the
substrate to the analog circuitry causing degradation of
converter performance.
GROUNDING
Three ground pins are present on the ADS7810. DGND
(pin 22) is the digital supply ground. AGND2 (pin 5) is the
analog supply ground. AGND1 (pin 2) is the ground which all
analog signals internal to the A/D are referenced. AGND1 is
more susceptible to current induced voltage drops and must
have the path of least resistance back to the power supply.
All the ground pins of the ADS should be tied to the
analog ground plane, separated from the system’s digital
logic ground, to achieve optimum performance. Both analog and digital ground planes should be tied to the “system” ground as near to the power supplies as possible.
This helps to prevent dynamic digital ground currents
from modulating the analog ground through a common
impedance to power ground.
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ADS7810