19-1166; Rev 0; 12/96 Single-Chip, 8-Bit CCD Digitizer with Clamp and 6-Bit PGA ________________________Applications ____________________________Features ♦ 1.0 Million Pixels/sec Conversion Rate ♦ Built-In Clamp Circuitry for Black-Level Correction or Correlated Double Sampling ♦ 64-Step PGA, Programmable from Gain = -2 to -10 ♦ Auxiliary Mux Inputs for Added Versatility ♦ Compatible with a Large Range of CCDs ♦ 8-Bit ADC Included ♦ Space-Saving, 24-Pin SO Package ______________Ordering Information Scanners Fax Machines PART TEMP. RANGE MAX1101CWG 0°C to +70°C PIN-PACKAGE 24 Wide SO Pin Configuration appears on last page. Digital Copiers CCD Imaging ___________________________________________________Typical Operating Circuit 1 CEXT 0.047µF 2 3 CCD ARRAY 4 5 6 7 GND CCDIN GND MAX1101 VDD GND CLAMP AIN1 VIDSAMP GND LOAD AIN2 DATA GND SCLK MODE GND 24 23 0.1µF +5V DC (SUPPLY) 22 21 20 µP/µC/ STATE LOGIC 19 18 17 16 VDD 15 11 0.1µF 12 REFGND REF- REFBIAS REF+ 14 13 +5V DC (REFERENCE) 0.1µF 1 2 AUXILIARY ANALOG INPUTS ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800 MAX1101 _______________General Description The MAX1101 is a highly integrated IC designed primarily for digitizing the output of a linear CCD array. It provides the components required for all necessary analog functions, including clamp circuitry for blacklevel correction or correlated double sampling (CDS), a three-input multiplexer (mux), and an 8-bit analog-todigital converter (ADC). The MAX1101 operates with a sample rate up to 1MHz and with a wide range of linear CCDs. The logic interface is serial, and a single input sets the bidirectional data line as either data in or data out, thus minimizing the I/O pins required for communication. Packaged in a 24-pin SO, the MAX1101 is available in the commercial (0°C to +70°C) temperature range. MAX1101 Single-Chip, 8-Bit CCD Digitizer with Clamp and 6-Bit PGA ABSOLUTE MAXIMUM RATINGS VDD to GND ............................................................-0.3V to +12V All Pins to GND...........................................-0.3V to (VDD + 0.3V) Current into Every Pin (except VDD) .................................±20mA Current into VDD ...............................................................±50mA Continuous Power Dissipation (TA = +70°C) SO (derate 11.76mW/°C above +70°C) ......................941mW Operating Temperature Range...............................0°C to +70°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = VREFBIAS = +4.75V to +5.25V, REFGND = 0V, REF- bypassed to REFGND with 0.1µF, CEXT = 47nF, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ±0.5 ±1 LSB ±1.5 LSB ANALOG-TO-DIGITAL CONVERTER Resolution N Differential Nonlinearity 8 DNL No-missing-codes guaranteed Integral Nonlinearity INL Best straight-line fit Total Unadjusted Error TUE Zero-Scale Drift TCVOS Full-Scale Drift TCFS Maximum Sample Rate ±1 ±2.5 fs Minimum Sample Rate 0.67 (Note 1) Input Full-Power Bandwidth tAP LSB 125 %µV/°C 0.016 %FS/°C 1.2 MHz 1 VIN = 2.5Vp-p Aperture Delay Bits kHz 1 MHz 10 ns ANALOG INPUT—CCD INTERFACE Maximum Peak CCD Differential Signal Range VWHITE VWHITE = (VREF+ - VREF-) / GPGA GPGA = -2 1.25 GPGA = -10 0.25 V Minimum PGA Gain Setting -1.9 -2 -2.1 Maximum PGA Gain Setting -9.375 -9.875 -10.375 V/V V/V Gain Adjust Resolution 64 Gain Adjust Step Size 0.125 V/V ±5 % Gain PGA Gain Error Black Sample Switch On-Resistance RON(BSS) Input Leakage (Note 2) IL(CCDIN) Including black sample switch off-leakage CCD Interface Offset Voltage VOS(CCD) VVIDEO = VRESET (Figure 4) 0 Steps 60 150 Ω 1 50 nA 4 8 LSB VREF+ V ANALOG INPUT—AUXILIARY INPUTS Input Voltage Range Input Capacitance (Note 1) On-Resistance 2 VIN VREF- CIN(ON) Channel on 45 CIN(OFF) Channel off 10 RON 120 _______________________________________________________________________________________ pF Ω Single-Chip, 8-Bit CCD Digitizer with Clamp and 6-Bit PGA (VDD = VREFBIAS = +4.75V to +5.25V, REFGND = 0V, REF- bypassed to REFGND with 0.1µF, CEXT = 47nF, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS REFERENCE VOLTAGE INPUT Positive Reference Voltage VREF+ Internally generated, VREFBIAS = 5V 2.94 3.00 3.06 V Negative Reference Voltage VREF- Internally generated, VREFBIAS = 5V 0.49 0.50 0.51 V 4.75 5 5.25 V 48 60 40 mA POWER SUPPLIES Positive Supply-Voltage Range PSRR, PGA and ADC Supply Current VDD PSRR 4.75V ≤ VDD ≤ 5.25V IDD 20 dB DIGITAL INPUTS/OUTPUTS Digital Input Voltage High VIH Digital Input Voltage Low VIL Digital Input Leakage Current IIL 3.5 -10 Digital Output Voltage High VOH ISOURCE = 4mA Digital Output Voltage Low VOL ISINK = 4mA Digital Output Leakage Current IOL Output in high-impedance mode V 1.5 V 10 µA VDD - 0.5 -10 V 0.5 V 10 µA 10 MHz DIGITAL TIMING SPECIFICATIONS (tr , tf ≤ 10ns, CL ≤ 50pF, unless otherwise noted) SCLK Frequency fSCLK SCLK Pulse Width tSPW 50 ns VIDSAMP Pulse Width tVS 500 ns VIDSAMP to CLAMP Separation tVB 50 ns LOAD Pulse Width tLD 50 ns VIDSAMP Fall to SCLK Rise Time tVLS MODE = 1 50 ns VIDSAMP Fall to DATA tVLD MODE = 1 VIDSAMP to Reset Separation tVR (Note 2) 50 ns Reset to CLAMP Separation tRB (Note 2) 50 ns 60 SCLK Rise to DATA tSD DATA Set-Up Time tDSU 20 ns DATA Hold Time tDH 20 ns LOAD Fall to SCLK Rise Time tLS MODE = 0 50 ns SCLK Rise to LOAD Rise Time tSL MODE = 0 50 ns Same as bus-relinquish time 50 ns MODE Setup Time tMSU 60 ns ns CLAMP Pulse Width tBS 300 ns CLAMP Fall to Video Update tBC (Note 1) 20 ns Digital Quiet Time (Note 3) tQ ± around VIDSAMP falling edge 20 ns Note 1: Due to leakage in the PGA and ADC, operation at sample rates below 1ksps is not recommended, as performance may degrade, particularly at high temperatures. Note 2: Production test equipment settling time prohibits leakage measurements below 1nA. Lab equipment has shown the MAX1101 switch input leakage below 1pA at TA = +25°C, and below 50pA at TA = +70°C. Note 3: Not a test parameter. Recommended for optimal performance. _______________________________________________________________________________________ 3 MAX1101 ELECTRICAL CHARACTERISTICS (continued) MAX1101 Single-Chip, 8-Bit CCD Digitizer with Clamp and 6-Bit PGA ______________________________________________________________Pin Description PIN NAME 1, 3, 5, 7, 10, 16, 24 FUNCTION GND 2 CCDIN 4 AIN1 Auxiliary Analog Input Channel 1 6 AIN2 Auxiliary Analog Input Channel 2 Ground CCD Input. Connect CCD through a series 0.047µF capacitor (CEXT). 8, 9, 10 I.C. 11 REFGND Internally Connected. Do not connect to this pin. 12 REF- Lower Limit of Reference Span. Sets the zero-code voltage. Range is GND ≤ REF- ≤ REF+. Nominally 0.5V. 13 REF+ Upper Limit of Reference Span. Sets the full-scale input. Voltage range is REF- ≤ REF+ ≤ VDD. Nominally 3.0V. 14 REFBIAS Reference Power Supply. Connect to external +5.0V to set VREF+ to +3.0V and VREF- to +0.5V. 15, 23 VDD Power Supply, +5V. Bypass to ground very close to the device and connect the two pins together, close to the MAX1101. 17 MODE Control Input. Set high, DATA is an output of the ADC. Set low, DATA enables programming of the PGA and mux. 18 SCLK Serial Clock Input 19 DATA Data Input or Output, as controlled by MODE 20 LOAD Control Input. Loads serial shift-register data to PGA and multiplexer registers when MODE = 0. 21 VIDSAMP 22 CLAMP Reference Ground. Ground reference for all analog signals. Control Input. Samples the video level and initiates the ADC conversion. Control Input. Samples black level. Can be used for correlated double sampling. REFBIAS AIN2 AIN1 Overview 2 1 REF+ MUX ADC 8 CCDIN CLAMP CLAMP CIRCUIT PGA GAIN REF- 0 6 2 VIDSAMP REFGND REGISTER REGISTER 6 _______________Detailed Description REGISTER 8 2 SERIAL PORT DATA SCLK LOAD MODE The MAX1101 directly processes the pixel stream from a monochrome CCD, and removes black level, offset, and noise errors through an internal clamp circuit, which can be used as a correlated double sampler (CDS). It uses a 6-bit, programmable-gain amplifier (PGA) to adjust gain. A three-input multiplexer (mux) selects either the PGA output or two unassigned inputs (AIN1, AIN2). The processed analog signal is digitized by an 8-bit, half-flash analog-to-digital converter (ADC), and output serially through the DATA pin. Digital data is input and output through the bidirectional serial pin (DATA) synchronously with the external serial clock (SCLK). When MODE = 0, the mux channels and the PGA gain can be programmed via DATA. With MODE = 1 (high), ADC serial data is output through this pin. Figure 1. MAX1101 Functional Diagram 4 _______________________________________________________________________________________ Single-Chip, 8-Bit CCD Digitizer with Clamp and 6-Bit PGA REF+ REF+ REF- MAX1101 REF+ REF- S1 CF CLAMP S1 CF S2 CI S1P CI S2 FROM CCD VOUT = VREF- ±V0S TO ADC CEXT 0.047µF REFREF- Figure 3a. PGA Connection with VIDSAMP = Low VIDSAMP CF S1* ON OFF S2* OFF ON S1P* OFF VREF+ - VVIDEO (FROM DC RESTORE) ON * INTERNALLY GENERATED SIGNALS CI REF- Figure 3b. PGA Connection with VIDSAMP = High Figure 2. PGA Functional Diagram Programmable-Gain Amplifier The PGA amplifies the differential video signal from the CCD (at CCDIN). Gain is settable with the 6-bit control word from -2 to -10 in 64 steps, in increments of -0.125. The PGA also provides for periodic DC restoration of the capacitively coupled input. As shown in Figure 2, the switched-capacitor amplifier’s gain is set by the ratio CI/CF. The input is sampled on the CI capacitors, which is a set of equal capacitors. The 6-bit gain control word determines the number of capacitors used. Thus the PGA gain is set from -2 to -10. A voltage equal to VREF- is applied to the PGA’s noninverting input. This offsets the PGA output to be within the range of the ADC (VREF- to VREF+). Clamp Circuit As shown in Figure 2, the CCD output is connected to the MAX1101 input (CCDIN) through an external capacitor, which removes the potentially large DC common-mode voltages from the input signal. Whenever CLAMP is high, the CLAMP switch is closed and C EXT is charged to V REF+ . It can be actuated either once per pixel (sampling reset level) or less frequently (such as for restoring optical black level once per line), as required by the application. VIDSAMP controls the sampling of the video signal and offset nulling of the PGA. To null out the offset, VIDSAMP causes switches S1 and S1P to close, placing the amplifier in a unity-gain configuration, as shown in Figure 3a. This configuration causes the amplifier’s offset voltage to be stored on CF. In the next portion of the cycle, when VIDSAMP returns low, the S1 switches are opened and S2 is closed (Figure 3b). This is the standard inverting op-amp configuration. The only difference is that capacitors are used to set the gain, and the amplifier’s offset voltage has been stored on these capacitors and is thus canceled. The amplifier’s output is [CF/CI] x VVIDEO + VREF-. The CDS function is shown in Figure 4. ADC The ADC uses a recycling half-flash conversion technique in which a 4-bit flash ADC section achieves an 8-bit result in two steps (Figure 5). Using 15 comparators, the flash ADC compares the unknown input voltage to the reference ladder (using REF+ and REF-) and provides the upper four data bits. An internal digital-to-analog converter (DAC) uses the four most significant bits (MSBs) to generate the analog result from the first flash conversion and a residue voltage that is the difference between the unknown voltage _______________________________________________________________________________________ 5 MAX1101 Single-Chip, 8-Bit CCD Digitizer with Clamp and 6-Bit PGA CCD OUTPUT LEVELS VARY DUE TO CCD RESET NOISE CCD OUTPUT CLAMP PULSE (CLAMP) VOLTAGE OF RESET SECTION IS SET TO VREF+ BY CLAMP VVIDEO CLAMP OUTPUT SAMPLE-AND-HOLD PULSE (VIDSAMP) Figure 4. Correlated Double Sampler (CDS) and the DAC output. The residue is then compared again with the flash comparators to obtain the lower four data bits. Single-shot timers control the timing of the two conversion steps. Once both MSBs and LSBs have been determined, the comparators return to input-acquisition/auto-zero mode. REF+ 4-BIT FLASH ADC REFFROM MUX REF+ and REFThe REF+ and REF- pins set the ADC’s full-scale range. The optimum input range is +0.5V to +3.0V. Figure 6 shows a matched resistive ladder that generates the reference voltages. Four pins are available: REF+, REF-, REFBIAS, and REFGND. If 5.00V is applied to REFBIAS while REFGND is grounded, then 3.00V and 0.50V are generated at REF+ and REF-, respectively. For increased accuracy or power-supply immunity, REF+ can be connected to an external +3.00V reference. If this is done, the accuracy must be better than ±5%. REFBIAS should be left open in this case. Multiplexer The mux selects either the output of the PGA or one of two other inputs to the ADC. The mux switching is break-before-make to prevent transient shorts between channels. The first two bits of the input control byte select the mux input channel (Table 1). 6 OUTPUT REGISTER 4-BIT DAC VREF+ 16 DATA OUT 4-BIT FLASH ADC (4LSB) Figure 5. ADC Functional Diagram Serial-Interface Logic The serial interface inputs and outputs data in 8-bit words. The interface is controlled by four signals: MODE, LOAD, DATA, and SCLK. _______________________________________________________________________________________ Single-Chip, 8-Bit CCD Digitizer with Clamp and 6-Bit PGA Data Output Data is clocked in and out of the device with the rising edge of SCLK. The first bit (the MSB, D7) immediately follows the falling edge of VIDSAMP (Figures 7 and 8). The first rising edge of SCLK clocks out the next bit, D6. Data is loaded into the shift register at the falling edge of VIDSAMP. Following the output of D0, DATA output is unspecified for additional SCLK pulses. Eight-bit-wide storage and output registers hold data from the ADC and delay the data output. The timing diagram in Figure 9 shows the data latency of two VIDSAMP cycles. New data is available after the second falling edge of VIDSAMP. LOAD LOAD is normally low and used only when MODE = 0. Once all eight bits have been clocked in, bring LOAD high to update the MAX1101 registers. DATA DATA is a bidirectional I/O pin. MODE controls the direction of data transfer. When MODE = 1, DATA is configured as an output from the shift register. Data is clocked out of the shift register by SCLK’s rising edge. When MODE = 0, DATA is configured as an input to the shift register, shifted in by the rising edge of SCLK. In this mode, the DATA output driver is disabled, putting DATA into a high-impedance state and allowing it to be driven externally. Data Input During data input, the first two bits (A0, A1) are the address, selecting either the mux or PGA. The next six bits set the input channel or PGA gain (Table 1). CLAMP and VIDSAMP The last two digital inputs are VIDSAMP and CLAMP. VIDSAMP controls the overall cycle timing, with one VIDSAMP cycle corresponding to one CCD pixel. The input is sampled into the ADC by the falling edge of VIDSAMP. CLAMP controls the black sample switch, which sets a reference DC voltage level (VREF+) at the capacitively coupled CCDIN input. The sample switch is on when CLAMP is high. REFBIAS 800Ω REF+ Control and Interface Logic The control and interface logic consists of a serial I/O port, which shifts data into and out of the MAX1101, and two registers for storing the mux channel and the PGA gain data. 1kΩ REF200Ω REFGND Figure 6. Reference Resistor String Table 1. Control-Byte Format FUNCTION Address Analog Input Mux Address CCD PGA No Operation Select CCD input Select AIN1 Select AIN2 Set PGA Gain to -2 Set PGA Gain to -2.125 Set PGA Gain to -9.750 Set PGA Gain to -9.875 A0 A1 D5 MSB D4 D3 D2 D1 D0 LSB 0 0 1 0 0 0 0 0 0 0 0 1 X 0 0 0 1 1 1 1 — — X 0 0 1 0 0 1 1 — — X 0 1 0 0 0 1 1 — — X 0 0 0 0 0 1 1 — — X X X X 0 0 1 1 — — X X X X 0 0 1 1 — — X X X X 0 1 0 1 X = Don’t Care _______________________________________________________________________________________ 7 MAX1101 MODE MODE controls the direction of data transfer. When MODE = 0, data is being shifted into the MAX1101 at the DATA pin either for the mux or the PGA. When MODE = 1, the ADC output is shifted out from the MAX1101 at the DATA pin. Data is shifted in and out of the MAX1101 at the rising edge of SCLK. MAX1101 Single-Chip, 8-Bit CCD Digitizer with Clamp and 6-Bit PGA MODE tMSU tSPW tSPW SCLK tLS tSL tLD LOAD tDSU DATA A0 tDH A1 D5 D4 D3 D2 D1 D0 Figure 7. MODE = 0 Timing RESET FEEDTHROUGH PRECHARGE LEVEL CCD OUT tVR VIDEO LEVEL tCPW tVS VIDSAMP tBC tRB tQ tVB CLAMP SCLK DATA tVB tBS tVLS tVLD tSD D7 D6 D5 D4 D3 D2 D1 D0 DATA OUTPUT AFTER D0 IS UNSPECIFIED Figure 8. MODE = 1 Timing LOAD controls the loading of data into the internal storage registers during data input. Once all eight input bits have been clocked into the shift register, a rising edge on LOAD clocks the data into the appropriate storage register (mux or PGA), decoded from the first two input bits. The logic is divided into four blocks: the two storage registers, the serial I/O port, and a power-on reset generator. The registers are reset by the power-on reset to place them in a predictable state (input channel = CCD, PGA gain = -2) on power-up. The power-on reset typically has a 2.1µs pulse width. The serial I/O port consists of a shift register, an 8-bit storage register, decode logic to clock input data into the appropriate storage register, and an output driver. The 8-bit storage register takes input data from the ADC. 8 Input Buffers and Output Drivers The DATA driver is capable of driving 50pF load capacitance while meeting the output delay specifications given in the Electrical Characteristics. The gates of the Pchannel and N-channel drivers are driven separately. If MODE is low, both drivers are off and the output is high impedance. The VIDSAMP, CLAMP, SCLK, and LOAD inputs are buffered and have hysteresis to reject noise with slowslewing signal edges. __________Applications Information MAX1101 Timing Figure 7 shows the timing configuration when MODE = 0 and data is loaded into the MAX1101. Figure 8 shows timing when MODE = 1 and the CCD signal is digitized. Figure 9 is an expansion of Figure 8, illustrating the two-VIDSAMP-cycle data latency. Figure 10 shows the relationship of CLAMP to VIDSAMP when MODE = 1. _______________________________________________________________________________________ Single-Chip, 8-Bit CCD Digitizer with Clamp and 6-Bit PGA MAX1101 CCD (OUT) VIDEO N VIDEO N+1 VIDEO N+2 VIDEO N+3 VIDSAMP CLAMP PGA ADC AUTO-ZERO MSB N-1 SAMPLE N LSB N-1 SAMPLE N AUTO-ZERO MSB N SAMPLE N+1 LSB N SAMPLE N+1 AUTO-ZERO MSB N+1 SAMPLE N+2 LSB N+1 SAMPLE N+2 AUTO-ZERO MSB N+2 SAMPLE N+3 LSB N+2 SAMPLE N+3 ADC REG DATA N-2 DATA N-1 DATA N DATA N+1 SHIFT REG DATA N-3 DATA N-2 DATA N-1 DATA N SCLK DATA D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 DATA N-3 D1 D0 D7 D6 D5 D4 D3 D2 DATA N-2 DATA N-1 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 DATA N Figure 9. MODE = 1 Timing Showing Data Latency BLACK CELL BLACK CELL CCD (OUT) VIDEO N VIDSAMP CLAMP (ONCE PER LINE) CLAMP (ONCE PER CELL) Figure 10. MODE = 1 Timing Showing Relationship of CLAMP to VIDSAMP Input/Output Transfer Function CCD Input Figure 11 shows the MAX1101 transfer function for CCDIN. Coding is binary, with a -4LSB offset added to ensure that offsets within the MAX1101, which can be positive or negative, do not cause the ADC to be out of range. Full-scale input range at CCDIN is: (VREF+ - VREF-) / GPGA where G PGA is the gain of the programmable gain amplifier. Analog Inputs (AIN_) The transfer function for auxiliary inputs is shown in Figure 11. Again, coding is binary and full-scale range is VREF- to VREF+. An offset has not been added to these channels; however, code transitions occur at the 1/2LSB point, as shown in Figure 12. Implementing Correlated Double Sampling (CDS) or Black-Level Compensation The CLAMP circuit in the MAX1101 can be used to either accomplish CDS or to compensate for the CCD black level. To accomplish CDS, CLAMP is activated once per _______________________________________________________________________________________ 9 MAX1101 Single-Chip, 8-Bit CCD Digitizer with Clamp and 6-Bit PGA pixel during the CCD output waveform’s reset phase. To compensate for the CCD black level, CLAMP is activated during the black-pixel portion of the linear array, as shown in Figure 10. Each of these modes requires a different value of CEXT, as described in the following section. Choosing CEXT for CDS In CDS applications, CEXT = 4nF. This value is the best compromise to minimize errors due to the CLAMP switch resistance/CEXT time constant and switch charge injection. The following equation represents the error due to incomplete charging of CEXT during integration time: ε = ∆VRESET x e-t/RC where ∆VRESET = the maximum change in reset level from one pixel to the next, t = CLAMP pulse width, and R = CLAMP switch resistance (150Ωmax). At a sample rate of 670kHz, with t = 750nsec, a 4nF capacitor removes at least 70% of the change in reset voltage level. Typically, R = 60Ω, which corresponds to a 96% cancellation of the change in reset level. The offset due to switch charge injection is represented by 13pC / 4nF = 3mV. Note that this error will behave like any DC offset; that is, it will be constant from pixel to pixel. Choosing CEXT in Black-Level Compensation In activating CLAMP once per line to compensate for the CCD black level, the recommended value of CEXT is governed by the following equations: CEXT ≥ 12nF and CEXT ≤ N x t x 760pF/µsec where N is the number of light-shielded cells, and t is the width of the CLAMP pulse in µsec. The second equation ensures that the time constant formed by R x CEXT is small enough that the black level is captured to within 0.5mV during the dark pixel phase. For example, in an array with 27 dark pixels at a 670kHz sample rate, with t = 750nsec, the second equation becomes CEXT ≤ 15nF. Capacitors smaller than 12nF can be used; however, offset increases due to switch charge injection, as explained in the section Choosing CEXT for CDS. DIGITAL OUTPUT 11. . .111 11. . .110 11. . .101 100. . .000 00. . .111 00. . .110 00. . .101 00. . .100 00. . .011 00. . .010 00. . .001 VVIDEO 00. . .000 -1 V 1 V 3 V -3 V FS FS FS FS 256 256 256 256 -4 V -2 V 2 V FS FS FS 256 256 256 VFS = 124 V FS 256 VREF+ - VREFGPGA VVIDEO = VOLTAGE DIFFERENCE BETWEEN THE VIDEO LEVEL AND THE PRE-CHARGE (RESET) LEVEL. Figure 11. Transfer Function for CCDIN DIGITAL OUTPUT 111. . . . 111 111. . . . 110 111. . . . 101 100. . . 000 000. . . 011 000. . . 010 000. . . 001 VAIN_ 000. . . 000 1 V 3 V FS FS 256 256 2 V 4 V FS FS VREF256 256 253 V 255 V FS FS 256 256 254 V FS 256 VFS = VREF+ - VREF- Figure 12. Transfer Function for AIN 10 249 V 251 V FS FS 256 256 250 V FS 256 ______________________________________________________________________________________ Single-Chip, 8-Bit CCD Digitizer with Clamp and 6-Bit PGA MAX1101-FIG13 100.00 TOP VIEW ERROR (BITS) 10.00 1.00 GND 1 24 GND CCDIN 2 23 VDD GND 3 22 BLKSAMP AIN1 4 0.10 GND 5 0.01 3 4 5 6 7 8 9 10 21 VIDSAMP MAX1101 20 LOAD AIN2 6 19 DATA GND 7 18 SCLK I.C. 8 17 MODE I.C. 9 16 GND I.C. 10 15 VDD NUMBER OF TIME CONSTANTS Figure 13. Black Level Error vs. CEXT Time Constant at Maximum PGA Gain (1mV/bit) REFGND 11 14 REFBIAS REF- 12 13 REF+ Bypassing and Layout Considerations Solder the MAX1101 to a multilayer board (two or more layers) where the layer immediately beneath the device is a ground plane. Connect the VDD pins together at the MAX1101. Connect all ground pins together at the device. Bypass VDD to ground with at least a 0.1µF ceramic capacitor. If larger capacitors are used, tantalum is satisfactory. SO ___________________Chip Information TRANSISTOR COUNT: 3430 ______________________________________________________________________________________ 11 MAX1101 __________________Pin Configuration ________________________________________________________Package Information SOICW.EPS MAX1101 Single-Chip, 8-Bit CCD Digitizer with Clamp and 6-Bit PGA Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 © 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.