LTC2602/LTC2612/LTC2622 Dual 16-/14-/12-Bit Rail-to-Rail DACs in 8-Lead MSOP U DESCRIPTIO FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Smallest Pin-Compatible Dual DACs: LTC2602: 16-Bits LTC2612: 14-Bits LTC2622: 12-Bits Guaranteed 16-Bit Monotonic Over Temperature Wide 2.5V to 5.5V Supply Range Low Power Operation: 300µA per DAC at 3V Individual Channel Power-Down to 1µA, Max Ultralow Crosstalk between DACs (30µV) High Rail-to-Rail Output Drive (±15mA) Double-Buffered Data Latches Pin-Compatible 10-Bit Version (LTC1661) Tiny 8-Lead MSOP Package U APPLICATIO S ■ ■ ■ ■ Mobile Communications Process Control and Industrial Automation Instrumentation Automatic Test Equipment The LTC®2602/LTC2612/LTC2622 are dual 16-,14- and 12-bit, 2.5V-to-5.5V rail-to-rail voltage-output DACs, in a tiny 8-lead MSOP package. They have built-in high performance output buffers and are guaranteed monotonic. These parts establish advanced performance standards for output drive, crosstalk and load regulation in singlesupply, voltage output multiples. The parts use a simple SPI/MICROWIRE™ compatible 3-wire serial interface which can be operated at clock rates up to 50MHz. The LTC2602/LTC2612/LTC2622 incorporate a poweron reset circuit. During power-up, the voltage outputs rise less than 10mV above zero scale, and after powerup, they stay at zero scale until a valid write and update take place. , LTC and LT are registered trademarks of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation. W BLOCK DIAGRA REGISTER Differential Nonlinearity (DNL)(LTC2602) REGISTER 16-BIT DAC A REGISTER VOUT A 8 REGISTER LTC2602 1.0 16-BIT DAC B VCC = 5V VREF = 4.096V 0.8 5 VOUT B 0.6 6 VCC GND 7 CS/LD 1 CONTROL LOGIC ERROR (LSB) 0.4 0.2 0 –0.2 –0.4 DECODE 4 REF –0.6 –0.8 SCK 2 24-BIT SHIFT REGISTER 3 SDI 2602 BD01 –1.0 0 16384 32768 CODE 49152 65535 2602 TA01 2602f 1 LTC2602/LTC2612/LTC2622 W U U W W W AXI U U ABSOLUTE PACKAGE/ORDER I FOR ATIO RATI GS (Note 1) Any Pin to GND ........................................... – 0.3V to 6V Any Pin to VCC ........................................................ –6V to 0.3V Maximum Junction Temperature ......................... 125°C Operating Temperature Range LTC2602C/LTC2612C/LTC2622C .......... 0°C to 70°C LTC2602I/LTC2612I/LTC2622I .......... – 40°C to 85°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................ 300°C ORDER PART NUMBER LTC2602CMS8 LTC2602IMS8 LTC2612CMS8 LTC2612IMS8 LTC2622CMS8 LTC2622IMS8 TOP VIEW CS/LD SCK SDI REF 8 7 6 5 1 2 3 4 VOUT A GND VCC VOUT B MS8 PACKAGE 8-LEAD PLASTIC MSOP MS8 PART MARKING TJMAX = 125°C, θJA = 300°C/W LTACX LTACY LTACZ LTADA LTADB LTADC Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.5V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN LTC2622 TYP MAX MIN LTC2612 TYP MAX MIN LTC2602 TYP MAX UNITS DC Performance Resolution Monotonicity ● 12 14 16 Bits VCC = 5V, VREF = 4.096V (Note 2) ● 12 14 16 Bits ±0.5 ±1 LSB ±3 ±16 ±12 ±64 LSB 0.025 0.125 0.05 0.125 0.1 0.2 0.5 0.5 0.4 0.65 2 2 LSB/mA LSB/mA 0.05 0.1 0.2 0.4 1 1 0.9 1.3 4 4 LSB/mA LSB/mA DNL Differential Nonlinearity VCC = 5V, VREF = 4.096V (Note 2) ● INL Integral Nonlinearity VCC = 5V, VREF = 4.096V (Note 2) ● ±0.75 Load Regulation VREF = VCC = 5V, Midscale IOUT = 0mA to 15mA Sourcing IOUT = 0mA to 15mA Sinking ● ● VREF = VCC = 2.5V, Midscale IOUT = 0mA to 7.5mA Sourcing IOUT = 0mA to 7.5mA Sinking ● ● ±4 0.25 0.25 ±1 ZSE Zero-Scale Error VCC = 5V, VREF = 4.096V Code = 0 ● 1 9 1 9 1 9 mV VOS Offset Error VCC = 5V, VREF = 4.096V, (Note 7) ● ±1 ±9 ±1 ±9 ±1 ±9 mV ±5 VOS Temperature Coefficient GE Gain Error Gain Temperature Coefficient VCC = 5V, VREF = 4.096V ● ±0.1 ±0.7 ±3 ±5 ±0.1 ±0.7 ±3 ±5 ±0.1 ±0.7 ±3 µV/°C %FSR ppm/°C 2602f 2 LTC2602/LTC2612/LTC2622 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.5V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted. LTC2602/LTC2612/LTC2622 MIN TYP MAX –80 SYMBOL PSRR PARAMETER Power Supply Rejection Ratio CONDITIONS VCC = 5V ±10% ROUT DC Output Impedance VREF = VCC = 5V, Midscale; –15mA ≤ IOUT ≤ 15mA VREF = VCC = 2.5V, Midscale; –7.5mA ≤ IOUT ≤ 7.5mA DC Crosstalk (Note 4) Due to Full Scale Output Change (Note 5) Due to Load Current Change Due to Powering Down (per Channel) Short-Circuit Output Current VCC = 5.5V, VREF = 5.5V Code: Zero Scale; Forcing Output to VCC Code: Full Scale; Forcing Output to GND ● ● 15 15 34 38 60 60 mA mA VCC = 2.5V, VREF = 2.5V Code: Zero Scale; Forcing Output to VCC Code: Full Scale; Forcing Output to GND ● ● 7.5 7.5 20 28 50 50 mA mA ISC 0.05 0.05 ● ● 0.15 0.15 ±30 ±16 ±4 UNITS dB Ω Ω µV µV/mA µV Reference Input Input Voltage Range Resistance Normal Mode ● 0 ● 44 64 Capacitance IREF VCC V 80 kΩ 1 µA 5.5 V 1.3 1 1 1 mA mA µA µA 23 Reference Current, Power Down Mode All DACs Powered Down 0.001 ● pF Power Supply VCC Positive Supply Voltage For Specified Performance ● 2.5 ICC Supply Current VCC = 5V (Note 3) VCC = 3V (Note 3) All DACs Powered Down (Note 3) VCC = 5V All DACs Powered Down (Note 3) VCC = 3V ● ● ● ● VIH Digital Input High Voltage VCC = 2.5V to 5.5V VCC = 2.5V to 3.6V ● ● VIL Digital Input Low Voltage VCC = 4.5V to 5.5V VCC = 2.7V to 5.5V VCC = 2.5V to 5.5V ● ● ● 0.8 0.6 0.5 V V V ILK Digital Input Leakage VIN = GND to VCC ● ±1 µA CIN Digital Input Capacitance (Note 6) ● 8 pF 0.7 0.6 0.35 0.10 Digital I/O SYMBOL PARAMETER AC Performance ts Settling Time (Note 8) Settling Time for 1LSB Step (Note 9) en Voltage Output Slew Rate Capacitive Load Driving Glitch Impulse Multiplying Bandwidth Output Voltage Noise Density Output Voltage Noise CONDITIONS ±0.024% (±1LSB at 12 Bits) ±0.006% (±1LSB at 14 Bits) ±0.0015% (±1LSB at 16 Bits) ±0.024% (±1LSB at 12 Bits) ±0.006% (±1LSB at 14 Bits) ±0.0015% (±1LSB at 16 Bits) At Midscale Transition At f = 1kHz At f = 10kHz 0.1Hz to 10Hz MIN LTC2622 TYP MAX MIN 2.4 2.0 LTC2612 TYP MAX 7 7 9 2.7 2.7 4.8 0.80 1000 12 180 120 100 15 0.80 1000 12 180 120 100 15 V V MIN LTC2602 TYP MAX 7 9 10 2.7 4.8 5.2 0.80 1000 12 180 120 100 15 UNITS µs µs µs µs µs µs V/µs pF nV • s kHz nV/√Hz nV/√Hz µVP-P 2602f 3 LTC2602/LTC2612/LTC2622 WU TI I G CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (See Figure 1) (Note 6) SYMBOL PARAMETER LTC2602/LTC2612/LTC2622 MIN TYP MAX CONDITIONS UNITS VCC = 2.5V to 5.5V t1 SDI Valid to SCK Setup ● 4 ns t2 SDI Valid to SCK Hold ● 4 ns t3 SCK High Time ● 9 ns t4 SCK Low Time ● 9 ns t5 CS/LD Pulse Width ● 10 ns t6 LSB SCK High to CS/LD High ● 7 ns t7 CS/LD Low to SCK High ● 7 ns t10 CS/LD High to SCK Positive Edge ● 7 ns SCK Frequency 50% Duty Cycle Note 1: Absolute maximum ratings are those values beyond which the life of a device may be impaired. Note 2: Linearity and monotonicity are defined from code kL to code 2N – 1, where N is the resolution and kL is given by kL = 0.016(2N/VREF), rounded to the nearest whole code. For VREF = 4.096V and N = 16, kL = 256 and linearity is defined from code 256 to code 65,535. Note 3: Digital inputs at 0V or VCC. Note 4: DC crosstalk is measured with VCC = 5V and VREF = 4.096V, with the measured DAC at midscale, unless otherwise noted. 50 ● MHz Note 5: RL = 2kΩ to GND or VCC at the output of the DAC not being tested. Note 6: Guaranteed by design and not production tested. Note 7: Inferred from measurement at code 256 (LTC2602), code 64 (LTC2612) or code 16 (LTC2622), and at fullscale. Note 8: VCC = 5V, VREF = 4.096V. DAC is stepped 1/4 scale to 3/4 scale and 3/4 scate to 1/4 scale. Load is 2k in parallel with 200pF to GND. Note 9: VCC = 5V, VREF = 4.096V. DAC is stepped ±LBS between half scale and half scale –1. Load is 2k in parallel with 200pF to GND. U W TYPICAL PERFOR A CE CHARACTERISTICS (LTC2602) Integral Nonlinearity (INL) 32 Differential Nonlinearity (DNL) 1.0 VCC = 5V VREF = 4.096V 24 INL vs Temperature 32 VCC = 5V VREF = 4.096V 0.8 24 0.6 16 0 –8 0.2 INL (LSB) DNL (LSB) INL (LSB) 16 0.4 8 VCC = 5V VREF = 4.096V 0 –0.2 INL (POS) 8 0 –8 INL (NEG) –0.4 –16 –0.6 –24 –32 –16 –24 –0.8 –1.0 0 16384 32768 CODE 49152 65535 2602 G20 0 16384 32768 CODE 49152 65535 2602 G21 –32 –50 –30 –10 10 30 50 TEMPERATURE (°C) 70 90 2602 G22 2602f 4 LTC2602/LTC2612/LTC2622 U W TYPICAL PERFOR A CE CHARACTERISTICS (LTC2602) DNL vs Temperature INL vs VREF 1.0 DNL vs VREF 32 VCC = 5V VREF = 4.096V 0.8 0.6 1.5 VCC = 5.5V 24 VCC = 5.5V 1.0 16 0.2 0 –0.2 0 –8 DNL (NEG) 0.5 INL (POS) 8 DNL (LSB) DNL (POS) INL (LSB) DNL (LSB) 0.4 INL (NEG) DNL (POS) 0 DNL (NEG) –0.5 –0.4 –16 –0.6 –1.0 –24 –0.8 –1.0 –50 –30 –10 10 30 50 TEMPERATURE (°C) 70 –32 90 1 0 2 3 VREF (V) 4 2602 G23 5 –1.5 0 1 2 3 VREF (V) 4 2602 G24 Settling to ±1LSB 5 2602 G25 Settling of Full-Scale Step VOUT 100µV/DIV VOUT 100µV/DIV 12.3µs 9.7µs CS/LD 2V/DIV CS/LD 2V/DIV 2602 G26 2µs/DIV 5µs/DIV VCC = 5V, VREF = 4.096V 1/4-SCALE TO 3/4-SCALE STEP RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS 2602 G27 VCC = 5V, VREF = 4.096V CODE 512 TO 65535 STEP AVERAGE OF 2048 EVENTS SETTLING TO ±1LSB (LTC2612) 1.0 VCC = 5V VREF = 4.096V 6 Settling to ±1LSB Differential Nonlinearity (DNL) Integral Nonlinearity (INL) 8 VCC = 5V VREF = 4.096V 0.8 0.6 4 DNL (LSB) INL (LSB) 0.4 2 0 –2 VOUT 100µV/DIV 0.2 0 CS/LD 2V/DIV –0.2 –0.6 –6 –8 8.9µs –0.4 –4 2µs/DIV –0.8 0 4096 8192 CODE 12288 16383 2602 G28 –1.0 0 4096 8192 CODE 12288 16383 2602 G30 VCC = 5V, VREF = 4.096V 1/4-SCALE TO 3/4-SCALE STEP RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS 2602 G29 2602f 5 LTC2602/LTC2612/LTC2622 U W TYPICAL PERFOR A CE CHARACTERISTICS (LTC2622) 2.0 1.0 VCC = 5V VREF = 4.096V 1.5 Settling to ±1LSB Differential Nonlinearity (DNL) Integral Nonlinearity (INL) VCC = 5V VREF = 4.096V 0.8 0.6 1.0 DNL (LSB) 0.5 INL (LSB) 6.8µs 0.4 0 –0.5 VOUT 1mV/DIV 0.2 0 CS/LD 2V/DIV –0.2 –0.4 –1.0 –0.6 –1.5 –2.0 –1.0 1024 0 2048 CODE 3072 4095 2602 G33 2µs/DIV –0.8 0 1024 2048 CODE 3072 VCC = 5V, VREF = 4.096V 1/4-SCALE TO 3/4-SCALE STEP RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS 4095 2602 G32 2602 G31 (LTC2602/LTC2612/LTC2622) Current Limiting CODE = MIDSCALE ∆VOUT (V) 0.4 0.02 0 –0.02 VREF = VCC = 3V –0.04 0.2 0 –0.2 VREF = VCC = 5V –0.4 VREF = VCC = 5V –0.06 2 0.6 VREF = VCC = 3V 0.04 CODE = MIDSCALE 0.8 VREF = VCC = 5V 0.06 3 OFFSET ERROR (mV) 0.08 Offset Error vs Temperature Load Regulation 1.0 ∆VOUT (mV) 0.10 –1 –2 –0.8 –0.10 10 –40 –30 –20 –10 0 IOUT (mA) 20 30 –1.0 –35 40 –25 –15 –5 5 IOUT (mA) 15 2602 G01 25 –3 –50 35 Zero-Scale Error vs Temperature Gain Error vs Temperature 90 Offset Error vs VCC 2 0.2 OFFSET ERROR (mV) GAIN ERROR (%FSR) 1.0 70 3 0.3 2.5 1.5 –10 10 30 50 TEMPERATURE (°C) 2602 G03 0.4 2.0 –30 2602 G02 3 ZERO-SCALE ERROR (mV) 0 VREF = VCC = 3V –0.6 –0.08 1 0.1 0 –0.1 1 0 –1 –0.2 0.5 0 –50 –2 –0.3 –30 –10 10 30 50 TEMPERATURE (°C) 70 90 2602 G04 –0.4 –50 –30 –10 10 30 50 TEMPERATURE (°C) 70 90 2602 G05 –3 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 2602 G06 2602f 6 LTC2602/LTC2612/LTC2622 U W TYPICAL PERFOR A CE CHARACTERISTICS (LTC2602/LTC2612/LTC2622) ICC Shutdown vs VCC 450 0.3 400 0.2 350 0.1 300 ICC (nA) GAIN ERROR (%FSR) Gain Error vs VCC 0.4 0 –0.1 Large-Signal Settling VOUT 0.5V/DIV 250 200 VREF = VCC = 5V 1/4-SCALE TO 3/4-SCALE 150 –0.2 100 –0.3 2.5µs/DIV 50 –0.4 2.5 3.5 3 4 VCC (V) 4.5 5 5.5 0 2.5 3 3.5 4 VCC (V) 4.5 5 2602 G09 5.5 2602 G08 2602 G07 Midscale Glitch Impulse Headroom at Rails vs Output Current Power-On Reset Glitch 5.0 5V SOURCING 4.5 4.0 VOUT 10mV/DIV 3.5 12nV-s TYP VOUT (V) VCC 1V/DIV 4mV 4mVPEAK PEAK CS/LD 5V/DIV VOUT 10mV/DIV 2.5 2.0 1.5 2602 G10 2.5µs/DIV 3V SOURCING 3.0 250µs/DIV 5V SINKING 1.0 2602 G11 3V SINKING 0.5 0 0 1 2 3 4 5 6 IOUT (mA) 7 8 9 10 2602 G12 Supply Current vs Logic Voltage Exiting Power-Down to Midscale VCC = 5V SWEEP SCK, SDI AND CS/LD 0V TO VCC 2.3 2.2 VCC = 5V VREF = 2V –6 –9 –12 –15 2.0 ONE DAC IN POWER DOWN MODE 1.9 dB ICC (mA) –3 VOUT 0.5V/DIV 2.1 –18 –21 CS/LD 5V/DIV 1.8 –24 VCC = 5V VREF (DC) = 2V VREF (AC) = 0.2VP-P CODE = FULL SCALE –27 1.7 2.5µs/DIV 1.6 1.5 Multiplying Frequency Response 0 2.4 2602 G14 –30 –33 –36 0 0.5 1 1.5 2 2.5 3 3.5 LOGIC VOLTAGE (V) 4 4.5 5 1k 10k 100k FREQUENCY (Hz) 1M 2602 G16 2602 G13 2602f 7 LTC2602/LTC2612/LTC2622 U W TYPICAL PERFOR A CE CHARACTERISTICS (LTC2602/LTC2612/LTC2622) Output Voltage Noise, 0.1Hz to 10Hz Short-Circuit Output Current vs VOUT (Sourcing) Short-Circuit Output Current vs VOUT (Sinking) 10mA/DIV VOUT 10µV/DIV 0 1 2 3 4 5 6 SECONDS 7 8 9 10 2602 G17 10mA/DIV 0mA 0mA VCC = 5.5V VREF = 5.6V CODE = 0 VOUT SWEPT 0V TO VCC 1V/DIV VCC = 5.5V VREF = 5.6V CODE = FULL SCALE VOUT SWEPT VCC TO 0V 2602 G18 1V/DIV 2602 G19 2602f 8 LTC2602/LTC2612/LTC2622 U U U PIN FUNCTIONS CS/LD (Pin 1): Serial Interface Chip Select/Load Input. When CS/LD is low, SCK is enabled for shifting data on SDI into the register. When CS/LD is taken high, SCK is disabled and the specified command (see Table 1) is executed. SCK (Pin 2): Serial Interface Clock Input. CMOS and TTL compatible. SDI (Pin 3): Serial Interface Data Input. Data is applied to SDI for transfer to the device at the rising edge of SCK. The LTC2602/LTC2612/LTC2622 accept input word lengths of either 24 or 32 bits. REF (Pin 4): Reference Voltage Input. 0V ≤ VREF ≤ VCC. VOUT B and VOUT A (Pins 5 and 8): DAC Analog Voltage Outputs. The output range is 0 – VREF. VCC (Pin 6): Supply Voltage Input. 2.5V ≤ VCC ≤ 5.5V. GND (Pin 7): Analog Ground. W DAC REGISTER INPUT REGISTER DAC A INPUT REGISTER VOUT A 8 DAC REGISTER BLOCK DIAGRA 5 VOUT B DAC B 6 VCC GND 7 CONTROL LOGIC CS/LD 1 DECODE 4 REF 24-BIT SHIFT REGISTER SCK 2 3 SDI 2602 BD WU W TI I G DIAGRA t1 t2 SCK t3 1 t6 t4 2 3 23 24 t10 SDI C3 t5 C2 C1 D1 D0 t7 CS/LD 2602 F01 Figure 1 2602f 9 LTC2602/LTC2612/LTC2622 U OPERATIO Power-On Reset The LTC2602/LTC2612/LTC2622 clear the outputs to zero scale when power is first applied, making system initialization consistent and repeatable. For some applications, downstream circuits are active during DAC power-up, and may be sensitive to nonzero outputs from the DAC during this time. The LTC2602/ LTC2612/LTC2622 contain circuitry to reduce the poweron glitch; furthermore, the glitch amplitude can be made smaller by reducing the ramp rate of the power supply. For example, if the power supply is ramped to 5V in 1ms, the analog outputs rise less than 10mV above ground (typ) during power-on. See Power-On Reset Glitch in the Typical Performance Characteristics section. Power Supply Sequencing The voltage at REF (Pin 4) should be kept within the range – 0.3V ≤ VREF ≤ VCC + 0.3V (see Absolute Maximum Ratings). Particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at VCC (Pin 6) is in transition. Transfer Function The digital-to-analog transfer function is k VOUT(IDEAL) = N VREF 2 where k is the decimal equivalent of the binary DAC input code, N is the resolution and VREF is the voltage at REF (Pin 4). Table 1. COMMAND* C3 C2 C1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 ADDRESS (n)* A3 A2 A1 0 0 0 0 0 0 1 1 1 C0 0 1 0 1 0 1 Write to Input Register n Update (Power Up) DAC Register n Write to Input Register n, Update (Power Up) All n Write to and Update (Power Up) n Power Down n No Operation A0 0 1 1 DAC A DAC B All DACs *Command and address codes not shown are reserved and should not be used. Serial Interface The CS/LD input is level triggered. When this input is taken low, it acts as a chip-select signal, activating the SDI and SCK buffers and enabling the input shift register. Data (SDI input) is transferred at the next 24 rising SCK edges. The 4-bit command, C3-C0, is loaded first; then the 4-bit DAC address, A3-A0; and finally the 16-bit data word. The data word comprises the 16-, 14- or 12-bit input code, ordered MSB-to-LSB, followed by 0, 2 or 4 don’t-care bits (LTC2602, LTC2612 and LTC2622 respectively). Data can only be transferred to the device when the CS/LD signal is low.The rising edge of CS/LD ends the data transfer and causes the device to carry out the action specified in the 24-bit input word. The complete sequence is shown in Figure 2a. The command (C3-C0) and address (A3-A0) assignments are shown in Table 1. The first four commands in the table consist of write and update operations. A write operation loads a 16-bit data word from the 32-bit shift register into the input register of the selected DAC, n. An update operation copies the data word from the input register to the DAC register. Once copied into the DAC register, the data word becomes the active 16-, 14- or 12-bit input code, and is converted to an analog voltage at the DAC output. The update operation also powers up the selected DAC if it had been in power-down mode. The data path and registers are shown in the block diagram. While the minimum input word is 24 bits, it may optionally be extended to 32 bits to accommodate microprocessors which have a minimum word width of 16 bits (2 bytes). To use the 32-bit word width, 8 don’t-care bits are transferred to the device first, followed by the 24-bit word as just described. Figure 2b shows the 32-bit sequence. Power-Down Mode For power-constrained applications, power-down mode can be used to reduce the supply current whenever less than two outputs are needed. When in power-down, the buffer amplifiers, bias circuits and reference inputs are disabled, and draw essentially zero current. The DAC outputs are put into a high-impedance state, and the 2602f 10 LTC2602/LTC2612/LTC2622 U OPERATIO INPUT WORD (LTC2602) COMMAND C3 C2 C1 C0 ADDRESS A3 A2 A1 DATA (16 BITS) A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB 2602 TBL01 INPUT WORD (LTC2612) COMMAND C3 C2 C1 C0 ADDRESS A3 A2 A1 DATA (14 BITS + 2 DON’T-CARE BITS) A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB X X LSB 2602 TBL02 INPUT WORD (LTC2622) COMMAND C3 C2 C1 C0 ADDRESS A3 A2 A1 DATA (12 BITS + 4 DON’T-CARE BITS) A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 MSB D2 D1 D0 X X X X LSB 2602 TBL03 output pins are passively pulled to ground through individual 90kΩ resistors. Input- and DAC-register contents are not disturbed during power-down. Either channel or both channels can be put into powerdown mode by using command 0100b in combination with the appropriate DAC address, (n). The 16-bit data word is ignored. The supply and reference currents are reduced by approximately 50% for each DAC powered down; the effective resistance at REF (pin 4) rises accordingly, becoming a high-impedance input (typically > 1GΩ) when both DACs are powered down. Normal operation can be resumed by executing any command which includes a DAC update, as shown in Table 1. The selected DAC is powered up as its voltage output is updated. When a DAC which is in a powered-down state is powered up and updated, normal settling is delayed. If one of the two DACs is in a powered-down state prior to the update command, the power-up delay is 5µs. If, on the other hand, both DACs are powered down, then the main bias generation circuit block has been automatically shut down in addition to the individual DAC amplifiers and reference inputs. In this case, the power up delay time is 12µs (for VCC = 5V) or 30µs (for VCC = 3V). Voltage Outputs Each of the two rail-to-rail amplifiers contained in these parts has guaranteed load regulation when sourcing or sinking up to 15mA at 5V (7.5mA at 3V). Load regulation is a measure of the amplifier’s ability to maintain the rated voltage accuracy over a wide range of load conditions. The measured change in output voltage per milliampere of forced load current change is expressed in LSB/mA. DC output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from LSB/mA to Ohms. The amplifiers’ DC output impedance is 0.050Ω when driving a load well away from the rails. When drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 25Ω typical channel resistance of the output devices; e.g., when sinking 1mA, the minimum output voltage = 25Ω • 1mA = 25mV. See the graph Headroom at Rails vs Output Current in the Typical Performance Characteristics section. The amplifiers are stable driving capacitive loads of up to 1000pF. 2602f 11 LTC2602/LTC2612/LTC2622 U OPERATIO Board Layout The excellent load regulation and DC crosstalk performance of these devices is achieved in part by keeping “signal” and “power” grounds separated internally and by reducing shared internal resistance. The GND pin functions both as the node to which the reference and output voltages are referred and as a return path for power currents in the device. Because of this, careful thought should be given to the grounding scheme and board layout in order to ensure rated performance. The PC board should have separate areas for the analog and digital sections of the circuit. This keeps digital signals away from sensitive analog signals and facilitates the use of separate digital and analog ground planes which have minimal capacitive and resistive interaction with each other. Digital and analog ground planes should be joined at only one point, establishing a system star ground as close to the device’s ground pin as possible. Ideally, the analog ground plane should be located on the component side of the board, and should be allowed to run under the part to shield it from noise. Analog ground should be a continuous and uninterrupted plane, except for necessary lead pads and vias, with signal traces on another layer. The GND pin of the part should be connected to analog ground. Resistance from the GND pin to system star ground should be as low as possible. Resistance here will add directly to the effective DC output impedance of the device (typically 0.050Ω), and will degrade DC crosstalk. Note that the LTC2602/LTC2612/LTC2622 are no more susceptible to these effects than other parts of their type; on the contrary, they allow layout-based performance improvements to shine rather than limiting attainable performance with excessive internal resistance. Rail-to-Rail Output Considerations In any rail-to-rail voltage output device, the output is limited to voltages within the supply range. Since the analog outputs of the device cannot go below ground, they may limit for the lowest codes as shown in Figure 3b. Similarly, limiting can occur near full scale when the REF pin is tied to VCC. If VREF = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC as shown in Figure 3c. No full-scale limiting can occur if VREF is less than VCC – FSE. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur. 2602f 12 SDI SCK CS/LD X 1 X 2 3 X 4 X C3 SDI C2 2 C1 3 DON’T CARE X 5 X 6 X 7 COMMAND WORD 1 SCK CS/LD X C0 4 8 A1 7 ADDRESS WORD A2 6 A0 8 D15 9 D14 10 D12 12 D11 13 D10 14 24-BIT INPUT WORD D13 11 D9 15 D7 17 DATA WORD D8 16 D6 18 C1 11 COMMAND WORD C2 10 C0 12 A3 A2 14 A1 15 ADDRESS WORD 13 A0 16 D15 17 D14 18 D13 19 D12 20 D11 21 D10 22 Figure 2b. LTC2602 32-Bit Load Sequence LTC2612 SDI Data Word 14-Bit Input Code + 2 Don’t Care Bits LTC2622 SDI Data Word 12-Bit Input Code + 4 Don’t Care Bits C3 9 D9 23 19 D5 Figure 2a. LTC2602 24-Bit Load Sequence (Minimum Input Word) LTC2612 SDI Data Word 14-Bit Input Code + 2 Don’t Care Bits LTC2622 SDI Data Word 12-Bit Input Code + 4 Don’t Care Bits A3 5 24 25 D7 D3 21 DATA WORD D8 D4 20 26 D6 D2 22 27 D5 D1 23 28 D4 D0 24 D3 29 YYYY F02a D2 30 D1 31 D0 32 2602 F02b LTC2602/LTC2612/LTC2622 U OPERATIO 2602f 13 LTC2602/LTC2612/LTC2622 U OPERATIO VREF = VCC VREF = VCC POSITIVE FSE OUTPUT VOLTAGE OUTPUT VOLTAGE INPUT CODE (c) OUTPUT VOLTAGE 0 65, 535 (a) 0V NEGATIVE OFFSET 32, 768 INPUT CODE INPUT CODE (b) 2600 F03 Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Codes Near Full Scale 2602f 14 LTC2602/LTC2612/LTC2622 U PACKAGE DESCRIPTIO MS8 Package 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1660) 0.889 ± 0.127 (.035 ± .005) 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 0.42 ± 0.038 (.0165 ± .0015) TYP 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 0.65 (.0256) BSC 8 7 6 5 0.52 (.0205) REF RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 4.90 ± 0.152 (.193 ± .006) DETAIL “A” 0° – 6° TYP GAUGE PLANE 0.53 ± 0.152 (.021 ± .006) DETAIL “A” 1 2 3 4 1.10 (.043) MAX 0.86 (.034) REF 0.18 (.007) SEATING PLANE 0.22 – 0.38 (.009 – .015) TYP 0.65 (.0256) BSC 0.127 ± 0.076 (.005 ± .003) MSOP (MS8) 0603 NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 2602f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LTC2602/LTC2612/LTC2622 RELATED PARTS PART NUMBER LTC1458/LTC1458L DESCRIPTION Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality LTC1654 LTC1655/LTC1655L LTC1657/LTC1657L LTC1660/LTC1665 LTC1661 LTC1821 LTC2600/LTC2610/ LTC2620 Dual 14-Bit Rail-to-Rail VOUT DAC Single 16-Bit VOUT DAC with Serial Interface in SO-8 Parrallel 5V/3V 16-Bit VOUT DAC Octal 10/8-Bit VOUT DAC in 16-Pin Narrow SSOP Dual 10-Bit VOUT DAC in 8-Lead MSOP Package Parallel 16-Bit Voltage Output DAC Octal 16/14/12-Bit Rail-to-Rail DACs in 16-Lead SSOP COMMENTS LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.096V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Programmable Speed/Power, 3.5µs/750µA, 8µs/450µA VCC = 5V(3V), Low Power, Deglitched Low Power, Deglitched, Rail-to-Rail VOUT VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output VCC = 2.7V to 5.5V, 60µA per DAC, Rail-to-Rail Output Precision 16-Bit Settling in 2µs for 10V Step 250µA per DAC, 2.5V to 5.5V Supply Range Rail-to-Rail Output 2602f 16 Linear Technology Corporation LT/TP 1003 1K • PRINTED IN THE USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2003