LTC2654 Quad 16-/12-Bit Rail-to-Rail DACs with 10ppm/°C Max Reference DESCRIPTION FEATURES n n n n n n n n n n n Precision Reference 10ppm/°C Max Maximum INL Error: ±4LSB at 16-Bits Low ±2mV (Max) Offset Error Guaranteed Monotonic Over Temperature Selectable Internal or External Reference 2.7V to 5.5V Supply Range (LTC2654-L) Integrated Reference Buffers Ultralow Crosstalk Between DACs (<3nV•s) Power-on-Reset to Zero-Scale/Mid-Scale Asynchronous DAC Update Pin Tiny 20-Lead 4mm × 4mm QFN and 16-Lead Narrow SSOP Packages APPLICATIONS n n n n n Mobile Communications Process Control and Industrial Automation Instrumentation Automatic Test Equipment Automotive The LTC®2654 is a family of quad 16-/12-bit rail-to-rail DACs with integrated 10ppm/°C maximum reference . The DACs have built-in high performance, rail-to-rail, output buffers and are guaranteed monotonic. The LTC2654-L has a full-scale output of 2.5V with the integrated reference and operates from a single 2.7V to 5.5V supply. The LTC2654-H has a full-scale output of 4.096V with the integrated reference and operates from a 4.5V to 5.5V supply. Each DAC can also operate with an external reference, which sets the full-scale output to 2 times the external reference voltage. These DACs communicate via a SPI/MICROWIRE™ compatible 4-wire serial interface which operates at clock rates up to 50MHz. The LTC2654 incorporates a power-on reset circuit that is controlled by the PORSEL pin. If PORSEL is tied to GND the DACs reset to zero-scale. If PORSEL is tied to VCC, the DACs reset to mid-scale. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. SPI/MICROWIRE is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5396245, 6891433 and patent pending. BLOCK DIAGRAM REFCOMP REFIN/OUT INTERNAL REFERENCE GND INL Curve VCC 4 DAC D DAC C 2 VOUTC 1 0 –1 –2 –3 CS/LD CONTROL LOGIC DECODE POWER-ON RESET PORSEL SDO SCK SDI LDAC VCC = 5V 3 VOUTD INL (LSB) REGISTER REGISTER REGISTER REGISTER REGISTER DAC B REGISTER VOUTB DAC A REGISTER VOUTA REGISTER REFLO 32-BIT SHIFT REGISTER –4 128 16384 32768 CODE 49152 65535 2654 TA01b CLR 2654 TA01a 2654f 1 LTC2654 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltage (VCC) ................................... –0.3V to 6V CS/LD, SCK, SDI, LDAC, CLR, REFLO .......... –0.3V to 6V VOUTA-D ............................–0.3V to Min (VCC + 0.3V, 6V) REFIN/OUT, REFCOMP .....–0.3V to Min (VCC + 0.3V, 6V) PORSEL, SDO ..................–0.3V to Min (VCC + 0.3V, 6V) Operating Temperature Range LTC2654C ................................................ 0°C to 70°C LTC2654I..............................................–40°C to 85°C Maximum Junction Temperature........................... 150°C Storage Temperature Range................... –65°C to 150°C Lead Temperature (Soldering GN-Package, 10 sec) ....................... 300°C PIN CONFIGURATION 15 VCC 3 14 VOUTD VOUTB 4 13 VOUTC REFIN/OUT 5 12 PORSEL LDAC 6 11 CLR CS/LD 7 10 SDO SCK 8 9 SDI GN PACKAGE 16-LEAD PLASTIC SSOP NARROW TJMAX = 150°C, θJA = 110°C/W DNC DNC 15 DNC VOUTA 1 14 VOUTD REFCOMP 2 21 GND VOUTB 3 13 VOUTC 12 PORSEL REFIN/OUT 4 11 CLR LDAC 5 6 7 8 9 10 SDO 2 SDI VOUTA REFCOMP 20 19 18 17 16 DNC 16 GND SCK 1 CS/LD REFLO VCC TOP VIEW GND REFLO TOP VIEW UF PACKAGE 20-LEAD (4mm s 4mm) PLASTIC QFN TJMAX = 150°C, θJA = 37°C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB 2654f 2 LTC2654 PRODUCT SELECTOR GUIDE LTC2654 B C UF –L 16 #TR PBF LEAD FREE DESIGNATOR TAPE AND REEL TR = Tape and Reel RESOLUTION 16 = 16-Bit 12 = 12-Bit FULL-SCALE VOLTAGE, INTERNAL REFERENCE MODE L = 2.5V H = 4.096V PACKAGE TYPE UF = 20-Lead (4mm × 4mm) Plastic QFN GN = 16-Lead Narrow SSOP TEMPERATURE GRADE C = Commercial Temperature Range (0°C to 70°C) I = Industrial Temperature Range (–40°C to 85°C) ELECTRICAL GRADE (OPTIONAL) B = ±4LSB INL (MAX) PRODUCT PART NUMBER Consult LTC Marketing for information on non-standard lead based finish parts. Consult LTC Marketing for parts specified with wider operating temperature ranges. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 2654f 3 LTC2654 ORDER INFORMATION TEMPERATURE RANGE MAXIMUM INL 16-Lead Narrow SSOP 0°C to 70°C ±4 16-Lead Narrow SSOP –40°C to 85°C ±4 20-Lead (4mm × 4mm) Plastic QFN 0°C to 70°C ±4 20-Lead (4mm × 4mm) Plastic QFN –40°C to 85°C ±4 16-Lead Narrow SSOP 0°C to 70°C ±4 654H16 16-Lead Narrow SSOP –40°C to 85°C ±4 LTC2654BCUF-H16#TRPBF 54H16 20-Lead (4mm × 4mm) Plastic QFN 0°C to 70°C ±4 LTC2654BIUF-H16#TRPBF 54H16 20-Lead (4mm × 4mm) Plastic QFN –40°C to 85°C ±4 LTC2654CGN-L12#TRPBF 654L12 16-Lead Narrow SSOP 0°C to 70°C ±1 LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION LTC2654BCGN-L16#PBF LTC2654BCGN-L16#TRPBF 654L16 LTC2654BIGN-L16#PBF LTC2654BIGN-L16#TRPBF 654L16 LTC2654BCUF-L16#PBF LTC2654BCUF-L16#TRPBF 54L16 LTC2654BIUF-L16#PBF LTC2654BIUF-L16#TRPBF 54L16 LTC2654BCGN-H16#PBF LTC2654BCGN-H16#TRPBF 654H16 LTC2654BIGN-H16#PBF LTC2654BIGN-H16#TRPBF LTC2654BCUF-H16#PBF LTC2654BIUF-H16#PBF LTC2654CGN-L12#PBF LTC2654IGN-L12#PBF LTC2654IGN-L12#TRPBF 654L12 16-Lead Narrow SSOP –40°C to 85°C ±1 LTC2654CUF-L12#PBF LTC2654CUF-L12#TRPBF 54L12 20-Lead (4mm × 4mm) Plastic QFN 0°C to 70°C ±1 LTC2654IUF-L12#PBF LTC2654IUF-L12#TRPBF 54L12 20-Lead (4mm × 4mm) Plastic QFN –40°C to 85°C ±1 LTC2654CGN-H12#PBF LTC2654CGN-H12#TRPBF 654H12 16-Lead Narrow SSOP 0°C to 70°C ±1 LTC2654IGN-H12#PBF LTC2654IGN-H12#TRPBF 654H12 16-Lead Narrow SSOP –40°C to 85°C ±1 LTC2654CUF-H12#PBF LTC2654CUF-H12#TRPBF 54H12 20-Lead (4mm × 4mm) Plastic QFN 0°C to 70°C ±1 LTC2654IUF-H12#PBF LTC2654IUF-H12#TRPBF 54H12 20-Lead (4mm × 4mm) Plastic QFN –40°C to 85°C ±1 Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified. LTC2654B-L16/LTC2654-L12 (Internal Reference = 1.25V) LTC2654-12 SYMBOL PARAMETER CONDITIONS MIN TYP LTC2654B-16 MAX MIN TYP MAX UNITS DC Performance Resolution l 12 16 Bits 12 16 Bits Monotonicity (Note 3) l DNL Differential Nonlinearity (Note 3) l ±0.1 ±0.5 ±0.3 ±1 LSB INL Integral Nonlinearity VCC = 5.5V, VREF = 2.5V (Note 3) l ±0.5 ±1 ±2 ±4 LSB Load Regulation VCC = 5V ±10%, Integral Reference, Mid-Scale, –15mA ≤ IOUT ≤ 15mA l 0.04 0.125 0.6 2 LSB/mA VCC = 3V ±10%, Integral Reference, Mid-Scale, –7.5mA ≤ IOUT ≤ 7.5mA l 0.06 0.25 1 4 LSB/mA l 1 3 1 3 mV l ±1 ±2 ±1 ±2 ZSE Zero-Scale Error VOS Offset Error (Note 4) VOS Temperature Coefficient GE Gain Error Gain Temperature Coefficient 5 (Note 13) l ±0.02 1 5 ±0.1 ±0.02 1 mV μV/°C ±0.1 %FSR ppm/°C 2654f 4 LTC2654 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified. SYMBOL PARAMETER CONDITIONS VOUT DAC Output Span Internal Reference External Reference = VEXTREF PSR Power Supply Rejection VCC ±10% ROUT DC Output Impedance VCC = 5V ±10%, Internal Reference, Mid-Scale, –15mA ≤ IOUT ≤ 15mA VCC = 3V ±10%, Internal Reference, Mid-Scale, –7.5mA ≤ IOUT ≤ 7.5mA ISC MIN TYP MAX UNITS 0 to 2.5 0 to 2•VEXTREF V V –80 dB l 0.04 0.15 Ω l 0.04 0.15 Ω DC Crosstalk Due to Full-Scale Output Change (Note 5) Due to Load Current Change (Note 5) Due to Powering Down (per Channel) (Note 5) ±1.5 ±2 ±1 μV μV/mA μV Short-Circuit Output Current VCC = 5.5V VEXTREF = 2.8V (Note 6) Code: Zero-Scale; Forcing Output to VCC (Note 6) Code: Full-Scale; Forcing Output to GND (Note 6) l l 20 20 65 65 mA mA VCC = 2.7V VEXTREF = 1.4V Code: Zero-Scale; Forcing Output to VCC Code: Full-Scale; Forcing Output to GND l l 10 10 45 45 mA mA LTC2654B-L16/ LTC2654-L12 (Internal Reference = 1.25V) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 1.248 1.25 1.252 V ±2 ±10 Reference Reference Output Voltage Reference Temperature Coefficient (Note 7) Reference Line Regulation VCC ±10% –80 ppm/°C dB Reference Short-Circuit Current VCC = 5.5V, Forcing Output to GND l Refcomp Pin Short-Circuit Current VCC = 5.5V, Forcing Output to GND l Reference Load Regulation VCC = 3V ±10% or 5V ±10%, IOUT = 100μA Sourcing 40 mV/mA Reference Output Voltage Noise Density CREFCOMP = CREFIN/OUT = 0.1μF, at f = 1kHz 30 nV/√Hz Reference Input Range External Reference Mode (Note 13) 5 mA 200 μA 0.5 l 0.001 (Note 9) l 20 Reference Input Current Reference Input Capacitance l 3 60 VCC/2 V 1 μA pF Power Supply VCC Positive Supply Voltage For Specified Performance l ICC Supply Current VCC = 5V, Internal Reference On (Note 8) VCC = 5V, Internal Reference Off (Note 8) VCC = 3V, Internal Reference On (Note 8) VCC = 3V, Internal Reference Off (Note 8) l l l l ISD Supply Current in Shutdown Mode VCC = 5V (Note 8) l VIH Digital Input High Voltage VCC = 3.6V to 5.5V VCC = 2.7V to 3.6V l l VIL Digital Input Low Voltage VCC = 4.5V to 5.5V VCC = 2.7V to 4.5V l l VOH Digital Output High Voltage Load Current = –100μA l VOL Digital Output Low Voltage Load Current = 100μA l 2.7 1.7 1.3 1.6 1.2 5.5 V 2.5 2 2.2 1.7 mA mA mA mA 3 μA Digital I/O 2.4 2.0 V V 0.8 0.6 V V 0.4 V VCC – 0.4 V 2654f 5 LTC2654 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified. LTC2654B-L16/ LTC2654-L12 (Internal Reference = 1.25V) SYMBOL PARAMETER ILK CIN CONDITIONS Digital Input Leakage Digital Input Capacitance MIN TYP MAX UNITS VIN = GND to VCC l ±1 μA (Note 9) l 8 pF AC Performance tS Settling Time ±0.024% (±1LSB at 12 Bits) (Note 10) ±0.0015% (±1LSB at 16 Bits) (Note 10) 4.2 8.9 μs μs Settling Time for 1LSB Step ±0.024% (±1LSB at 12 Bits) ±0.0015% (±1LSB at 16 Bits) 2.2 4.9 μs μs 1.8 V/μs Voltage Output Slew Rate Capacitive Load Driving 1000 Glitch Impulse At Mid-Scale Transition (Note 11) 3 nV•s DAC-to-DAC Crosstalk Due to Full-Scale Output Change (Note 12) 3 nV•s Multiplying Bandwidth en pF 150 kHz Output Voltage Noise Density At f = 1kHz At f = 10kHz 85 80 nV/√Hz nV/√Hz Output Voltage Noise 0.1Hz to 10Hz, Internal Reference 0.1Hz to 200kHz, Internal Reference 8 400 μVP-P μVP-P The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified. LTC2654B-H16/LTC2654-H12 (Internal Reference = 2.048V) LTC2654-12 SYMBOL PARAMETER CONDITIONS MIN TYP LTC2654B-16 MAX MIN TYP MAX UNITS DC Performance l 12 16 Bits (Note 3) l 12 16 Bits (Note 3) l ±0.1 ±0.5 ±0.3 ±1 LSB l ±0.5 ±1 ±2 ±4 LSB l 0.04 0.125 0.6 2 LSB/mA l 1 3 1 3 mV l ±1 ±2 ±1 ±2 mV Resolution Monotonicity DNL Differential Nonlinearity INL Integral Nonlinearity (Note 3) VCC = 5.5V, VREF = 2.5V Load Regulation ZSE Zero-Scale Error VOS Offset Error VCC = 5V ±10%, Integral Reference, Mid-Scale, –15mA ≤ IOUT ≤ 15mA (Note 4) VOS Temperature Coefficient GE Gain Error 5 l (Note 13) ±0.1 ±0.02 1 Gain Temperature Coefficient SYMBOL PARAMETER ±0.02 5 CONDITIONS VOUT DAC Output Span Internal Reference External Reference = VEXTREF PSR Power Supply Rejection VCC ±10% ROUT DC Output Impedance VCC = 5V ±10%, Internal Reference, Mid-Scale, –15mA ≤ IOUT ≤ 15mA ±0.1 1 MIN l μV/°C TYP %FSR ppm/°C MAX UNITS 0 to 4.096 0 to 2•VEXTREF V V –80 dB 0.04 0.15 Ω 2654f 6 LTC2654 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified. SYMBOL PARAMETER ISC CONDITIONS DC Crosstalk Due to Full-Scale Output Change (Note 5) Due to Load Current Change (Note 5) Due to Powering Down (per Channel) (Note 5) Short-Circuit Output Current VCC = 5.5V VEXTREF = 2.8V (Note 6) Code: Zero-Scale; Forcing Output to VCC (Note 6) Code: Full-Scale; Forcing Output to GND (Note 6) MIN TYP MAX ±1.5 ±2 ±1 l l UNITS μV μV/mA μV 20 20 65 65 mA mA LTC2654B-H16/ LTC2654-H12 (Internal Reference = 2.048V) SYMBOL PARAMETER CONDITIONS MIN TYP MAX 2.044 UNITS Reference 2.048 2.052 Reference Temperature Coefficient Reference Output Voltage (Note 7) ±2 ±10 Reference Line Regulation VCC ±10% –80 Reference Short-Circuit Current VCC = 5.5V, Forcing Output to GND l 3 5 mA Refcomp Pin Short-Circuit Current VCC = 5.5V, Forcing Output to GND l 60 200 μA Reference Load Regulation VCC = 5V ±10%, IOUT = 100μA Sourcing 40 mV/mA Reference Output Voltage Noise Density CREFCOMP = CREFIN/OUT = 0.1μF, at f = 1kHz 35 nV/√Hz Reference Input Range External Reference Mode (Note 13) 0.5 l 0.001 (Note 9) l 20 Reference Input Current Reference Input Capacitance l V ppm/°C dB VCC/2 V 1 μA pF Power Supply VCC Positive Supply Voltage For Specified Performance l ICC Supply Current VCC = 5V, Internal Reference On (Note 8) VCC = 5V, Internal Reference Off (Note 8) l l ISD Supply Current in Shutdown Mode VCC = 5V (Note 8) l VIH Digital Input High Voltage VCC = 4.5V to 5.6V l VIL Digital Input Low Voltage VCC = 4.5V to 5.5V l 4.5 1.9 1.5 5.5 V 2.5 2 mA mA 3 μA Digital I/O 2.4 V 0.8 V VOH Digital Output High Voltage Load Current = –100μA l VOL Digital Output Low Voltage Load Current = 100μA l 0.4 V ILK Digital Input Leakage VIN = GND to VCC l ±1 μA CIN Digital Input Capacitance (Note 9) l 8 pF VCC – 0.4 V AC Performance tS Settling Time ±0.024% (±1LSB at 12 Bits) (Note 10) ±0.0015% (±1LSB at 16 Bits) (Note 10) 4.6 7.9 μs μs Settling Time for 1LSB Step ±0.024% (±1LSB at 12 Bits) ±0.0015% (±1LSB at 16 Bits) 2.0 3.8 μs μs 1.8 V/μs Voltage Output Slew Rate Capacitive Load Driving 1000 pF Glitch Impulse At Mid-Scale Transition (Note 11) 6 nV•s DAC-to-DAC Crosstalk Due to Full-Scale Output Change (Note 12) 3 nV•s 150 kHz Multiplying Bandwidth 2654f 7 LTC2654 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified. LTC2654B-H16/ LTC2654-H12 (Internal Reference = 2.048V) SYMBOL PARAMETER en CONDITIONS MIN TYP MAX UNITS Output Voltage Noise Density At f = 1kHz At f = 10kHz 85 80 nV/√Hz nV/√Hz Output Voltage Noise 0.1Hz to 10Hz, Internal Reference 0.1Hz to 200kHz, Internal Reference 12 450 μVP-P μVP-P TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. LTC2654B-L16/LTC2654-L12/LTC2654B-H16/LTC2654-H12 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VCC = 2.7V to 5.5V t1 SDI Valid to SCK Setup l 4 ns t2 SDI Valid to SCK Hold l 4 ns t3 SCK High Time l 9 ns t4 SCK Low Time l 9 ns t5 CS/LD Pulse Width l 10 ns t6 LSB SCK High to CS/LD High l 7 ns t7 CS/LD Low to SCK High l 7 ns t8 SDO Propagation Delay from SCK Falling Edge CLOAD = 10pF VCC = 4.5V to 5.5V VCC = 2.7V to 4.5V l l t9 CLR Pulse Width l 20 ns ns ns t10 CS/LD High to SCK Positive Edge l 7 ns t12 LDAC Pulse Width l 15 ns t13 CS/LD High to LDAC High or Low Transition l 200 ns SCK Frequency l 50% Duty Cycle Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltages with respect to GND. Note 3: Linearity and monotonicity are defined from code kL to code 2N–1, where N is the resolution and kL is the lower end code for which no output limiting occurs. For VREF = 2.5V and N = 16, kL = 128 and linearity is defined from code 128 to code 65535. For VREF = 2.5V and N = 12, kL = 8 and linearity is defined from code 8 to code 4,095. Note 4: Inferred from measurement at code 128 (LTC2654-16), or code 8 (LTC2654-12). Note 5: DC Crosstalk is measured with VCC = 5V and using internal reference, with the measured DAC at mid-scale. Note 6: This IC includes current limiting that is intended to protect the device during momentary overload conditions. Junction temperature can exceed the rated maximum during current limiting. Continuous operation above the specified maximum operating junction temperature may impair device reliability. 20 45 50 MHz Note 7: Temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. Maximum temperature coefficient is guaranteed for C-grade only. Note 8: Digital inputs at 0V or VCC. Note 9: Guaranteed by design and not production tested. Note 10: Internal Reference mode. DAC is stepped ¼ scale to ¾ scale and ¾ scale to ¼ scale. Load is 2kΩ in parallel with 200pF to GND. Note 11: VCC = 5V, Internal Reference mode. DAC is stepped ±1 LSB between half-scale and half-scale - 1. Load is 2kΩ in parallel with 200pF to GND. Note 12: DAC to DAC Crosstalk is the glitch that appears at the output of one DAC due to a full-scale change at the output of another DAC. It is measured with VCC = 5V and using internal reference, with the measured DAC at mid-scale. CREFIN/OUT = No Load. Note 13: Gain error specification may be degraded for reference input voltages less than 1V. See Gain Error vs Reference Input Voltage curve in the Typical Performance Characteristics section. 2654f 8 LTC2654 TYPICAL PERFORMANCE CHARACTERISTICS LTC2654-L16 Integral Nonlinearity (INL) 4 Differential Nonlinearity (DNL) 1.0 VCC = 3V INL vs Temperature 4 VCC = 3V 3 DNL (LSB) 1 0 –1 –2 2 INL (LSB) 0.5 0 INL (POS) 1 0 –1 –0.5 INL (NEG) –2 –3 –3 16384 32768 CODE 49152 –1.0 128 65535 16384 32768 CODE 49152 2654 G01 1.0 65535 –4 –50 –30 –10 10 30 50 70 90 110 130 TEMPERATURE (°C) 2654 G02 2654 G03 Reference Output Voltage vs Temperature DNL vs Temperature 1.253 VCC = 3V VCC = 3V 1.252 0.5 1.251 DNL (POS) VREF (V) DNL (LSB) INL (LSB) 2 –4 128 VCC = 3V 3 0 DNL (NEG) 1.250 1.249 –0.5 1.248 –1.0 –50 –30 –10 10 30 50 70 90 110 130 TEMPERATURE (°C) 1.247 –50 –30 –10 10 30 50 70 90 110 130 TEMPERATURE (°C) 2654 G05 2654 G04 Sampling to ±1LSB Rising Sampling to ±1LSB Falling CS/LD 3V/DIV VOUT 200μV/DIV 8.1μs 8μs VOUT 200μV/DIV CS/LD 3V/DIV 2μs/DIV 1/4 SCALE TO 3/4 SCALE STEP VCC = 3V, VFS = 2.50V RL = 2k, CL = 200pF 2654 G06 2μs/DIV 3/4 SCALE TO 1/4 SCALE STEP VCC = 3V, VFS = 2.50V RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS 2654 G07 2654f 9 LTC2654 TYPICAL PERFORMANCE CHARACTERISTICS LTC2654-H16 Integral Nonlinearity (INL) 4 Differential Nonlinearity (DNL) 1.0 VCC = 5V INL vs Temperature 4 VCC = 5V 3 0.5 0 –1 –2 2 INL (LSB) 1 DNL (LSB) INL (LSB) 2 0 INL (POS) 1 0 –1 INL (NEG) –0.5 –2 –3 –4 128 VCC = 5V 3 –3 32768 CODE 16384 49152 65535 –1.0 128 16384 32768 CODE 49152 2654 G08 –4 –50 –30 –10 10 30 50 70 90 110 130 TEMPERATURE (°C) 2654 G09 2654 G10 Reference Output Voltage vs Temperature DNL vs Temperature 1.0 65535 2.054 VCC = 5V VCC = 5V 2.052 0.5 VREF (V) DNL (LSB) 2.050 DNL (POS) 0 DNL (NEG) 2.048 2.046 –0.5 2.044 –1.0 –50 –30 –10 10 30 50 70 90 110 130 TEMPERATURE (°C) 2.042 –50 –30 –10 10 30 50 70 90 110 130 TEMPERATURE (°C) 2654 G12 2654 G11 Settling to ±1LSB Rising Settling to ±1LSB Falling CS/LD 5V/DIV 6.8μs VOUT 250μV/DIV 7.9μs VOUT 250μV/DIV CS/LD 5V/DIV 2μs/DIV 1/4 SCALE TO 3/4 SCALE STEP VCC = 5V, VFS = 4.096V RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS 10 2654 G13 2μs/DIV 3/4 SCALE TO 1/4 SCALE STEP VCC = 5V, VFS = 4.096V RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS 2654 G14 2654f LTC2654 TYPICAL PERFORMANCE CHARACTERISTICS LTC2654-12 Integral Nonlinearity (INL) 1.0 Differential Nonlinearity (DNL) 1.0 VCC = 5V VREF = 2.048V VCC = 3V VREF = 1.25V CS/LD 5V/DIV 0.5 DNL (LSB) INL (LSB) 0.5 Settling to ±1LSB (12-Bit) Rising 0 0 4.6μs VOUT 1mV/DIV –0.5 –1.0 –0.5 0 1024 2048 CODE 3072 –1.0 4095 0 1024 2048 CODE 2654 G15 3072 2654 G17 4095 2μs/DIV 1/4 SCALE TO 3/4 SCALE STEP VCC = 5V, VFS = 4.095V, RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS 2654 G16 LTC2654-16 Load Regulation 10 8 Headroom at Rails vs Output Current Current Limiting 0.20 VCC = 5V (LTC2654-H) VCC = 3V (LTC2654-L) 0.15 5.0 VCC = 5V (LTC2654-H) VCC = 3V (LTC2654-L) 6 4.0 0.10 0 –2 3.5 0.05 VOUT (V) 2 $VOUT (V) $VOUT (V) 4 0 –0.05 –4 3V (LTC2654-L) SOURCING 3.0 2.5 2.0 1.5 –0.10 –6 INTERNAL REF –8 CODE = MID-SCALE –10 –50 –40 –30 –20 –10 0 10 20 30 40 50 IOUT (mA) 2654 G18 INTERNAL REF CODE = MID-SCALE –0.20 –50 –40 –30 –20 –10 0 10 20 30 40 50 IOUT (mA) 0.5 0 2.5 –3 –50 –30 –10 10 30 50 70 90 110 130 TEMPERATURE (°C) 2654 G21 2 3 4 5 6 IOUT (mA) 7 8 9 10 Gain Error vs Temperature 48 32 2.0 1.5 1.0 16 0 –16 –32 0.5 –2 1 64 GAIN ERROR (LSB) ZERO-SCALE ERROR (mV) 2 –1 0 2654 G20 Zero-Scale Error vs Temperature 3.0 0 3V (LTC2654-H) SINKING 2654 G19 3 1 5V (LTC2654-H) SINKING 1.0 –0.15 Offset Error vs Temperature OFFSET ERROR (mV) 5V (LTC2654-H) SOURCING 4.5 –48 0 –50 –30 –10 10 30 50 70 90 110 130 TEMPERATURE (°C) 2654 G22 –64 –50 –30 –10 10 30 50 70 90 110 130 TEMPERATURE (°C) 2654 G23 2654f 11 LTC2654 TYPICAL PERFORMANCE CHARACTERISTICS LTC2654-16 Offset Error vs Reference Input 2.0 VCC = 5.5V OFFSET ERROR OF 4 CHANNELS 1.5 48 VCC = 5.5V OFFSET ERROR OF 4 CHANNELS 400 350 32 0.5 0 –0.5 300 16 0 –16 250 200 150 –1.0 –32 100 –1.5 –48 50 –2.0 0.5 1.5 2 1 REFERENCE VOLTAGE (V) 2.5 –64 0.5 1.5 2 1 REFERENCE VOLTAGE (V) 2654 G24 2.5 0 2.5 3.5 4 VCC (V) 4.5 5 Hardware CLR VCC = 3V, VREF = 1.25V CODE = FULL-SCALE SWEEP SCK, SDI, CS/LD BETWEEN 0V AND VCC 5.5 2654 G26 Hardware CLR to Mid-Scale 3.1 3 2654 G25 Supply Current vs Logic Voltage 3.5 ICC (nA) ICC Shutdown vs VCC 450 ICC (nA) 1.0 GAIN ERROR (LSB) OFFSET ERROR (mV) Gain Error vs Reference Input 64 VCC = 3V, VREF = 1.25V CODE = FULL-SCALE VOUT 1V/DIV VOUT 1V/DIV 2.7 2.3 VCC = 5V (LTC2654-H) CLR 3V/DIV CLR 3V/DIV 1.9 VCC = 3V (LTC2654-L) 1.5 0 1 3 2 LOGIC VOLTAGE (V) 4 5 1μs/DIV 2654 G28 2654 G29 1μs/DIV 2654 G27 Multiplying Bandwidth Large-Signal Response 8 LTC2654-H16 VCC = 5V, VFS = 4.095V ZERO-SCALE TO FULL-SCALE 6 4 BANDWIDTH (dB) Mid-Scale Glitch Impulse CS/LD 5mV/DIV 2 0 –2 –4 MS-1 –6 VCC = 5V VREF(DC) = 2V –10 VREF(AC) = 0.2VP-P CODE = FULL-SCALE –12 10k 1k 100k FREQUENCY (Hz) LTC2654-H16 VCC = 5V, 5nV-s TYP VOUT 5mV/DIV VOUT 5mV/DIV VOUT 1V/DIV –8 1M 2.5μs/DIV 2654 G31 MS LTC2654-L16 VCC = 3V, 3nV-s TYP 2μs/DIV 2654 G32 2654 G30 2654f 12 LTC2654 TYPICAL PERFORMANCE CHARACTERISTICS LTC2654-16 DAC to DAC Crosstalk (Dynamic) ONE DAC SWITCH 0-FS 2V/DIV LTC2654-L16, VCC = 5V, 4nV TYP CREFCOMP = 1000pF CREFOUT = NO LOAD VOUT 2mV/DIV VCC 2V/DIV LTC2654-L16, VCC = 5V CREFCOMP = CREFOUT = 0.22μF VOUT 2mV/DIV 2μs/DIV Power-On Reset Glitch VOUT 10mV/DIV ZERO-SCALE 2654 G33 2654 G34 200μs/DIV Power-On Reset to Mid-Scale Noise Voltage vs Frequency 400 NOISE VOLTAGE (nV/√Hz) LTC2654-L VCC 2V/DIV VCC = 5V CODE = MID-SCALE INTERNAL REF 300 CREFCOMP = CREFOUT = 0.1μF 200 LTC2654-H 100 LTC2654-L VOUT 1V/DIV 1ms/DIV 2654 G35 0 10 100 1k 10k FREQUENCY (Hz) 100k 1M 2654 G36 DAC Output 0.1Hz to 10Hz Voltage Noise Reference 0.1Hz to 10Hz Voltage Noise VREFOUT = 2.048V CREFCOMP = CREFOUT = 0.1μF VCC = 5V, LTC2654-H CODE = MID-SCALE INTERNAL REF CREFCOMP = CREFOUT = 0.1μF 2μV/DIV 5μV/DIV 1s/DIV 2654 G37 1s/DIV 2654 G38 2654f 13 LTC2654 PIN FUNCTIONS (QFN/SSOP) VOUTA to VOUTD (Pins 1, 3, 13, 14/Pins 2,4,13,14): DAC Analog Voltage Outputs. The output range is 0V to 2 times the voltage at the REFIN/OUT pin. REFCOMP (Pin 2/Pin 3): Internal Reference Compensation pin. For low noise and reference stability, tie a 0.1μF capacitor to GND. Connecting this pin to GND allows the use of external reference at start-up. REFIN/OUT (Pin 4/Pin 5): Reference Input/Output. This pin acts as the internal reference output in internal reference mode and acts as the reference input pin in external reference mode. When acting as an output the nominal voltage at this pin is 1.25V for -L options and 2.048V for -H options. For low noise and reference stability tie a capacitor to GND. Capacitor value must be ≤CREFCOMP. In external reference mode, the allowable reference input voltage range is 0.5V to VCC /2. LDAC (Pin 5/Pin 6): Asynchronous DAC Update Pin. If CS/LD is high, a falling edge on LDAC immediately updates the DAC register with the contents of the input register (similar to a software update). If CS/LD is low when LDAC goes low, the DAC register is updated after CS/LD returns high. A low on the LDAC pin powers up the DAC outputs. All the software power-down commands are ignored if LDAC is low when CS/LD goes high. CS/LD (Pin 6/Pin 7): Serial Interface Chip Select/Load Input. When CS/LD is low, SCK is enabled for shifting data on SDI into the register. When CS/LD is taken high, SCK is disabled and the specified command (see Table 1) is executed. SCK (Pin 7/Pin 8): Serial Interface Clock Input. CMOS and TTL compatible. SDI (Pin 9/Pin 9): Serial Interface Data Input. Data is applied to SDI for transfer to the device at the rising edge of SCK (Pin 10). The LTC2654 accepts input word lengths of either 24 or 32 bits. See Figures 2a and 2b. SDO (Pin 10/Pin 10): Serial Interface Data Output. This pin is used for daisy-chain operation. The serial output of the shift register appears at the SDO pin. The data transferred to the device via the SDI pin is delayed 32 SCK rising edges before being output at the next falling edge. This pin is continuously driven and does not go high impedance when CS/LD is taken active high. CLR (Pin 11/Pin 11): Asynchronous Clear Input. A logic low at this level-triggered input clears all registers and causes the DAC voltage outputs to drop to 0V if PORSEL pin is tied to GND. If the PORSEL pin is tied to VCC, a logic low at CLR sets all registers to mid-scale code and causes the DAC voltage outputs to go to mid-scale. PORSEL (Pin 12/Pin 12): Power-On-Reset Select Pin. If tied to GND, the DACs reset to zero-scale. If tied to VCC, the DACs reset to mid-scale. VCC (Pin 18/Pin 15): Supply Voltage Input. For -L options, 2.7V ≤ VCC ≤ 5.5V, and for -H options, 4.5V ≤ VCC ≤ 5.5V. Should be bypassed by a 0.1μF low ESR ceramic capacitor to GND. GND (Pin 19, Exposed Pad Pin 21/Pin 16): Ground. Exposed pad must be soldered to PCB Ground. REFLO (Pin 20/Pin 1): Reference Low Pin. The voltage at this pin sets the zero-scale voltage of all DACs. This pin should be tied to GND. DNC (Pins 8, 15, 16, 17/NA): Do not connect these pins. 2654f 14 LTC2654 BLOCK DIAGRAM REFCOMP REFIN/OUT INTERNAL REFERENCE GND VCC REGISTER REGISTER REGISTER DAC D DAC B REGISTER REGISTER REGISTER VOUTB DAC A REGISTER VOUTA REGISTER REFLO DAC C CS/LD CONTROL LOGIC POWER-ON RESET DECODE VOUTD VOUTC PORSEL SDO SCK SDI 32-BIT SHIFT REGISTER LDAC CLR 2636 BD TIMING DIAGRAMS t1 t2 SCK t3 1 t6 t4 2 3 23 24 t10 SDI t5 t7 CS/LD t8 SDO t13 t12 LDAC 2654 F01a Figure 1a CS/LD t13 LDAC 2654 F01b Figure 1b 2654f 15 LTC2654 OPERATION The LTC2654 is a family of quad voltage output DACs in 20-lead 4mm × 4mm QFN and in 16-lead narrow SSOP packages. Each DAC can operate rail-to-rail in external reference mode, or with its full-scale voltage set by an integrated reference. Four combinations of accuracy (16bit and 12-bit), and full-scale voltage (2.5V or 4.096V) are available. The LTC2654 is controlled using a 4-wire SPI/MICROWIRE compatible interface. Power-On Reset The LTC2654-L/LTC2654-H clear the output to zero-scale if PORSEL pin is tied to GND, when power is first applied, making system initialization consistent and repeatable. For some applications, downstream circuits are active during DAC power-up, and may be sensitive to nonzero outputs from the DAC during this time. The LTC2654 contains circuitry to reduce the power-on glitch. The analog outputs typically rise less than 10mV above zero-scale during power-on if the power supply is ramped to 5V in 1ms or more. In general, the glitch amplitude decreases as the power supply ramp time is increased. See PowerOn-Reset Glitch in the Typical Performance Characteristics section. Alternatively, if PORSEL pin is tied to VCC (Pin 18/Pin 15), The LTC2654-L/LTC2654-H set the output to mid-scale when power is first applied. Power Supply Sequencing and Start-Up For LTC2654 family of parts, the internal reference is powered-up at start-up by default. If an external reference is to be used, the REFCOMP pin (Pin 2/Pin 3) must be hardwired to GND. Having REFCOMP hardwired to GND at power up, will cause the REFIN/OUT pin to become high-impedance and will allow for the use of an external reference at start-up. However in this configuration, internal reference will still be ON, even though it is disconnected from the REFIN/OUT pin and it will draw supply current. In order to use external reference after power-up, the command Select External Reference (0111b) should be used to turn the internal reference off (See Table 1). The voltage at REFIN/OUT (Pin 4/Pin 5) should be kept within the range –0.3V ≤ REFIN/OUT ≤ VCC + 0.3V (see Absolute Maximum Ratings). Particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at VCC (Pin 18/ Pin 15) is in transition. Transfer Function The digital-to-analog transfer function is ⎛ k ⎞ VOUT(IDEAL) = ⎜ N ⎟ • 2 • ⎡⎣ VREF − VREFLO ⎤⎦ + VREFLO ⎝2 ⎠ where k is the decimal equivalent of the binary DAC input code, N is the resolution of the DAC, and VREF is the voltage at the REFIN/OUT Pin. The resulting DAC output span is 0V to 2•VREF, as it is necessary to tie REFLO to GND. VREF is nominally 1.25V for LTC2654-L and 2.048V for LTC2654-H, in Internal Reference Mode. Table 1. Command and Address Codes COMMAND* C3 C2 C1 C0 0 0 0 0 Write to Input Register n 0 0 0 1 Update (Power-Up) DAC Register n 0 0 1 0 Write to Input Register n, Update (Power-Up) All 0 0 1 1 Write to and Update (Power-Up) n 0 1 0 0 Power-Down n 0 1 0 1 Power-Down Chip (All DAC’s and Reference) 0 1 1 0 Select Internal Reference (Power-Up Reference) 0 1 1 1 Select External Reference (Power-Down Reference) 1 1 1 1 No Operation ADDRESS (n)* A3 A2 A1 A0 0 0 0 0 DAC A 0 0 0 1 DAC B 0 0 1 0 DAC C 0 0 1 1 DAC D 1 1 1 1 All DACs *Command and address codes not shown are reserved and should not be used. 2654f 16 LTC2654 OPERATION Serial Interface Daisy-Chain Operation The CS/LD input is level triggered. When this input is taken low, it acts as a chip-select signal, powering on the SDI and SCK buffers and enabling the input shift register. Data (SDI input) is transferred at the next 24 rising SCK edges. The 4-bit command, C3-C0, is loaded first; followed by the 4-bit DAC address, A3-A0; and finally the 16-bit data word. For the LTC2654-16 the data word comprises the 16-bit input code, ordered MSB-to-LSB. For the LTC265412 the data word comprises the 12-bit input code, ordered MSB-to-LSB followed by four don’t-care bits. Data can only be transferred to the LTC2654 when the CS/LD signal is low. The rising edge of CS/LD ends the data transfer and causes the device to carry out the action specified in the 24-bit input word. The complete sequence is shown in Figure 2a. The serial output of the shift register appears at the SDO pin. Data transferred to the device from the SDI input is delayed 32 SCK rising edges before being output at the next SCK falling edge. The SDO pin is continuously driven and does not go high impedance when CS/LD is taken active high. The command (C3-C0) and address (A3-A0) assignments are shown in Table 1. The first four commands in the table consist of write and update operations. A write operation loads a 16-bit data word from the 32-bit shift register into the input register of the selected DAC, n. An update operation copies the data word from the input register to the DAC register. Once copied into the DAC register, the data word becomes the active 16- or 12-bit input code, and is converted to an analog voltage at the DAC output. The update operation also powers up the selected DAC if it had been in power-down mode. The data path and registers are shown in the block diagram. While the minimum input word is 24 bits, it may optionally be extended to 32 bits. To use the 32-bit word width, 8 don’t-care bits are transferred to the device first, followed by the 24-bit word as just described. Figure 2b shows the 32-bit sequence. The 32-bit word is required for daisy chain operation, and is also available to accommodate microprocessors that have a minimum word width of 16 bits (2 bytes). The 16-bit data word is ignored for all commands that do not include a write operation. The SDO output can be used to facilitate control of multiple serial devices from a single 3-wire serial port (i.e., SCK, SDI and CS/LD). Such a daisy-chain series is configured by connecting SDO of each up-stream device to SDI of the next device in the chain. The shift registers of the devices are thus connected in series, effectively forming a single input shift register which extends through the entire chain. Because of this, the devices can be addressed and controlled individually by simply concatenating their input words; the first instruction addresses the last device in the chain and so forth. The SCK and CS/LD signals are common to all devices in the series. In use, CS/LD is first taken low. Then the concatenated input data is transferred to the chain, using SDI of the first device as the data input. When the data transfer is complete, CS/LD is taken high, completing the instruction sequence for all devices simultaneously. A single device can be controlled by using the no-operation command (1111b) for the other devices in the chain. Power-Down Mode For power-constrained applications, power-down mode can be used to reduce the supply current whenever less than four DAC outputs are needed. When in power-down, the buffer amplifiers, bias circuits and integrated reference circuits are disabled, and draw essentially zero current. The DAC outputs are put into a high-impedance state, and the output pins are passively pulled to ground through individual 80k resistors. Input- and DAC-register contents are not disturbed during power-down. 2654f 17 18 X X SDI SDO SCK CS/LD 1 X X 2 X X 3 4 X 5 X X DON’T CARE X C3 SDI C2 2 C1 3 X X 6 X X 7 X X 8 COMMAND WORD 1 SCK CS/LD C3 7 A1 ADDRESS A2 6 A0 8 D15 9 D14 10 D12 12 D11 13 D10 14 24-BIT INPUT WORD D13 11 D9 15 D7 17 DATA WORD D8 16 D6 18 D5 19 C2 10 C1 11 C1 C0 A1 15 A2 A1 ADDRESS WORD A2 14 A0 A0 16 17 D15 D15 PREVIOUS 32-BIT INPUT WORD A3 A3 13 D14 D14 18 20 D12 D12 t8 t4 D7 25 18 D14 D8 D7 DATA WORD D8 24 PREVIOUS D15 PREVIOUS D14 17 t3 D9 D9 23 SDO t2 D10 D10 22 D15 t1 D11 D11 21 26 D6 D6 D3 21 SDI SCK D13 D13 19 20 D4 Figure 2b. LTC2654-16 32-Bit Load Sequence. LTC2654-12 SDI/SDO Data Word: 12-Bit Input Code + 4 Don’t Care Bits C2 C0 12 Figure 2a. LTC2654-16 24-Bit Load Sequence (Minimum Input Word) LTC2654-12 SDI Data Word: 12-Bit Input Code + 4 Don’t Care Bits A3 5 COMMAND WORD 9 C3 C0 4 27 D5 D5 D2 22 28 D4 D4 D1 23 29 D3 D3 D0 24 D2 D2 30 2654 F02a D1 D1 31 2654 F02b CURRENT 32-BIT INPUT WORD D0 D0 32 LTC2654 OPERATION 2654f LTC2654 OPERATION Any channel or combination of DAC channels can be put into power-down mode by using command 0100b in combination with the appropriate DAC address, (n). The integrated reference is automatically powered down when external reference is selected using command 0111b. In addition, all the DAC channels and the integrated reference together can be put into power-down mode using Power-Down Chip command 0101b. For all power-down commands the 16-bit data word is ignored, but still needs to be clocked in. Normal operation resumes by executing any command which includes a DAC update, in software as shown in Table 1 or by taking the asynchronous LDAC pin low. The selected DAC is powered up as its voltage output is updated. When a DAC which is in a powered-down state is powered up and updated, normal settling is delayed. If less than four DACs are in a powered-down state prior to the update command, the power-up delay time is 12μs. If on the other hand, all four DACs and the integrated reference are powered down, then the main bias generation circuit block has been automatically shut down in addition to the individual DAC amplifiers and integrated reference. In this case, the power up delay time is 14μs. The power-up of integrated reference depends on the command that powered it down. If the reference is powered down using the Select External Reference Command (0111b) then it can only be powered back-up using Select Internal Reference Command (0110b). However if the reference was powered down using Power-Down Chip Command (0101b) then in addition to Select Internal Reference Command (0110b), any command that powers up the DACs will also power-up the integrated reference. Asynchronous DAC Update Using LDAC In addition to the update commands shown in Table 1, the LDAC pin asynchronously updates all the DAC registers with the contents of the input registers. If CS/LD is high, a low on the LDAC pin causes all the DAC registers to be updated with the contents of the input registers. If CS/LD is low, a low going pulse on the LDAC pin before the rising edge of CS/LD powers up all the DAC outputs but does not cause the output to be updated. If LDAC remains low after the rising edge of CS/LD, then LDAC is recognized, the command specified in the 24-bit word just transferred is executed and the DAC outputs are updated. The DAC outputs are powered up when LDAC is taken low, independent of the state of CS/LD. The integrated reference is also powered up if it was powered down using Power-Down Chip (0101b) command. The integrated reference will not power up when LDAC is taken low, if it was powered down using Select External Reference (0111b) Command. If LDAC is low at the time CS/LD goes high, it inhibits any software power-down command (Power-Down n, PowerDown Chip, Select External Reference) that was specified in the input word. Reference Modes For applications where an accurate external reference is not available, the LTC2654 has a user-selectable, integrated reference. The LTC2654-L has a 1.25V reference that provides a full-scale output of 2.5V. The LTC2654-H has a 2.048V reference that provides a full-scale output of 4.096V. Both references exhibit a typical temperature drift of 2ppm/°C. Internal reference mode can be selected by using command 0110b, and is the power-on default. A buffer is needed if the internal reference is required to drive external circuitry. For reference stability and low noise, connect a 0.1μF capacitor between REFCOMP and GND. In this configuration, the internal reference can drive up to 0.1μF capacitive load without any stability problems. In order to ensure stable operation, the capacitive load on REFIN/OUT pin should not exceed the capacitive load on the REFCOMP pin. The DAC can also operate in external reference mode using command 0111b. In this mode, REFIN/OUT pin acts as an input that sets the DAC’s reference voltage. The input is high impedance and does not load the external reference source. The acceptable voltage range at this pin is 0.5V ≤ REFIN/OUT ≤ VCC/2. The resulting full-scale output voltage is 2•VREFIN/OUT. For using External Reference at start-up, see the Power Supply Sequencing and Start-Up Section. 2654f 19 LTC2654 OPERATION Integrated Reference Buffers Board Layout Each of the four DACs in the LTC2654 has its own integrated high performance reference buffer. The buffers have very high input impedance and do not load the reference voltage source. These buffers shield the reference voltage from glitches caused by DAC switching and thus minimize DAC-to-DAC Dynamic Crosstalk. Typically DAC-to-DAC crosstalk is less than 3nV•s. By tying 0.22μF capacitors between REFCOMP and GND, and also between REFIN/ OUT and GND, this number can be reduced to less than 1nV•s. See the curve DAC-to-DAC Dynamic Crosstalk in the Typical Performance Characteristics section. The excellent load regulation and DC crosstalk performance of these devices is achieved in part by keeping signal and power grounds separate. Voltage Outputs Each of the LTC2654’s four rail-to-rail output amplifiers contained in these parts has guaranteed load regulation when sourcing or sinking up to 15mA at 5V (7.5mA at 3V). Load regulation is a measure of the amplifier’s ability to maintain the rated voltage accuracy over a wide range of load conditions. The measured change in output voltage per milliampere of forced load current change is expressed in LSB/mA. DC output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from LSB/mA to Ohms. The amplifiers’ DC output impedance is 0.04Ω when driving a load well away from the rails. When drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 30Ω typical channel resistance of the output devices; e.g., when sinking 1mA, the minimum output voltage = 30Ω • 1mA = 30mV. See the graph Headroom at Rails vs Output Current in the Typical Performance Characteristics section. The amplifiers are stable driving capacitive loads of up to 1000pF. The PC board should have separate areas for the analog and digital sections of the circuit. This keeps digital signals away from sensitive analog signals and facilitates the use of separate digital and analog ground planes which have minimal capacitive and resistive interaction with each other. Digital and analog ground planes should be joined at only one point, establishing a system star ground as close to the device’s ground pin as possible. Ideally, the analog ground plane should be located on the component side of the board, and should be allowed to run under the part to shield it from noise. Analog ground should be a continuous and uninterrupted plane, except for necessary lead pads and vias, with signal traces on another layer. The GND pin functions as a return path for power supply currents in the device and should be connected to analog ground. The REFLO pin should be connected to system star ground. Resistance from the REFLO pin to system star ground should be as low as possible. Rail-to-Rail Output Considerations In any rail-to-rail voltage output device, the output is limited to voltages within the supply range. Since the analog outputs of the device cannot go below ground, they may limit for the lowest codes as shown in Figure 3b. Similarly, limiting can occur in external reference mode near full-scale when the REFIN/OUT pin is at VCC/2. If VREFIN/OUT = VCC/2 and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC as shown in Figure 3c. No full-scale limiting can occur if VREFIN/OUT ≤ (VCC – FSE)/2. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur. 2654f 20 NEGATIVE OFFSET 0V OUTPUT VOLTAGE 0 32,768 INPUT CODE (a) 4,095 INPUT CODE (c) Figure 3. Effects of Rail-to-Rail Operation on a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Codes Near Full-Scale (b) INPUT CODE 0V OUTPUT VOLTAGE VREF = VCC VREF = VCC 2654 F04 OUTPUT VOLTAGE POSITIVE FSE LTC2654 OPERATION 2654f 21 LTC2654 PACKAGE DESCRIPTION GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .189 – .196* (4.801 – 4.978) .045 ±.005 16 15 14 13 12 11 10 9 .254 MIN .009 (0.229) REF .150 – .165 .229 – .244 (5.817 – 6.198) .0165 ± .0015 .150 – .157** (3.810 – 3.988) .0250 BSC RECOMMENDED SOLDER PAD LAYOUT 1 .015 ± .004 × 45° (0.38 ± 0.10) .007 – .0098 (0.178 – 0.249) .0532 – .0688 (1.35 – 1.75) 2 3 4 5 6 7 8 .004 – .0098 (0.102 – 0.249) 0° – 8° TYP .016 – .050 (0.406 – 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) .008 – .012 (0.203 – 0.305) TYP .0250 (0.635) BSC GN16 (SSOP) 0204 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 2654f 22 LTC2654 PACKAGE DESCRIPTION UF Package 20-Lead Plastic QFN (4mm × 4mm) (Reference LTC DWG # 05-08-1710) 0.70 ±0.05 4.50 ± 0.05 3.10 ± 0.05 2.00 REF 2.45 ± 0.05 2.45 ± 0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 ± 0.10 0.75 ± 0.05 R = 0.05 TYP R = 0.115 TYP 19 20 0.40 ± 0.10 PIN 1 TOP MARK (NOTE 6) 4.00 ± 0.10 PIN 1 NOTCH R = 0.20 TYP OR 0.35 × 45° CHAMFER BOTTOM VIEW—EXPOSED PAD 1 2.00 REF 2.45 ± 0.10 2 2.45 ± 0.10 (UF20) QFN 01-07 REV A 0.200 REF 0.00 – 0.05 0.25 ± 0.05 0.50 BSC NOTE: 1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-1)—TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 2654f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 23 LTC2654 TYPICAL APPLICATION True Rail-to-Rail Output DAC 5V C2 0.1μF C1 0.1μF 18 VCC 6 7 PIN NUMBERS SHOWN ARE FOR THE QFN PACKAGE. 9 10 PINS 5, 6, 7, 9, 11 TIE TO DIGITAL CONTROL LINES C3 0.1μF 2 4 5 12 11 REFIN/OUT LDAC PORSEL CLR REFCOMP CS/LD VOUTA SCK VOUTB LTC2654 SDI VOUTC VOUTD SDO GND 19 GND REFLO DNC 20 8 21 DNC 17 DNC DNC 16 15 1 3 13 14 2654 TA02 D1 BAS70 R2 10k –5V RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1660/LTC1665 Octal 10-/8-Bit VOUT DACs in 16-Pin Narrow SSOP VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output LTC1664 Quad 10-Bit VOUT DAC in 16-Pin Narrow SSOP VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output LTC1821 Single 16-Bit VOUT DAC with ±1LSB INL, DNL Parallel Interface, Precision 16-Bit Settling in 2μs for 10V Step LTC2656 Octal 16-/12-Bit VOUT DACs 325μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface, Internal Reference LTC2601/LTC2611/ LTC2621 Single 16-/14-/12-Bit VOUT DACs in 10-Lead DFN 300μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface LTC2602/LTC2612/ LTC2622 Dual 16-/14-/12-Bit VOUT DACs in 8-Lead MSOP 300μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface LTC2604/LTC2614/ LTC2624 Quad 16-/14-/12-Bit VOUT DACs in 16-Lead SSOP 250μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface LTC2605/LTC2615/ LTC2625 Octal 16-/14-/12-Bit VOUT DACs with I2C Interface 250μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output LTC2606/LTC2616/ LTC2626 Single 16-/14-/12-Bit VOUT DACs with I2C Interface 270μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output LTC2609/LTC2619/ LTC2629 Quad 16-/14-/12-Bit VOUT DACs with I2C Interface 250μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output with Separate VREF Pins for Each DAC LTC2634 Quad 12-/10-/8-Bit VOUT DACs with 10ppm/°C (Typical) Reference 125μA per DAC, 2.7V to 5.5V Supply Range, Internal 1.25V or 2.048V Reference, Rail-to-Rail Output, SPI Interface LTC2636 Octal 12-/10-/8-Bit VOUT DACs with 10ppm/°C Reference 125μA per DAC, 2.7V to 5.5V Supply Range, Internal 1.25V or 2.048V Reference, Rail-to-Rail Output, SPI Interface LTC2641/LTC2642 Single 16-/14-/12-Bit VOUT DACs with ±1LSB INL, DNL ±1LSB (Max) INL, DNL, 3mm × 3mm DFN and MSOP Packages, 120μA Supply Current, SPI Interface LTC2704 Quad 16-/14-/12-Bit VOUT DACs with ±2LSB INL, ±1LSB DNL Software Programmable Output Ranges Up to ±10V, SPI Interface LTC2754 Quad 16-/14-/12-Bit SPI IOUT DACs with ±1LSB INL, ±1LSB DNL Software Programmable Output Ranges Up to ±10V SPI Interface LTC2755 Quad 16-/14-/12-Bit IOUT DACs with ±1LSB INL, ±1LSB DNL Software Programmable Output Ranges Up to ±10V, Parallel Interface 2654f 24 Linear Technology Corporation LT 0310 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2010