SEMICONDUCTOR TECHNICAL DATA The MC10H016 is a high–speed synchronous, presettable, cascadable 4–bit binary counter. It is useful for a large number of conversion, counting and digital integration applications. • Counting Frequency, 200 MHz Minimum • Improved Noise Margin 150 mV (Over Operating Voltage and Temperature Range) • Voltage Compensated • MECL 10K–Compatible • Positive Edge Triggered L SUFFIX CERAMIC PACKAGE CASE 620–10 P SUFFIX PLASTIC PACKAGE CASE 648–08 MAXIMUM RATINGS Symbol Rating Unit Power Supply (VCC = 0) Characteristic VEE –8.0 to 0 Vdc Input Voltage (VCC = 0) VI 0 to VEE Vdc Iout 50 100 mA TA 0 to +75 °C Tstg –55 to +150 –55 to +165 °C Output Current — Continuous — Surge Operating Temperature Range Storage Temperature Range — Plastic — Ceramic FN SUFFIX PLCC CASE 775–02 DIP PIN ASSIGNMENT ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note) 0° Characteristic Power Supply Current 25° 75° Symbol Min Max Min Max Min Max Unit VCC1 1 16 VCC2 IE — 126 — 115 — 126 mA Q1 2 15 Q2 Q0 3 14 Q3 TC 4 13 CP Input Current High All Except MR Pin 12 MR IinH Input Current Low µA — — 450 1190 — — 265 700 — — 265 700 IinL 0.5 — 0.5 — 0.3 — µA High Output Voltage VOH –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 Vdc PE 5 12 MR Low Output Voltage VOL –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 Vdc CE 6 11 P3 High Input Voltage VIH –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 Vdc Low Input Voltage VIL –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 Vdc PO 7 10 P2 VEE 8 9 P1 AC PARAMETERS Propagation Delay Clock to Q Clock to TC MR to Q tpd Set–up Time Pn to Clock CE or PE to Clock tset Hold Time Clock to Pn Clock to CE or PE thold Counting Frequency ns 1.0 0.7 0.7 2.4 2.4 2.4 1.0 0.7 0.7 2.5 2.5 2.5 1.0 0.7 0.7 2.7 2.6 2.6 2.0 2.5 — — 2.0 2.5 — — 2.0 2.5 — — 1.0 0.5 — — 1.0 0.5 — — 1.0 0.5 — — Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 6–11 of the Motorola MECL Data Book (DL122/D). ns TRUTH TABLE ns fcount 200 — 200 — 200 — MHz Rise Time tr 0.5 2.0 0.5 2.1 0.5 2.2 ns Fall Time tf 0.5 2.0 0.5 2.1 0.5 2.2 ns NOTE: Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Ifpm is maintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts. CE PE MR CP Function L H L H X L L H H X L L L L L Z Z Z Z ZZ X X H X Load Parallel (Pn to Qn) Load Parallel (Pn to Qn) Count Hold Masters Respond; Slaves Hold Reset (Qn = LOW, TC = HIGH) Z = Clock Pulse (Low to High); ZZ = Clock Pulse (High to Low) Features include assertion inputs and outputs on each of the four master/slave counting flip–flops. Terminal count is generated internally in a manner that allows synchronous loading at nearly the speed of the basic counter. 9/96 Motorola, Inc. 1996 2–1 REV 6 MOTOROLA CP CLOCK CE MR P0 PE 2–2 C MR CE P0–P3 LSB Q0–Q3 Tc PE 1/2 10H109 MASTER SLAVE Q P1 MASTER Q Q SLAVE Q Q1 P2 MASTER Q Q SLAVE Q Q2 P3 C MR CE Tc PE 1/2 10H109 C MR CE P0–P3 Q0–Q3 Tc PE 1/2 10H109 C MR CE Max freq. is only OR gate delay below max when counting alone. P0–P3 Q0–Q3 ÷N Counter 1 to 16 5 MC10H016 Cascaded for 5 Stage Presettable Counter P0–P3 Q0–Q3 Tc PE 1/2 10H109 Note that this diagram is provided for understanding of logic operation only. It should not be used for evaluation of propagation delays as many gate functions are achieved internally without incurring a full gate delay. Q Q Q0 4–Bit Binary Counter Logic Diagram C MR CE P0–P3 MSB Q0–Q3 Tc PE FO Q Q3 TC MC10H016 MECL Data DL122 — Rev 6 MC10H016 OUTLINE DIMENSIONS FN SUFFIX PLASTIC PLCC PACKAGE CASE 775–02 ISSUE C 0.007 (0.180) M T L–M B Y BRK –N– U N S 0.007 (0.180) M T L–M S S N S D –L– –M– Z W 20 D 1 V 0.010 (0.250) G1 X S T L–M S N S VIEW D–D A 0.007 (0.180) M T L–M S N S R 0.007 (0.180) M T L–M S N S Z C H –T– SEATING PLANE F VIEW S G1 0.010 (0.250) S T L–M S 0.007 (0.180) M T L–M S N S VIEW S S N S NOTES: 1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM –T–, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). MECL Data DL122 — Rev 6 N K 0.004 (0.100) J S K1 E G 0.007 (0.180) M T L–M 2–3 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.385 0.395 0.385 0.395 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 ––– 0.025 ––– 0.350 0.356 0.350 0.356 0.042 0.048 0.042 0.048 0.042 0.056 ––– 0.020 2_ 10 _ 0.310 0.330 0.040 ––– MILLIMETERS MIN MAX 9.78 10.03 9.78 10.03 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 ––– 0.64 ––– 8.89 9.04 8.89 9.04 1.07 1.21 1.07 1.21 1.07 1.42 ––– 0.50 2_ 10 _ 7.88 8.38 1.02 ––– MOTOROLA MC10H016 OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE V –A– 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. –B– C L DIM A B C D E F G H K L M N –T– K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A T B M –A– 9 1 8 B F C L S –T– SEATING PLANE K H G D M J 16 PL 0.25 (0.010) M MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 ––– 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 S P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R 16 S INCHES MIN MAX 0.750 0.785 0.240 0.295 ––– 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 T A M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 MFAX: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 ◊ MOTOROLA 2–4 *MC10H016/D* MC10H016/D MECL Data DL122 — Rev 6