AD SSM2315

Filterless, High Efficiency,
Mono 3 W Class-D Audio Amplifier
SSM2315
The SSM2315 features a high efficiency, low noise modulation
scheme that requires no external LC output filters. The modulation
continues to provide high efficiency even at low output power.
It operates with 93% efficiency at 1.4 W into 8 Ω or 85% efficiency
at 3 W into 3 Ω from a 5.0 V supply and has an SNR of >103 dB.
Spread-spectrum pulse density modulation is used to provide
lower EMI-radiated emissions compared with other Class-D
architectures.
FEATURES
Filterless Class-D amplifier with Σ-Δ modulation
No sync necessary when using multiple Class-D amplifiers
from Analog Devices, Inc.
3 W into 3 Ω load and 1.4 W into 8 Ω load at 5.0 V supply
with <1% total harmonic distortion (THD + N)
93% efficiency at 5.0 V, 1.4 W into 8 Ω speaker
>103 dB signal-to-noise ratio (SNR)
Single-supply operation from 2.5 V to 5.5 V
20 nA ultralow shutdown current
Short-circuit and thermal protection
Available in 9-ball, 1.5 mm × 1.5 mm WLCSP
Pop-and-click suppression
Built-in resistors reduce board component count
Default fixed 6 dB or user adjustable gain setting
The SSM2315 has a micropower shutdown mode with a typical
shutdown current of 20 nA. Shutdown is enabled by applying
a logic low to the SD pin.
APPLICATIONS
The device also includes pop-and-click suppression circuitry.
This suppression circuitry minimizes voltage glitches at the
output during turn-on and turn-off, reducing audible noise
on activation and deactivation.
Mobile phones
MP3 players
Portable gaming
Portable electronics
Educational toys
The fully differential input of the SSM2315 provides excellent
rejection of common-mode noise on the input. Input coupling
capacitors can be omitted if the dc input common-mode voltage
is approximately VDD/2.
GENERAL DESCRIPTION
The default gain of the SSM2315 is 6 dB, but users can reduce the
gain by using a pair of external resistors (see the Gain section).
The SSM2315 is a fully integrated, high efficiency, Class-D audio
amplifier. It is designed to maximize performance for mobile
phone applications. The application circuit requires a minimum
of external components and operates from a single 2.5 V to 5.5 V
supply. It is capable of delivering 3 W of continuous output power
with <1% THD + N driving a 3 Ω load from a 5.0 V supply.
The SSM2315 is specified over the industrial temperature range of
−40°C to +85°C. It has built-in thermal shutdown and output
short-circuit protection. It is available in a 9-ball, 1.5 mm × 1.5 mm
wafer level chip scale package (WLCSP).
FUNCTIONAL BLOCK DIAGRAM
0.1µF
10µF
SSM2315
47nF*
AUDIO IN+
IN+
IN–
AUDIO IN–
VBATT
2.5V TO 5.5V
VDD
160kΩ
80kΩ
80kΩ
OUT+
MODULATOR
(Σ-Δ)
FET
DRIVER
OUT–
47nF*
160kΩ
SHUTDOWN
SD
BIAS
INTERNAL
OSCILLATOR
POP/CLICK
SUPPRESSION
*INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY VDD/2.
06857-001
GND
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
SSM2315
TABLE OF CONTENTS
Features .............................................................................................. 1 Typical Application Circuits ......................................................... 11 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 12 General Description ......................................................................... 1 Overview ..................................................................................... 12 Functional Block Diagram .............................................................. 1 Gain .............................................................................................. 12 Revision History ............................................................................... 2 Pop-and-Click Suppression ...................................................... 12 Specifications..................................................................................... 3 Output Modulation Description .............................................. 12 Absolute Maximum Ratings............................................................ 4 Layout .......................................................................................... 13 Thermal Resistance ...................................................................... 4 Input Capacitor Selection .......................................................... 13 ESD Caution .................................................................................. 4 Proper Power Supply Decoupling ............................................ 13 Pin Configuration and Function Descriptions ............................. 5 Outline Dimensions ....................................................................... 14 Typical Performance Characteristics ............................................. 6 Ordering Guide .......................................................................... 14 REVISION HISTORY
8/08—Rev. 0 to Rev. A
Changes to Efficiency and Total Harmonic
Distortion + Noise Parameters ....................................................... 3
Changes to Ordering Guide .......................................................... 14
2/08—Revision 0: Initial Version
Rev. A | Page 2 of 16
SSM2315
SPECIFICATIONS
VDD = 5.0 V, TA = 25oC, RL = 8 Ω + 33 μH, unless otherwise noted.
Table 1.
Parameter
DEVICE CHARACTERISTICS
Output Power
Symbol
Conditions1
PO
RL = 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V
RL = 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V
RL = 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V
RL = 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V
RL = 4 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V
RL = 4 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V
RL = 4 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V
RL = 4 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V
RL = 3 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V
RL = 3 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V
RL = 3 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V
RL = 3 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V
PO = 1.4 W, RL = 8 Ω + 33 μH, VDD = 5.0 V
PO = 1 W, RL = 8 Ω + 33 μH, f = 1 kHz, VDD = 5.0 V
PO = 0.5 W, RL = 8 Ω + 33 μH, f = 1 kHz, VDD = 3.6 V
Efficiency
Total Harmonic Distortion + Noise
η
THD + N
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
Average Switching Frequency
Differential Output Offset Voltage
POWER SUPPLY
Supply Voltage Range
Power Supply Rejection Ratio
VCM
CMRRGSM
fSW
VOOS
Supply Current
VDD
PSRR
PSRRGSM
ISY
Shutdown Current
Min
Typ
Max
1.48
0.75
1.84
0.94
2.72
1.38
3.402
1.72
3.43
1.72
4.282
2.14
93
0.004
0.004
1.0
VCM = 2.5 V ± 100 mV at 217 Hz, output referred
VDD − 1.0
55
280
2.0
Gain = 6 dB
ISD
GAIN CONTROL
Closed-Loop Gain
Differential Input Impedance
Gain
ZIN
SD = VDD
6
80
dB
kΩ
SHUTDOWN CONTROL
Input Voltage High
Input Voltage Low
Turn-On Time
Turn-Off Time
Output Impedance
VIH
VIL
tWU
tSD
ZOUT
ISY ≥ 1 mA
ISY ≤ 300 nA
SD rising edge from GND to VDD
SD falling edge from VDD to GND
SD = GND
1.2
0.5
7
5
>100
V
V
ms
μs
kΩ
NOISE PERFORMANCE
Output Voltage Noise
en
VDD = 3.6 V, f = 20 Hz to 20 kHz, inputs are ac-grounded,
gain = 6 dB, A-weighted
PO = 1.4 W, RL = 8 Ω
21
μV rms
103
dB
1
2
SNR
5.5
W
W
W
W
W
W
W
W
W
W
W
W
%
%
%
V
dB
kHz
mV
Guaranteed from PSRR test
VDD = 2.5 V to 5.0 V, dc input floating
VRIPPLE = 100 mV at 217 Hz, inputs ac GND, CIN = 0.1 μF
VIN = 0 V, no load, VDD = 5.0 V
VIN = 0 V, no load, VDD = 3.6 V
VIN = 0 V, no load, VDD = 2.5 V
VIN = 0 V, load = 8 Ω + 33 μH, VDD = 5.0 V
VIN = 0 V, load = 8 Ω + 33 μH, VDD = 3.6 V
VIN = 0 V, load = 8 Ω + 33 μH, VDD = 2.5 V
SD = GND
Signal-to-Noise Ratio
2.5
70
Unit
85
60
3.2
2.8
2.4
3.3
2.9
2.4
20
V
dB
dB
mA
mA
mA
mA
mA
mA
nA
Note that although the SSM2315 has good audio quality above 3 W, continuous output power beyond 3 W must be avoided due to device packaging limitations.
This value represents measured performance; packaging limitations must not be exceeded.
Rev. A | Page 3 of 16
SSM2315
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply at 25°C, unless otherwise noted.
THERMAL RESISTANCE
Table 2.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Parameter
Supply Voltage
Input Voltage
Common-Mode Input Voltage
Continuous Output Power
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Soldering, 60 sec)
Rating
6V
VDD
VDD
3W
−65°C to +150°C
−40°C to +85°C
−65°C to +165°C
300°C
Table 3. Thermal Resistance
Package Type
9-ball, 1.5 mm × 1.5 mm WLCSP
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. A | Page 4 of 16
PCB
1S0P
2S0P
θJA
162
76
θJB
39
21
Unit
°C/W
°C/W
SSM2315
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
BALL A1
CORNER
1
2
3
A
B
C
06857-002
SSM2315
TOP VIEW
BALL SIDE DOWN
(Not to Scale)
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
2C
2A
1A
1C
3C
1B
3B
3A
2B
Mnemonic
SD
GND
IN+
IN−
OUT+
VDD
GND
OUT−
PVDD
Description
Shutdown Input. Active low digital input.
Ground.
Noninverting Input.
Inverting Input.
Noninverting Output.
Power Supply.
Ground.
Inverting Output.
Power Supply.
Rev. A | Page 5 of 16
SSM2315
TYPICAL PERFORMANCE CHARACTERISTICS
100
100
RL = 8Ω + 33µH
GAIN = 6dB
VDD = 3.6V
VDD = 2.5V
10
10
VDD = 5V
GAIN = 6dB
RL = 8Ω + 33µH
THD + N (%)
THD + N (%)
1
1
0.1
0.1
0.25W
0.01
VDD = 5V
0.01
0.5W
0.001
0.01
0.1
1
10
OUTPUT POWER (W)
06857-003
0.001
Figure 3. THD + N vs. Output Power, RL = 8 Ω + 33 μH, Gain = 6 dB
100
RL = 4Ω + 33µH
GAIN = 6dB
0.0001
10
1k
10k
100k
FREQUENCY (Hz)
Figure 6. THD + N vs. Frequency, VDD = 5 V, RL = 8 Ω + 33 μH, Gain = 6 dB
100
VDD = 3.6V
VDD = 2.5V
10
100
06857-006
1W
0.001
0.0001
10
VDD = 5V
GAIN = 6dB
RL = 4Ω + 33µH
THD + N (%)
0.1
0.1
0.5W
0.01
0.01
1W
0.001
VDD = 5V
0.01
0.1
1
10
OUTPUT POWER (W)
Figure 4. THD + N vs. Output Power, RL = 4 Ω + 33 μH, Gain = 6 dB
100
RL = 3Ω + 33µH
GAIN = 6dB
1k
100k
Figure 7. THD + N vs. Frequency, VDD = 5 V, RL = 4 Ω + 33 μH, Gain = 6 dB
100
10
VDD = 2.5V
VDD = 5V
GAIN = 6dB
RL = 3Ω + 33µH
3W
1
THD + N (%)
1
0.1
0.1
0.5W
0.01
0.01
0.75W
0.001
VDD = 5V
0.001
0.0001
0.001
0.01
0.1
1
10
OUTPUT POWER (W)
Figure 5. THD + N vs. Output Power, RL = 3 Ω + 33 μH, Gain = 6 dB
0.0001
10
06857-005
THD + N (%)
10k
FREQUENCY (Hz)
VDD = 3.6V
10
100
06857-007
0.001
2W
0.0001
10
06857-004
0.001
0.0001
100
1k
FREQUENCY (Hz)
10k
100k
06857-008
THD + N (%)
1
1
Figure 8. THD + N vs. Frequency, VDD = 5 V, RL = 3 Ω + 33 μH, Gain = 6 dB
Rev. A | Page 6 of 16
SSM2315
100
VDD = 3.6V
GAIN = 6dB
RL = 8Ω + 33µH
10
10
1
1
THD + N (%)
THD + N (%)
100
0.1
VDD = 2.5V
GAIN = 6dB
RL = 8Ω + 33µH
0.1
0.25W
0.125W
0.01
0.01
0.25W
1k
10k
100k
FREQUENCY (Hz)
Figure 9. THD + N vs. Frequency, VDD = 3.6 V, RL = 8 Ω + 33 μH, Gain = 6 dB
100
10
10
1
1
0.5W
0.01
0.125W
1k
10k
100k
Figure 12. THD + N vs. Frequency, VDD = 2.5 V, RL = 8 Ω + 33 μH, Gain = 6 dB
VDD = 3.6V
GAIN = 6dB
RL = 4Ω + 33µH
0.1
0.63W
100
FREQUENCY (Hz)
THD + N (%)
THD + N (%)
100
0.001
10
06857-012
100
06857-009
0.001
10
0.5W
VDD = 2.5V
GAIN = 6dB
RL = 4Ω + 33µH
0.5W
0.1
0.25W
0.01
1W
100
1k
10k
100k
FREQUENCY (Hz)
Figure 10. THD + N vs. Frequency, VDD = 3.6 V, RL = 4 Ω + 33 μH, Gain = 6 dB
1k
100k
Figure 13. THD + N vs. Frequency, VDD = 2.5 V, RL = 4 Ω + 33 μH, Gain = 6 dB
100
VDD = 3.6V
GAIN = 6dB
RL = 3Ω + 33µH
VDD = 2.5V
GAIN = 6dB
RL = 3Ω + 33µH
10
1
THD + N (%)
1.5W
0.1
0.75W
1
0.1
0.375W
0.75W
0.01
0.01
0.188W
0.38W
100
1k
FREQUENCY (Hz)
10k
100k
0.001
10
06857-011
0.001
10
10k
FREQUENCY (Hz)
10
THD + N (%)
0.125W
100
Figure 11. THD + N vs. Frequency, VDD = 3.6 V, RL = 3 Ω + 33 μH, Gain = 6 dB
100
1k
FREQUENCY (Hz)
10k
100k
06857-014
100
0.001
10
06857-013
0.25W
06857-010
0.001
10
Figure 14. THD + N vs. Frequency, VDD = 2.5 V, RL = 3 Ω + 33 μH, Gain = 6 dB
Rev. A | Page 7 of 16
SSM2315
4.1
4.5
FREQUENCY = 1kHz
GAIN = 6dB
4.0 R = 3Ω + 33µH
L
3.5
3.7
RL = 3Ω + 33µH
OUTPUT POWER (W)
3.5
RL = 4Ω + 33µH
3.3
NO LOAD
3.1
2.9
10%
2.5
1.5
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
0
2.5
100
FREQUENCY = 1kHz
1.8 GAIN = 6dB
RL = 8Ω + 33µH
80
1.4
70
EFFICIENCY (%)
1.6
1.2
10%
1.0
1%
40
30
20
0.2
10
5.0
SUPPLY VOLTAGE (V)
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
OUTPUT POWER (W)
Figure 16. Maximum Output Power vs. Supply Voltage,
RL = 8 Ω + 33 μH, Gain = 6 dB
Figure 19. Efficiency vs. Output Power, RL = 8 Ω + 33 μH
4.0
100
FREQUENCY = 1kHz
GAIN = 6dB
3.5 RL = 4Ω + 33µH
90
80
DO NOT EXCEED 3W CONTINUOUS OUTPUT POWER
3.0
RL = 8Ω + 33µH
0
06857-016
4.5
VDD = 5V
50
0.4
4.0
5.0
60
0.6
3.5
4.5
VDD = 3.6V
VDD = 2.5V
90
0.8
4.0
Figure 18. Maximum Output Power vs. Supply Voltage,
RL = 3 Ω + 33 μH, Gain = 6 dB
2.0
3.0
3.5
SUPPLY VOLTAGE (V)
Figure 15. Supply Current vs. Supply Voltage
0
2.5
3.0
06857-019
3.5
06857-015
3.0
06857-018
0.5
2.5
2.5
OUTPUT POWER (W)
1%
2.0
1.0
2.7
EFFICIENCY (%)
70
2.5
10%
2.0
1%
1.5
VDD = 2.5V
VDD = 3.6V
VDD = 5V
60
50
40
30
1.0
20
0.5
10
0
2.5
3.0
3.5
4.0
4.5
SUPPLY VOLTAGE (V)
5.0
06857-017
OUTPUT POWER (W)
DO NOT EXCEED 3W
CONTINUOUS OUTPUT POWER
3.0
Figure 17. Maximum Output Power vs. Supply Voltage,
RL = 4 Ω + 33 μH, Gain = 6 dB
RL = 4Ω + 33µH
0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2
OUTPUT POWER (W)
Figure 20. Efficiency vs. Output Power, RL = 4 Ω + 33 μH
Rev. A | Page 8 of 16
06857-020
SUPPLY CURRENT (mA)
3.9
SSM2315
0.16
0.25
VDD = 5V
RL = 8Ω + 33µH
0.14
VDD = 3.6V
RL = 4Ω + 33µH
POWER DISSIPATION (W)
POWER DISSIPATION (W)
0.20
0.12
0.10
0.08
0.06
0.04
0.15
0.10
0.05
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
OUTPUT POWER (W)
Figure 21. Power Dissipation vs. Output Power, RL = 8 Ω + 33 μH at VDD = 5.0 V
0.40
0
0.4
0.6
0.8
1.0
1.2
1.4
1.6
Figure 24. Power Dissipation vs. Output Power, RL = 4 Ω + 33 μH at VDD = 3.6 V
400
RL = 8Ω + 33µH
VDD = 5V
350
SUPPLY CURRENT (mA)
0.30
0.25
0.20
0.15
0.10
0.05
300
VDD = 3.6V
250
VDD = 2.5V
200
150
100
0.5
1.0
1.5
2.0
2.5
3.0
OUTPUT POWER (W)
0
06857-022
0
0
0.6
0.8
1.0
1.2
1.4
1.6
1.8
Figure 25. Supply Current vs. Output Power, RL = 8 Ω + 33 μH
800
VDD = 3.6V
RL = 8Ω + 33µH
0.08
0.4
OUTPUT POWER (W)
Figure 22. Power Dissipation vs. Output Power, RL = 4 Ω + 33 μH at VDD = 5.0 V
0.09
0.2
06857-025
50
0
RL = 4Ω + 33µH
700
VDD = 5V
0.07
SUPPLY CURRENT (mA)
0.06
0.05
0.04
0.03
0.02
600
VDD = 3.6V
500
400
VDD = 2.5V
300
200
100
0
0
0.1
0.2
0.3
0.4
0.5
0.6
OUTPUT POWER (W)
0.7
0.8
0.9
06857-023
0.01
Figure 23. Power Dissipation vs. Output Power, RL = 8 Ω + 33 μH at VDD = 3.6 V
Rev. A | Page 9 of 16
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
OUTPUT POWER (W)
Figure 26. Supply Current vs. Output Power, RL = 4 Ω + 33 μH
06857-026
POWER DISSIPATION (W)
0.2
OUTPUT POWER (W)
VDD = 5V
RL = 4Ω + 33µH
0.35
POWER DISSIPATION (W)
0
06857-021
0
06857-024
0.02
8
–10
7
–20
6
–30
5
–50
–60
4
3
2
–70
1
–80
0
–90
–1
–100
10
100
1k
10k
100k
FREQUENCY (Hz)
–2
–2
OUTPUT
0
6
8
10
12
14
16
18
20
90
Figure 29. Turn-On Response
8
–10
7
–20
6
–30
5
VOLTAGE (V)
0
–40
–50
–60
–70
4
3
OUTPUT
2
1
–80
0
–90
–1
100
1k
10k
100k
FREQUENCY (Hz)
06857-028
CMRR (dB)
4
TIME (ms)
Figure 27. Power Supply Rejection Ratio (PSRR) vs. Frequency
–100
10
2
06857-029
–40
SD INPUT
06857-030
VOLTAGE (V)
0
06857-027
PSRR (dB)
SSM2315
Figure 28. Common-Mode Rejection Ratio (CMRR) vs. Frequency
–2
–90
SD INPUT
–70
–50
–30
–10
10
30
TIME (µs)
Figure 30. Turn-Off Response
Rev. A | Page 10 of 16
50
70
SSM2315
TYPICAL APPLICATION CIRCUITS
EXTERNAL GAIN SETTINGS = 160kΩ/(80kΩ + REXT )
0.1µF
10µF
SSM2315
47nF*
AUDIO IN+
REXT
REXT
AUDIO IN–
IN+
IN–
VBATT
2.5V TO 5.5V
VDD
160kΩ
80kΩ
80kΩ
OUT+
MODULATOR
(Σ-Δ)
FET
DRIVER
OUT–
47nF*
160kΩ
SD
SHUTDOWN
INTERNAL
OSCILLATOR
BIAS
POP/CLICK
SUPPRESSION
06857-031
GND
*INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY VDD/2.
Figure 31. Differential Input Configuration, User-Adjustable Gain
EXTERNAL GAIN SETTINGS = 160kΩ/(80kΩ + REXT )
0.1µF
10µF
SSM2315
47nF
AUDIO IN+
REXT
IN+
80kΩ
REXT
IN–
80kΩ
VBATT
2.5V TO 5.5V
VDD
160kΩ
OUT+
MODULATOR
(Σ-Δ)
FET
DRIVER
OUT–
47nF
160kΩ
SD
BIAS
INTERNAL
OSCILLATOR
POP/CLICK
SUPPRESSION
GND
Figure 32. Single-Ended Input Configuration, User-Adjustable Gain
Rev. A | Page 11 of 16
06857-032
SHUTDOWN
SSM2315
THEORY OF OPERATION
OVERVIEW
OUTPUT MODULATION DESCRIPTION
The SSM2315 mono Class-D audio amplifier features a filterless
modulation scheme that greatly reduces the external component
count, conserving board space and, thus, reducing systems cost.
The SSM2315 does not require an output filter but, instead, relies
on the inherent inductance of the speaker coil and the natural
filtering of the speaker and human ear to fully recover the audio
component of the square wave output. Most Class-D amplifiers
use some variation of pulse-width modulation (PWM), but the
SSM2315 uses a Σ-Δ modulation to determine the switching
pattern of the output devices, resulting in a number of important
benefits. Σ-Δ modulators do not produce a sharp peak with many
harmonics in the AM frequency band, as pulse-width modulators
often do. Σ-Δ modulation provides the benefits of reducing the
amplitude of spectral components at high frequencies, that is,
reducing EMI emission that may otherwise be radiated by
speakers and long cable traces. The SSM2315 does not require
external EMI filtering for twisted speaker cable lengths shorter
than 10 cm. Due to the inherent spread spectrum nature of Σ-Δ
modulation, the need for oscillator synchronization is eliminated
for designs incorporating multiple SSM2315 amplifiers.
The SSM2315 uses three-level, Σ-Δ output modulation. Each
output can swing from GND to VDD and vice versa. Ideally,
when no input signal is present, the output differential voltage
is 0 V because there is no need to generate a pulse. In a real world
situation, there are always noise sources present.
However, most of the time, output differential voltage is 0 V,
due to the Analog Devices patented, three-level, Σ-Δ output
modulation. This feature ensures that the current flowing through
the inductive load is small.
When the user wants to send an input signal, an output pulse
is generated to follow the input voltage. The differential pulse
density is increased by raising the input signal level. Figure 33
depicts three-level, Σ-Δ output modulation with and without
input stimulus.
OUTPUT = 0V
OUT+
0V
+5V
OUT–
GAIN
The SSM2315 has a default gain of 6 dB that can be reduced by
using a pair of external resistors with a value calculated as follows:
0V
+5V
VOUT
0V
–5V
OUTPUT > 0V
External Gain Settings = 160 kΩ/(80 kΩ + REXT)
OUT+
POP-AND-CLICK SUPPRESSION
0V
+5V
VOUT
0V
OUTPUT < 0V
OUT+
OUT–
VOUT
+5V
0V
+5V
OUT–
Voltage transients at the output of audio amplifiers may occur
when shutdown is activated or deactivated. Voltage transients as
low as 10 mV can be heard as an audio pop in the speaker. Clicks
and pops can also be classified as undesirable audible transients
generated by the amplifier system and, therefore, as not coming
from the system input signal. Such transients may be generated
when the amplifier system changes its operating mode. For example,
the following may be sources of audible transients: system power-up
and power-down, mute and unmute, input source change, and
sample rate change. The SSM2315 has a pop-and-click suppression
architecture that reduces these output transients, resulting in
noiseless activation and deactivation.
+5V
+5V
0V
+5V
0V
0V
–5V
06857-033
The SSM2315 also offers protection circuits for overcurrent and
temperature protection.
Due to this constant presence of noise, a differential pulse is
generated, when required, in response to this stimulus. A small
amount of current flows into the inductive load when the differential pulse is generated.
Figure 33. Three-Level, Σ-Δ Output Modulation With and Without Input Stimulus
Rev. A | Page 12 of 16
SSM2315
LAYOUT
INPUT CAPACITOR SELECTION
As output power continues to increase, care must be taken to lay
out PCB traces and wires properly among the amplifier, load,
and power supply. A good practice is to use short, wide PCB
tracks to decrease voltage drops and to minimize inductance.
Ensure that track widths are at least 200 mil for every inch of track
length for lowest DCR, and use 1 oz or 2 oz of copper PCB traces
to further reduce IR drops and inductance. A poor layout increases
voltage drops, consequently affecting efficiency. Use large traces
for the power supply inputs and amplifier outputs to minimize
losses due to parasitic trace resistance.
The SSM2315 does not require input coupling capacitors if the
input signal is biased from 1.0 V to VDD − 1.0 V. Input capacitors are
required if the input signal is not biased within this recommended
input dc common-mode voltage range, if high-pass filtering is
needed, or if a single-ended source is used. If high-pass filtering
is needed at the input, the input capacitor and the input resistor
of the SSM2315 form a high-pass filter whose corner frequency
is determined by the following equation:
Proper grounding guidelines help improve audio performance,
minimize crosstalk between channels, and prevent switching noise
from coupling into the audio signal. To maintain high output swing
and high peak output power, the PCB traces that connect the
output pins to the load and supply pins should be as wide as
possible to maintain the minimum trace resistances. It is also
recommended that a large ground plane be used for minimum
impedances.
In addition, good PCB layouts isolate critical analog paths from
sources of high interference. High frequency circuits (analog
and digital) should be separated from low frequency circuits.
Properly designed multilayer printed circuit boards can reduce
EMI emission and increase immunity to the RF field by a factor
of 10 or more, compared with double-sided boards. A multilayer
board allows a complete layer to be used for the ground plane,
whereas the ground plane side of a double-sided board is often
disrupted with signal crossover.
fC = 1/(2π × RIN × CIN)
The input capacitor can significantly affect the performance of
the circuit. Not using input capacitors degrades both the output
offset of the amplifier and the dc PSRR performance.
PROPER POWER SUPPLY DECOUPLING
To ensure high efficiency, low total harmonic distortion (THD),
and high PSRR, proper power supply decoupling is necessary.
Noise transients on the power supply lines are short-duration
voltage spikes. Although the actual switching frequency can range
from 10 kHz to 100 kHz, these spikes can contain frequency
components that extend into the hundreds of megahertz. The
power supply input needs to be decoupled with a good quality,
low ESL, low ESR capacitor, usually of around 4.7 μF. This capacitor
bypasses low frequency noises to the ground plane. For high
frequency transients noises, use a 0.1 μF capacitor as close as
possible to the VDD pin of the device. Placing the decoupling
capacitor as close as possible to the SSM2315 helps maintain
efficient performance.
If the system has separate analog and digital ground and power
planes, the analog ground plane should be underneath the analog
power plane. Similarly, the digital ground plane should be
underneath the digital power plane. There should be no overlap
between analog and digital ground planes or analog and digital
power planes.
Rev. A | Page 13 of 16
SSM2315
OUTLINE DIMENSIONS
1.490
1.460 SQ
1.430
SEATING
PLANE
3
2
A
0.350
0.320
0.290
B
C
0.50
BALL PITCH
TOP VIEW
(BALL SIDE DOWN)
0.385
0.360
0.335
1
BOTTOM VIEW
0.270
0.240
0.210
(BALL SIDE UP)
101507-C
A1 BALL
CORNER
0.655
0.600
0.545
Figure 34. 9-Ball Wafer Level Chip Scale Package [WLCSP]
(CP-9-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
SSM2315CBZ-R21
SSM2315CBZ-REEL1
SSM2315CBZ-REEL71
SSM2315-EVALZ1
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
9-Ball Wafer Level Chip Scale Package [WLCSP]
9-Ball Wafer Level Chip Scale Package [WLCSP]
9-Ball Wafer Level Chip Scale Package [WLCSP]
Evaluation Board
Z = RoHS Compliant Part.
Rev. A | Page 14 of 16
Package Option
CB-9-2
CB-9-2
CB-9-2
Branding
Y0P
Y0P
Y0P
SSM2315
NOTES
Rev. A | Page 15 of 16
SSM2315
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06857-0-8/08(A)
Rev. A | Page 16 of 16