TI TPA3000D1

TPA3000D1
SLOS379A – SEPTEMBER 2001 – REVISED JANUARY 2002
17-W MONO FILTER-FREE CLASS-D AUDIO POWER AMPLIFIER
FEATURES
D 17 W Into 8-Ω Load From 18-V Supply
D Third-Generation Modulation Technique:
D
D
D
D
D
DESCRIPTION
The TPA3000D1 is a 17-W mono bridge-tied load (BTL)
filter-free class-D audio power amplifier with high
efficiency, eliminating the need for heatsinks. The
TPA3000D1 is designed to drive speakers without an
output filter.
– Filter-Free Operation
– Improved Efficiency
– Improved SNR
Low Supply Current . . . 8 mA Typ at 12 V
Shutdown Control . . . <1 µA Typ
Shutdown Pin Is TTL Compatible
TA = –40°C to 85°C
Space-Saving, Thermally-Enhanced
PowerPAD Packaging
The gain of the amplifier is controlled by two input
terminals, GAIN1 and GAIN0. This allows the amplifier
to be configured for a gain of 12, 18, 23.6, and 36 dB.
The differential input stage provides high common
mode rejection and improved power supply rejection.
The amplifier also includes depop circuitry to reduce the
amount of turnon pop at power-up and when cycling
SHUTDOWN.
APPLICATIONS
D LCD Monitors
D Hands-Free Car Kits
D Powered Speakers
The TPA3000D1 is available in the 24-pin thermally
enhanced TSSOP package (PWP) which eliminates the
need for an external heat sink when playing music.
EFFICIENCY
vs
OUTPUT POWER
OUTPUT POWER
vs
SUPPLY VOLTAGE
100
17
90
15
80
PO – Output Power – W
RL = 8 Ω Speaker
Efficiency – %
70
60
50
40
30
13
11
RL = 8 Ω
9
7
20
0
0
3
6
9
12
VCC = 8 V TO 18 V
f = 1 kHz
Maximum 1% THD+N
5
VCC = 15 V
f = 1 kHz
10
15
PO – Output Power – W
3
8
10
12
14
16
18
VCC – Supply Voltage – V
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
1
TPA3000D1
SLOS379A – SEPTEMBER 2001 – REVISED JANUARY 2002
AVAILABLE OPTIONS
PACKAGED DEVICES
TSSOP (PWP)†
TA
– 40°C to 85°C
TPA3000D1PWP
† The PWP package is available taped and reeled. To order a taped and
reeled part, add the suffix R to the part number (e.g., TPA3000D1PWPR).
PWP PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
INN
INP
GAIN0
GAIN1
SHUTDOWN
PGND
VCLAMP
BSN
PVCC
OUTN
OUTN
PGND
24
23
22
21
20
19
18
17
16
15
14
13
VCC
VREF
BYPASS
COSC
ROSC
AGND
AGND
BSP
PVCC
OUTP
OUTP
PGND
Terminal Functions
TERMINAL
NAME
AGND
NO.
I/O
18, 19
DESCRIPTION
Analog ground
BSN
8
I
Bootstrap pin for high-side gate drive of negative BTL output (connect a 10-nF capacitor from OUTN to
BSN)
BSP
17
I
Bootstrap pin for high-side gate drive of positive BTL output (connect a 10-nF capacitor from OUTP
to BSP)
BYPASS
22
I
Connect 0.47 µF capacitor to ground for BYPASS voltage filtering.
COSC
21
I
Connect a 220-pF capacitor to ground to set oscillation frequency.
GAIN0
3
I
Bit 0 of gain control (see Table 1 for gain settings)
GAIN1
4
I
Bit 1 of gain control (see Table 1 for gain settings)
INN
1
I
Negative differential input
INP
2
I
Positive differential input
OUTN
10, 11
O
Negative BTL output
OUTP
14, 15
O
Positive BTL output
PGND
6, 12, 13
PVCC
ROSC
9, 16
I
High-voltage power supply (for output stages)
20
I
Connect 120 kΩ resistor to ground to set oscillation frequency.
SHUTDOWN
5
I
Shutdown terminal (negative logic), TTL compatible, 21-V compliant
VCC
VCLAMP
24
I
Analog high-voltage power supply
7
O
Connect 100-nF capacitor to ground to provide reference voltage for H-bridge gates
VREF
23
O
5-V internal regulator for control circuitry (connect a 0.1-µF to 1-µF capacitor to ground)
2
Power ground
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TPA3000D1
SLOS379A – SEPTEMBER 2001 – REVISED JANUARY 2002
functional block diagram
VREF
AGND
VREF
VCC
VCLAMP
VCC
Clamp
Reference
BSN
PVCC
+
_
Gain
Adjust
INN
Deglitch
Logic
Gate
Drive
OUTN
_
PGND
+
_
+
Gain
Adjust
INP
BSP
+
_
PVCC
+
_
_
+
Deglitch
Logic
Gate
Drive
OUTP
PGND
SHUTDOWN
SD
GAIN1
GAIN0
2
Gain
Biases
and
References
Ramp
Generator
COSC
ROSC
BYPASS
OC
Detect{
Start-Up
Protection
Logic
Thermal
VCC OK
† Short-circuit protection operates only for shorts from the outputs to ground.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage: VCC, PVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 21 V
Input voltage: SHUTDOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V
GAIN0, GAIN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 5.5 V
INN, INP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (see Dissipation Rating Table)
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
} Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
PACKAGE
PWP
TA ≤ 25°C
2.7 W
DERATING FACTOR
21.8 mW/°C
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TA = 70°C
1.7 W
TA = 85°C
1.4 W
3
TPA3000D1
SLOS379A – SEPTEMBER 2001 – REVISED JANUARY 2002
recommended operating conditions
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Supply voltage, VCC, PVCC
GAIN0, GAIN1, SHUTDOWN†
GAIN0, GAIN1, SHUTDOWN†
High-level input voltage, VIH
Low-level input voltage, VIL
MIN
MAX
8
18
2
Operating free-air temperature, TA
† See Application Information for more information on the characteristics of the SHUTDOWN terminal.
– 40
UNIT
V
V
0.8
V
85
°C
electrical characteristics at TA = 25°C, PVCC = VCC = 12 V (unless otherwise noted)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PARAMETER
TEST CONDITIONS
|VOS|
Output offset voltage (measured differentially)
PSRR
Power supply rejection ratio
|IIH|
High-level input current
|IIL|
Low-level input current
ICC
ICC(SD)
Supply current
Supply current, shutdown mode
MIN
VI = 0 V,
AV = 12 dB
PVCC = 11.5 V to 12.5 V
PVCC = 12 V,
PVCC = 12 V,
TYP
MAX
50
–75
VI = PVCC
UNIT
mV
dB
1
µA
–1
µA
8
15
mA
1
2
µA
VI = 0 V
operating characteristics, PVCC = VCC = 12 V, TA = 25°C, RL = 8 Ω, Gain = 12 dB (unless otherwise
noted)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
Output power
THD = 0.5%,
f = 1 kHz
Total harmonic distortion plus noise
1%
Maximum output power bandwidth
PO = 15 W,
THD = 1%
f = 20 Hz to 20 kHz
BOM
kSVR
20
kHz
Supply ripple rejection ratio
f = 1 kHz,
C(BYPASS) = 0.47 µF
–70
dB
SNR
Signal-to-noise ratio
PO = 12 W
95
dB
C(BYPASS) = 0.47 µF, f = 20 Hz to 22 kHz,
No weighting filter used
86
µV(rms)
Vn
Zi
Noise output voltage
C(BYPASS) = 0.47 µF,
A-weighted filter
7
UNIT
PO
THD + N
f = 20 Hz to 22 kHz,
Input impedance
W
–81
dBV
66
µV(rms)
–84
dBV
>23
kΩ
operating characteristics, PVCC = VCC = 18 V, TA = 25°C, RL = 8 Ω, Gain = 12 dB (unless otherwise
noted)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PARAMETER
TEST CONDITIONS
PO
THD + N
Output power
THD = 0.5%,
f = 1 kHz
Total harmonic distortion plus noise
f = 20 Hz to 20 kHz
BOM
kSVR
Maximum output power bandwidth
PO = 15 W,
THD = 1%
Supply ripple rejection ratio
f = 1 kHz,
CBYPASS = 0.47 µF
SNR
Signal-to-noise ratio
PO = 17 W
C(BYPASS) = 0.47 µF, f = 20 Hz to 20 kHz,
No weighting filter used
Vn
Zi
4
Noise output voltage
C(BYPASS) = 0.47 µF,
A-weighted filter
Input impedance
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f = 20 Hz to 22 kHz,
MIN
TYP
17
MAX
UNIT
W
1%
20
kHz
70
dB
102
dB
86
µV(rms)
–81
dBV
66
µV(rms)
–84
dBV
>23
kΩ
TPA3000D1
SLOS379A – SEPTEMBER 2001 – REVISED JANUARY 2002
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Efficiency
vs Output power
PO
ICC
Output power
IO(sd)
Shutdown current
1, 2, 3
4
Supply current
vs Supply
Su ly voltage
5
vs Output power
7, 8, 9, 10
6
THD+N
Total harmonic distortion + noise
kSVR
Supply voltage rejection ratio
vs Frequency
11, 12, 13, 14
15, 16, 17
Gain and phase
18
vs Frequency
CMRR
Common-mode rejection ratio
VIO
Input offset voltage
19
vs Common-mode input voltage
EFFICIENCY
vs
OUTPUT POWER
EFFICIENCY
vs
OUTPUT POWER
100
100
90
90
80
80
RL = 8 Ω Speaker
70
Efficiency – %
Efficiency – %
70
60
50
40
50
40
30
20
20
VCC = 15 V
f = 1 kHz
RL = 8 Ω Speaker
60
30
10
20, 21, 22
VCC = 18 V
f = 1 kHz
10
0
0
0
3
6
9
12
15
0
2
4
6
8
10
12
PO – Output Power – W
PO – Output Power – W
Figure 1
Figure 2
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5
TPA3000D1
SLOS379A – SEPTEMBER 2001 – REVISED JANUARY 2002
TYPICAL CHARACTERISTICS
EFFICIENCY
vs
OUTPUT POWER
OUTPUT POWER
vs
SUPPLY VOLTAGE
100
17
90
15
Efficiency – %
70
PO – Output Power – W
80
RL = 8 Ω Speaker
60
50
40
30
13
11
RL = 8 Ω
9
7
20
0
0
1
2
3
VCC = 8 V TO 18 V
f = 1 kHz
Maximum 1% THD+N
5
VCC = 8 V
f = 1 kHz
10
3
4
8
10
PO – Output Power – W
12
Figure 3
18
SHUTDOWN CURRENT
vs
SUPPLY VOLTAGE
11
5
ICC(SD) – Shutdown Current – µA
10
ICC – Supply Current – mA
16
Figure 4
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
9
8
7
6
8
10
12
14
16
18
VCC – Supply Voltage – V
4
3
2
1
0
8
10
12
14
VCC – Supply Voltage – V
Figure 6
Figure 5
6
14
VCC – Supply Voltage – V
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16
18
TPA3000D1
SLOS379A – SEPTEMBER 2001 – REVISED JANUARY 2002
TYPICAL CHARACTERISTICS
10
VCC = 18 V
RL = 8 Ω
Gain = 12 dB
1
f = 1 kHz
0.1
f = 20 Hz
f = 20 kHz
0.01
0.01
0.1
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
THD+N – Total Harmonic Distortion + Noise – %
THD+N – Total Harmonic Distortion + Noise – %
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
1
10
VCC = 15 V
RL = 8 Ω
Gain = 12 dB
10
1
f = 20 kHz
f = 1 kHz
0.1
f = 20 Hz
0.01
0.01
0.1
PO – Output Power – W
Figure 7
f = 1 kHz
0.1
f = 20 kHz
f = 20 Hz
0.1
1
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
THD+N – Total Harmonic Distortion + Noise – %
THD+N – Total Harmonic Distortion + Noise – %
VCC = 12 V
RL = 8 Ω
Gain = 12 dB
1
0.01
0.01
10
Figure 8
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
1
PO – Output Power – W
10
1
f = 1 kHz
0.1
f = 20 Hz
f = 20 kHz
0.01
0.01
10
PO – Output Power – W
VCC = 8 V
RL = 8 Ω
Gain = 12 dB
0.1
1
PO – Output Power – W
Figure 9
Figure 10
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7
TPA3000D1
SLOS379A – SEPTEMBER 2001 – REVISED JANUARY 2002
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
1
THD+N – Total Harmonic Distortion + Noise – %
THD+N – Total Harmonic Distortion + Noise – %
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
VCC = 18 V
RL = 8 Ω
Gain = 12 dB
PO = 500 mW
PO = 2 W
0.1
PO = 10 W
0.01
20
100
1k
10k
1
VCC = 15 V
RL = 8 Ω
Gain = 12 dB
0.1
PO = 500 mW
PO = 2 W
PO = 10 W
0.01
20
100
f – Frequency – Hz
f – Frequency – Hz
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
1
THD+N – Total Harmonic Distortion + Noise – %
THD+N – Total Harmonic Distortion + Noise – %
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
VCC = 12 V
RL = 8 Ω
Gain = 12 dB
PO = 250 mW
0.1
PO = 1 W
PO = 5 W
0.01
100
1k
1
VCC = 8 V
RL = 8 Ω
Gain = 12 dB
PO = 250 mW
0.1
PO = 1 W
PO = 5 W
0.01
20
10k
100
1k
f – Frequency – Hz
f – Frequency – Hz
Figure 13
8
10k
Figure 12
Figure 11
20
1k
Figure 14
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10k
TPA3000D1
SLOS379A – SEPTEMBER 2001 – REVISED JANUARY 2002
TYPICAL CHARACTERISTICS
SUPPLY VOLTAGE REJECTION RATIO
vs
FREQUENCY
SUPPLY VOLTAGE REJECTION RATIO
vs
FREQUENCY
–50
kSVR – Supply Voltage Rejection Ratio – dB
VDD = 15 V
RL = 8 Ω
–60
C(Bypass) = 1 µF
C(Bypass) = 470 nF
–70
C(Bypass) = 100 nF
–80
–90
20
100
1k
VDD = 12 V
RL = 8 Ω
–60
C(Bypass) = 470 nF
C(Bypass) = 100 nF
–70
C(Bypass) = 1 µF
–80
–90
20
10k
100
f – Frequency – Hz
Figure 15
10k
Figure 16
GAIN and PHASE
vs
FREQUENCY
SUPPLY VOLTAGE REJECTION RATIO
vs
FREQUENCY
30
14
–50
VCC = 8 V
RL = 8 Ω
12
C(Bypass) = 1 µF
–60
20
Gain
10
0
10
–10
C(Bypass) = 470 nF
C(Bypass) = 100 nF
–70
Gain – dB
kSVR – Supply Voltage Rejection Ratio – dB
1k
f – Frequency – Hz
8
–20
Phase
6
–30
Phase – °
kSVR – Supply Voltage Rejection Ratio – dB
–50
–40
4
–50
–80
2
–90
20
100
1k
0
10
10k
–60
VCC = 8 V
RL = 8 Ω
Gain = 12 dB
100
–70
1k
10k
–80
100k
f – Frequency – Hz
f – Frequency – Hz
Figure 18
Figure 17
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9
TPA3000D1
SLOS379A – SEPTEMBER 2001 – REVISED JANUARY 2002
TYPICAL CHARACTERISTICS
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
6
VCC = 8 V to 18 V
RL = 8 Ω
5
–41
VIO – Input Offset Voltage – mV
CMRR – Common-Mode Rejection Ratio – dB
–40
–42
–43
–44
–45
VCC = 18 V
4
3
2
1
0
–1
–2
–3
–46
20
100
1k
–4
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
10k
f – Frequency – Hz
VIC – Common-Mode Input Voltage – V
Figure 19
Figure 20
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
6
5
4
VIO – Input Offset Voltage – mV
VIO – Input Offset Voltage – mV
5
6
VCC = 12 V
3
2
1
0
–1
–2
4
3
2
1
0
–1
–2
–3
–3
–4
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
–4
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VIC – Common-Mode Input Voltage – V
VIC – Common-Mode Input Voltage – V
Figure 21
10
VCC = 8 V
Figure 22
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TPA3000D1
SLOS379A – SEPTEMBER 2001 – REVISED JANUARY 2002
APPLICATION INFORMATION
eliminating the output filter with the TPA3000D1
This section focuses on how the user can eliminate the output filter with the TPA3000D1.
effect on audio
The class-D amplifier outputs a pulse-width modulated (PWM) square wave, which is the sum of the switching
waveform and the amplified input audio signal. The human ear acts as a band-pass filter such that only the
frequencies between approximately 20 Hz and 20 kHz are passed. The switching frequency components are
much greater than 20 kHz, so the only signal heard is the amplified input audio signal.
traditional class-D modulation scheme
The traditional class-D modulation scheme, which is used in the TPA032D0x family, has a differential output
where each output is 180 degrees out of phase and changes from ground to the supply voltage, VCC. Therefore,
the differential prefiltered output varies between positive and negative VCC, where filtered 50% duty cycle yields
0 V across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown
in Figure 23. Note that even at an average of 0 V across the load (50% duty cycle), the current to the load is
high, causing high loss, thus causing a high supply current.
OUTP
OUTN
+12 V
Differential Voltage
Across Load
0V
–12 V
Current
Figure 23. Traditional Class-D Modulation Scheme’s Output Voltage and
Current Waveforms Into an Inductive Load With No Input
TPA3000D1 modulation scheme
The TPA3000D1 uses a modulation scheme that still has each output switching from 0 to the supply voltage.
However, OUTP and OUTN are now in phase with each other with no input. The duty cycle of OUTP is greater
than 50% and OUTN is less than 50% for positive output voltages. The duty cycle of OUTP is less than 50%
and OUTN is greater than 50% for negative output voltages. The voltage across the load sits at 0 V throughout
most of the switching period, greatly reducing the switching current, which reduces any I2R losses in the load.
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11
TPA3000D1
SLOS379A – SEPTEMBER 2001 – REVISED JANUARY 2002
APPLICATION INFORMATION
TPA3000D1 modulation scheme (continued)
OUTP
OUTN
Differential
Voltage
Across
Load
Output = 0 V
+12 V
0V
–12 V
Current
OUTP
OUTN
Differential
Voltage
Output > 0 V
+12 V
0V
Across
Load
–12 V
Current
Figure 24. The TPA3000D1 Output Voltage and Current Waveforms Into an Inductive Load
efficiency: filter required with the traditional class-D modulation scheme
The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform
results in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple
current is large for the traditional modulation scheme, because the ripple current is proportional to voltage
multiplied by the time at that voltage. The differential voltage swing is 2 × VCC, and the time at each voltage is
half the period for the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from
each half cycle for the next half cycle, while any resistance causes power dissipation. The speaker is both
resistive and reactive, whereas an LC filter is almost purely reactive.
The TPA3000D1 modulation scheme has very little loss in the load without a filter because the pulses are very
short and the change in voltage is VCC instead of 2 × VCC. As the output power increases, the pulses widen,
making the ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for
most applications the filter is not needed.
An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow
through the filter instead of the load. The filter has less resistance than the speaker, which results in less power
dissipation, therefore increasing efficiency.
12
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TPA3000D1
SLOS379A – SEPTEMBER 2001 – REVISED JANUARY 2002
APPLICATION INFORMATION
effects of applying a square wave into a speaker
Audio specialists have advised for years not to apply a square wave to speakers. If the amplitude of the
waveform is high enough and the frequency of the square wave is within the bandwidth of the speaker, the
square wave could cause the voice coil to jump out of the air gap and/or scar the voice coil. A 250-kHz switching
frequency, however, does not significantly move the voice coil, as the cone movement is proportional to 1/f2 for
frequencies beyond the audio band.
Damage may occur if the voice coil cannot handle the additional heat generated from the high-frequency
switching current. The amount of power dissipated in the speaker may be estimated by first considering the
overall efficiency of the system. If the on-resistance (rds(on)) of the output transistors is considered to cause the
dominant loss in the system, then the maximum theoretical efficiency for the TPA3000D1 with an 8-Ω load is
as follows:
ǒ
Efficiency (theoretical, %) + R ń R ) r
L
L
ds(on)
Ǔ
100% + 8ń(8 ) 0.4)
100% + 95.24%
(1)
The maximum measured output power is approximately 17 W with an 18-V power supply. The total theoretical
power supplied (P(total)) for this worst-case condition would therefore be as follows:
P
(total)
+ P ńEfficiency + 17 W ń 0.9524 + 17.85 W
O
(2)
The efficiency measured in the lab using an 8-Ω speaker was 89%. The power not accounted for as dissipated
across the rds(on) may be calculated by simply subtracting the theoretical power from the measured power:
Other losses + P
(total)
(measured) * P
(total)
(theoretical) + 19.1 * 17.85 + 1.25 W
(3)
The quiescent supply current at 18 V is measured to be 9.8 mA. It can be assumed that the quiescent current
encapsulates all remaining losses in the device, i.e., biasing and switching losses. It may be assumed that any
remaining power is dissipated in the speaker and is calculated as follows:
P
(dis)
+ 1.25 W * (18 V
9.8 mA) + 1.07 W
(4)
Note that these calculations are for the worst-case condition of 17 W delivered to the speaker. Since the 1.07 W
is only 6.3% of the power delivered to the speaker, it may be concluded that the amount of power actually
dissipated in the speaker is relatively insignificant. Furthermore, this power dissipated is well within the
specifications of most loudspeaker drivers in a system, as the power rating is typically selected to handle the
power generated from a clipping waveform.
when to use an output filter
Design the TPA3000D1 without the filter if the traces from amplifier to speaker are short. Powered speakers,
where the speaker is in the same enclosure as the amplifier, is a typical application for class-D without a filter.
A ferrite bead filter may be used if the design is failing radiated emissions without a filter, or if a frequency
sensitive circuit is operating higher than 1 MHz. The ferrite filter reduces EMI around 1 MHz and higher (FCC
and CE only test radiated emissions greater than 30 MHz). When selecting a ferrite bead, choose one with high
impedance at high frequencies, but very low impedance at low frequencies.
Use a LC output filter if there are low frequency (<1 MHz) EMI sensitive circuits and/or there are long wires from
the amplifier to the speaker.
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13
TPA3000D1
SLOS379A – SEPTEMBER 2001 – REVISED JANUARY 2002
APPLICATION INFORMATION
when to use an output filter (continued)
15 µH
OUTP
0.22 µF
15 µH
1 µF
OUTN
0.22 µF
Figure 25. Typical LC Output Filter, Cutoff Frequency of 41 kHz
Ferrite
Chip Bead
OUTP
1 nF
Ferrite
Chip Bead
OUTN
1 nF
Figure 26. Typical Ferrite Chip Bead Filter (Chip bead example: Fair-Rite 2512067007Y3)
gain setting via GAIN0 and GAIN1 inputs
The gain of the TPA3000D1 is set by two input terminals, GAIN0 and GAIN1.
The gains listed in Table 1 are realized by changing the taps on the input resistors inside the amplifier. This
causes the input impedance (Zi) to be dependent on the gain setting. The actual gain settings are controlled
by ratios of resistors, so the actual gain distribution from part-to-part is quite good. However, the input
impedance may shift by 30% due to shifts in the actual resistance of the input resistors.
For design purposes, the input network (discussed in the next section) should be designed assuming an input
impedance of 23 kΩ, which is the absolute minimum input impedance of the TPA3000D1. At the lower gain
settings, the input impedance could increase as high as 313 kΩ.
Table 1. Gain Settings
14
AMPLIFIER GAIN
(dB)
INPUT IMPEDANCE
(kΩ)
TYP
TYP
12
241
1
18
168
0
23.5
104
1
36
33
GAIN0
GAIN1
0
0
0
1
1
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TPA3000D1
SLOS379A – SEPTEMBER 2001 – REVISED JANUARY 2002
APPLICATION INFORMATION
input resistance
Each gain setting is achieved by varying the input resistance of the amplifier, which can range from its smallest
value to over six times that value. As a result, if a single capacitor is used in the input high-pass filter, the –3 dB
or cutoff frequency also changes by over six times.
Zf
Ci
Input
Signal
Zi
IN
The –3-dB frequency can be calculated using equation 5.
f+
1
2p Z iC i
(5)
input capacitor, Ci
In the typical application an input capacitor (Ci) is required to allow the amplifier to bias the input signal to the
proper dc level for optimum operation. In this case, Ci and the input impedance of the amplifier (Zi) form a
high-pass filter with the corner frequency determined in equation 6.
–3 dB
fc +
(6)
1
2 p Zi Ci
fc
The value of Ci is important, as it directly affects the bass (low frequency) performance of the circuit. Consider
the example where Zi is 241 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 6
is reconfigured as equation 7.
Ci +
1
2p Z i f c
(7)
In this example, Ci is 33 nF, so one would likely choose a value of 0.1 µF as this value is commonly used. If the
gain is known and will be constant, use Zi from Table 1 to calculate Ci. A further consideration for this capacitor
is the leakage path from the input source through the input network (Ci) and the feedback network to the load.
This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom,
especially in high gain applications. For this reason a low-leakage tantalum or ceramic capacitor is the best
choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input
in most applications as the dc level there is held at 2.5 V, which is likely higher than the source dc level. Note
that it is important to confirm the capacitor polarity in the application.
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15
TPA3000D1
SLOS379A – SEPTEMBER 2001 – REVISED JANUARY 2002
APPLICATION INFORMATION
power supply decoupling, CS
The TPA3000D1 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling
to ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also
prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is
achieved by using two capacitors of different types that target different types of noise on the power supply leads.
For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance
(ESR) ceramic capacitor, typically 0.1 µF placed as close as possible to the device VCC lead works best. For
filtering lower-frequency noise signals, a larger aluminum electrolytic capacitor of 10 µF or greater placed near
the audio power amplifier is recommended.
BSN and BSP capacitors
The full H-bridge output stage uses only NMOS transistors. It therefore requires bootstrap capacitors for the
high side of each output to turn on correctly. A 10-nF ceramic capacitor, rated for at least 25 V, must be connected
from each output to its corresponding bootstrap input. Specifically, one 10-nF capacitor must be connected from
OUTP to BSP, and one 10-nF capacitor must be connected from OUTN to BSN. (See the evaluation circuit
diagram at the end of this data sheet.)
VCLAMP capacitors
To ensure that the maximum gate-to-source voltage for the NMOS output transistors is not exceeded, an internal
regulator clamps the gate voltage. A 0.1-µF capacitor must be connected from VCLAMP (pin 7) to ground and
must be rated for at least 25 V. The voltage at VCLAMP (pin 7) varies with VCC and may not be used for powering
any other circuitry.
midrail bypass capacitor, CBYPASS
The midrail bypass capacitor (CBYPASS) is the most critical capacitor and serves several important functions.
During start-up or recovery from shutdown mode, CBYPASS determines the rate at which the amplifier starts up.
The second function is to reduce noise produced by the power supply caused by coupling into the output drive
signal. This noise is from the midrail generation circuit internal to the amplifier, which appears as degraded
PSRR and THD+N.
Bypass capacitor (CBYPASS) values of 0.47-µF to 1-µF ceramic or tantalum low-ESR capacitors are
recommended for the best THD noise, and depop performance.
VREF decoupling capacitor
The VREF terminal (pin 23) is the output of an internally-generated 5-V supply, used for the oscillator and gain
setting logic. It requires a 0.1-µF to 1-µF capacitor to ground to keep the regulator stable. The regulator may
not be used to power any additional circuitry.
differential input
The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel.
To use the TPA3000D1 EVM with a differential source, connect the positive lead of the audio source to the INP
input and the negative lead from the audio source to the INN input. To use the TPA3000D1 with a single-ended
source, ac ground the INN input through a capacitor and apply the audio single to the input. In a single-ended
input application, the INN input should be ac-grounded at the audio source instead of at the device input for best
noise performance.
16
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TPA3000D1
SLOS379A – SEPTEMBER 2001 – REVISED JANUARY 2002
,APPLICATION INFORMATION
SHUTDOWN operation
The TPA3000D1 employs a shutdown mode of operation designed to reduce supply current (ICC) to the absolute
minimum level during periods of nonuse for battery-power conservation. The SHUTDOWN input terminal
should be held high during normal operation when the amplifier is in use. Pulling SHUTDOWN low causes the
outputs to mute and the amplifier to enter a low-current state, ICC(SD) = 1 µA. SHUTDOWN should never be left
unconnected, because amplifier operation would be unpredictable.
Ideally, the device should be held in shutdown when the system powers up and brought out of shutdown once
any digital circuitry has settled. However, if SHUTDOWN is to be left unused or if the device is to be powered
up with SHUTDOWN held high, the circuit below should be used.
VCC (or SHUTDOWN Control Signal, TTL Compatible)
R(SD)
120 kΩ
SHUTDOWN
Pin 23
CSD
0.1 µF
The values for RSD and CSD should be chosen for a time constant (τ = RSDCSD) of at least 10 ms for proper
operation. The maximum output current of the SHUTDOWN control signal source must not be exceeded.
using low-ESR capacitors
Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal)
capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this
resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this
resistance the more the real capacitor behaves like an ideal capacitor.
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17
MECHANICAL DATA
MHTS001D – JANUARY 1995 – REVISED MAY 1999
MECHANICAL DATA
PWP (R-PDSO-G**)
PowerPAD PLASTIC SMALL-OUTLINE
20 PINS SHOWN
0,30
0,19
0,65
20
0,10 M
11
Thermal Pad
(See Note D)
4,50
4,30
0,15 NOM
6,60
6,20
Gage Plane
1
10
0,25
A
0°–ā8°
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
14
16
20
24
28
A MAX
5,10
5,10
6,60
7,90
9,80
A MIN
4,90
4,90
6,40
7,70
9,60
DIM
4073225/F 10/98
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusions.
The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.
This pad is electrically and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-153
PowerPAD is a trademark of Texas Instruments.
18
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