INTEGRATED CIRCUITS DATA SHEET TDA8041H Quadrature demodulator controller Preliminary specification File under Integrated Circuits, IC03 Philips Semiconductors November 1994 Philips Semiconductors Preliminary specification Quadrature demodulator controller TDA8041H FEATURES APPLICATIONS • Generates all control signals for Quadrature Phase-Shift Keying (QPSK) and Binary Phase-Shift Keying (BPSK) demodulation • Demodulation of BPSK and QPSK modulated signals in satellite and telephone applications. • Can be used in applications with low Eb/No and high symbol rate (up to 30 × 106 symbols/s) • Digital I and Q outputs (3 bits) for soft decision within error correction • Two matched analog-to-digital converters to quantize the I and Q signals • A digital detector for each control loop to generate the required control signals • Digital-to-analog converters and operational amplifiers to allow high flexibility for loop time constants • Special input stage to interface with the voltage controlled crystal oscillator • Positive 5 V supply voltage. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDD(A) supply voltage for operational amplifiers (pin 5) 4.75 5.0 5.25 V VDDA(C) analog supply voltage for converters (pin 20) 4.75 5.0 5.25 V VDD(I/O) supply voltage for digital inputs/outputs (pin 30) 4.75 5.0 5.25 V VDDD supply voltage for digital section (pin 35) 4.75 5.0 5.25 V VDD(C) supply voltage for digital part of ADC and DAC (pin 42) 4.75 5.0 5.25 V IDD(tot) total supply current − 30 − mA VDD = 5 V VIQ I and Q input voltage − 1.0 − V Rsym symbol rate − − 30 × 106 symbols/s IO(DAC) DAC output current −100 − +100 mA ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA8041H QFP44(1) DESCRIPTION plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm; high stand-off height VERSION SOT307-2 Note 1. When using reflow soldering it is recommended that the Drypack instructions in the “Quality Reference Handbook” (order number 9398 510 63011) are followed. November 1994 2 I ana 18 ADC A 4 4 LOGIC data LCK LOCK DETECTOR I (3..0) LCKTC LCKO 1 2 I LCK 4 4 DAC CLK1 VDD 3 Vref(mid) 15 R4 V ref(pos) CARRIER data CAR RECOVERY 7 CLK1 8 TDA8041H R2 Vref(neg) 3 mode control AFC1 AFC2 TEST 39 V th 9 38 data AFC2 AFC2 12 data AGC AGC 40 I AGC 2 DAC 13 ADC A 4 4 LOGIC CLOCK data CLK Q (3..0) RECOVERY Vref(mid) 22 DAC 23 CLK1 SWPO Vref(mid) ADC 3 AGCTC AGCO CLKRTC CLKRO CLKIX CLK1 CLK2 25 DAC 2 CLKSR CLK1 OPAMP 26 to 28 6 11 17 20 24 29 30 34 35 42 43 V SS(A) V SSA(C) V SS1 V DD(I/O) V DDD V SS(C) V DD(A) V SS2 V DDA(C) V SS(I/O) V SSD V DD(C) Fig.1 Block diagram. MBE167 TDA8041H QDO0 to QDO2 5 Preliminary specification I bias I bias BIAS GENERATOR I bias 21 I CLK 5 CLK2 41 SWEEP CLK1 37 Q ana CARO AFC2O CLK1 I bias 10 DAC 36 19 CARTC 14 I AFC2 5 VSS LCKTH Vref(mid) LOGIC R1 BQN 16 DAC R3 V ref(mid) I CAR 4 LCKIO Philips Semiconductors CLK2 44 Quadrature demodulator controller 3 LCKDAC BLOCK DIAGRAM handbook, full pagewidth November 1994 IDO0 to IDO2 31 to 33 Philips Semiconductors Preliminary specification Quadrature demodulator controller TDA8041H PINNING SYMBOL PIN DESCRIPTION SYMBOL PIN DESCRIPTION LCKTC 1 carrier lock time constant VSS1 24 negative supply voltage 1 LCKO 2 carrier lock output CLKSR 25 clock output at symbol rate LCKTH 3 carrier lock threshold voltage QDO2 26 Q digital output (bit 2) LCKIO 4 carrier lock indicator output QDO1 27 Q digital output (bit 1) VDD(A) 5 supply voltage for operational amplifiers QDO0 28 Q digital output (bit 0) VSS(I/O) 29 negative supply voltage for digital inputs/outputs VSS(A) 6 negative supply voltage for operational amplifiers VDD(I/O) 30 Vref(pos) 7 positive reference voltage for converters supply voltage for digital inputs/outputs IDO2 31 I digital output (bit 2) Vref(mid) 8 middle reference voltage for converters IDO1 32 I digital output (bit 1) Vref(neg) 9 negative reference voltage for converters IDO0 33 I digital output (bit 0) VSSD 34 AFC2O 10 AFC 2 output negative supply voltage for digital section VSS2 11 negative supply voltage 2 VDDD 35 supply voltage for digital section AGCTC 12 automatic gain control time constant AFC1 36 AFC control switch 1 (1 = on; 0 = off) AGCO 13 automatic gain control output AFC2 37 AFC control switch 2 (1 = on; 0 = off) SWPO 14 sweep current output BQN 38 CARTC 15 carrier recovery time constant BPSK/QPSK control switch (1 = BPSK; 0 = QPSK) CARO 16 carrier recovery output SWEEP 39 VSSA(C) 17 analog negative supply voltage for converters sweep control switch (1 = on; 0 = off) TEST 40 test control switch (1 = on; 0 = off) Iana 18 analog input I Ibias 41 input bias current for analog blocks Qana 19 analog input Q VDD(C) 42 VDDA(C) 20 analog supply voltage for converters supply voltage for digital part of ADC and DAC VSS(C) 43 negative supply voltage for digital part of ADC and DAC LCKDAC 44 carrier lock DAC output CLKRTC 21 clock recovery time constant CLKRO 22 clock recovery output CLKIX 23 clock input from crystal circuit (at double symbol rate) November 1994 4 Philips Semiconductors Preliminary specification 34 VSSD LCKTC 1 33 IDO0 LCKO 2 32 IDO1 LCKTH 3 31 IDO2 LCKIO 4 30 VDD(I/O) V DD(A) 5 29 VSS(I/O) V SS(A) 6 Vref(pos) 7 27 QDO1 Vref(mid) 8 26 QDO2 Vref(neg) TDA8041H 28 QDO0 5 CLKRO 22 CLKRTC 21 VDDA(C) 20 Q ana 19 I ana 18 23 CLKIX CARO 16 11 VSSA(C) 17 V SS2 CARTC 15 24 VSS1 AGCO 13 AFC2O SWPO 14 25 CLKSR AGCTC 12 9 10 Fig.2 Pin configuration. November 1994 35 VDDD 36 AFC1 37 AFC2 38 BQN 39 SWEEP TDA8041H 40 TEST 41 I bias 42 VDD(C) handbook, full pagewidth 43 VSS(C) 44 LCKDAC Quadrature demodulator controller MBE166 Philips Semiconductors Preliminary specification Quadrature demodulator controller TDA8041H GENERAL DESCRIPTION FUNCTIONAL DESCRIPTION The quadrature demodulator controller TDA8041H, generates all control signals required for demodulation of BPSK and QPSK modulated signals. This device is specially designed to be used in conjunction with the quadrature demodulator IC, TDA8040T. The TDA8041H has a 3-bit-wide digital I and Q output for soft error correction. These 3-bit outputs represent the main symbols only. The relationship between the 4-bits ADC signals and the 3-bit output signals is illustrated in Fig.3. The quadrature demodulator controller generates the following signals: • Symbol clock recovery control signal; this signal locks the VCXO to the received symbol clock. The clock recovery algorithm used in this device operates independently from the other loops. • Carrier recovery control signal; depending on the selected mode (BPSK or QPSK), this signal will adjust the phase of the I and Q input signal. This adjustment will be such that the constellation points are as defined in Fig.4. • Frequency control signals (AFC1 and AFC2); to serve a broad range of applications, two different AFC detectors and a sweep function are built-in: – AFC1: this is a robust detector which forces the offset frequency in the I and Q branch to zero. This detector can handle frequency offset up to 1/8 × symbol rate. – AFC2: this detector can handle frequency offsets greater than 1/8 × symbol frequency. However this AFC algorithm will bring the offset frequency only close to zero. – Sweep: this signal generates a triangular current output which can tune a VCO over its complete frequency range. Sweeping must be switched off as soon as the logical output of the lock detect function becomes positive. The value of the sweep current is set by an external resistor. Fig.3 • Amplitude control signals (AGC); this signal adjusts a variable gain amplifier so that the amplitude of the I and Q signals is in accordance with the specified constellation points of Fig.4. • Lock detect signal; this signal is related to the Eb/No of the incoming I and Q signals. This lock detect signal can be used for two purposes: – Lock detection by comparing the lock detect signal with an external set reference voltage, one can obtain a logical signal indicating lock detect. – The relationship between Eb/No can be used to display the Eb/No for antenna adjustment. November 1994 6 I and Q output levels for soft error decision FEC. Philips Semiconductors Preliminary specification Quadrature demodulator controller TDA8041H BBBBBBB BBBBBBB BBBBBBB BBBBBBB BBBBBBB BBBBBBB BBBBBBB BBBBBBB BBBBBBBBBBBBB BBBBBBBBBBBBB BBBBBB BBBBBBB BBBBBBBBBBBBB BBBBBBBBBBBBB BBBBBB Fig.4 Constellation points. LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDD(A) supply voltage for operational amplifiers (pin 5) −0.5 +6.5 V VDDA(C) analog supply voltage for converters (pin 20) −0.5 +6.5 V VDD(I/O) supply voltage for digital inputs/outputs (pin 30) −0.5 +6.5 V VDDD supply voltage for digital section (pin 35) −0.5 +6.5 V VDD(C) supply voltage for digital part of ADC and DAC (pin 42) −0.5 +6.5 V Vn(max) maximum voltage on all pins 0 VDD V Ptot total power dissipation − 500 mW Tstg storage temperature −55 +150 °C Tj junction temperature − +150 °C Tamb operating ambient temperature 0 +70 °C Tamb = 70 °C THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient in free air VALUE UNIT 75 K/W HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. November 1994 7 Philips Semiconductors Preliminary specification Quadrature demodulator controller TDA8041H CHARACTERISTICS VDD = 4.75 to 5.25 V; Rsym = 30 × 106 symbols/s; Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Digital outputs (pins 26 to 28 and 31 to 33) 0 − 0.1VDD see Fig.6 0.9VDD − VDD V see Fig.6 th − 22 ns hold time 8 − td ns VIL LOW level input voltage 0 − 0.3VDD V VIH HIGH level input voltage 0.7VDD − VDD V CI input capacitance − − 10 pF − 0.1VDD V VOL LOW level output voltage VOH HIGH level output voltage td delay time th V Digital inputs Clock output (pins 22 and 25); see Fig.5 VOL LOW level output voltage 0 VOH HIGH level output voltage 0.9VDD − VDD V Tcy cycle time 33 − − ns tW pulse width duty cycle 40/60 13.2 − − ns tr rise time CL = 30 pF − − 6 ns tf fall time CL = 30 pF − − 6 ns Clock input (pin 23) Rsource source resistance − − 50 Ω fs sampling frequency − − 60 MHz − − 30 × 106 symbols/s Analog inputs (pins 18 and 19) Rsym symbol rate Vref(pos) positive reference voltage IO = 0 − 0.48VDD − V Vref(mid) middle reference voltage IO = 0 − 0.38VDD − V Vref(neg) negative reference voltage IO = 0 − 0.28VDD − V IL load current at pin 8 −5 − +5 mA Vi(I,Q) I and Q input voltage 0 − VDD V VI,Q(op) I and Q operating voltage 0.28VDD − 0.48VDD V RI input resistance 50 − − kΩ CI input capacitance − − 20 pF Ibias input bias current RL = 100 kΩ − −37 − mA note 1 DAC outputs (pins 10, 12, 15 and 21) Io(av) average output current VDAC = Vref(mid); note 2 − 100 − mA DIo matching of positive and negative output currents VDAC = Vref(mid); note 2 −7 − +7 % Io zero output current −25 − +25 nA November 1994 8 Philips Semiconductors Preliminary specification Quadrature demodulator controller SYMBOL PARAMETER TDA8041H CONDITIONS MIN. TYP. MAX. UNIT Sweep current (pin 14) VOH HIGH level output voltage − 2Vref(mid) − V VOL LOW level output voltage − 0 − V ZO output impedance SWEEP = 1 − 2 − kΩ SWEEP = 0 10 − − MΩ VCARO(min) LOW switching level 0.1VDD − 0.2VDD V VCARO(max) HIGH switching level 0.8VDD − 0.9VDD V Vo output voltage 0.1VDD − 0.9VDD V Gv open loop gain −. 60 − dB GB gain bandwidth − 1 − MHz RL load resistance 5 − − kΩ Loop amplifiers Notes 1. Vref(mid) is usually open-circuit. However, this pin may also be used as a reference output for an external buffer. 2. ( I pos + I neg ) ( I pos – I neg ) I o ( av ) = -------------------------------; D lo = 100 × --------------------------------( I pos – I neg ) 2 November 1994 9 Philips Semiconductors Preliminary specification Quadrature demodulator controller TDA8041H Fig.5 Timing of CLKO. Fig.6 Timing definition of digital outputs. November 1994 10 100 nF lock indicator 5 5V 100 nF BQN 36 35 34 VSSD VDDD 37 AF C1 38 AF C2 39 SWEEP 40 TEST 41 I bias VDD(C) 42 IDO2 VDD(I/O) VSS(I/O) V DD(A) 6 TDA8041H QDO0 7 QDO2 Vref(mid) 9 CLKSR 12 100 Ω 13 820 kΩ 14 15 270 pF 17 1 kΩ 19 CLKRTC VDDA(C) Qana 18 10 nF 100 nF AGC voltage 16 Iana AGCTC CARO V SS2 VSSA(C) AFC2O 11 CARTC 11 Vref(neg) 10 SWPO 100 nF QDO1 Vref(pos) 8 AGCO 100 nF 20 100 nF 330 pF VSS1 CLKIX CLKRO 21 82 kΩ 330 pF 33 IDO0 IDO1 V SS(A) 100 nF AFC2 current 43 VSS(C) 8.2 nF 44 22 kΩ LCKDAC 1 LCKTC 2 LCKO 3 LCKTH 4 LCKIO 100 nF 100 kΩ 10 nF 32 31 I0 I1 I2 30 29 28 27 26 25 5V 100 nF Q0 Q1 Q2 clock output 24 23 5V 22 100 pF Philips Semiconductors 22 kΩ 33 kΩ 33 nF 5V Quadrature demodulator controller 10 kΩ 100 nF APPLICATION INFORMATION 10 kΩ 5V 56 kΩ 5V dbook, full pagewidth November 1994 5V 10 Ω 27 kΩ 4.7 kΩ 10 nF 50 Ω 49.7 MHz BFS17A carrier voltage 5V BB620 10 kΩ 56 pF 0Ω 100 pF 390 nH Q from TDA8040 MBE168 Fig.7 Application diagram. 560 Ω 10 nF TDA8041H 56 pF Preliminary specification I from TDA8040 Philips Semiconductors Preliminary specification Quadrature demodulator controller TDA8041H PACKAGE OUTLINE seating plane S 0.15 S 12.9 12.3 44 1.2 0.8 (4x) 34 B 33 1 pin 1 index 0.15 M B 0.8 11 23 12 10.1 9.9 12.9 12.3 0.40 0.20 22 0.8 0.40 0.20 1.2 0.8 (4x) 0.15 M A 10.1 9.9 X A 0.85 0.75 1.85 1.65 0.50 0.20 MBC864 - 2 0.25 0.14 detail X 0.95 0.55 0 to 10 2.35 1.85 o Dimensions in mm. Fig.8 Plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm; high stand-off height (QFP44; SOT307-1). November 1994 12 Philips Semiconductors Preliminary specification Quadrature demodulator controller TDA8041H applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. SOLDERING Plastic quad flat-packs Several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. Dwell times vary between 50 and 300 s according to method. Typical reflow temperatures range from 215 to 250 °C. BY WAVE During placement and before soldering, the component must be fixed with a droplet of adhesive. After curing the adhesive, the component can be soldered. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 min at 45 °C. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 °C within 6 s. Typical dwell time is 4 s at 250 °C. REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING IRON OR PULSE-HEATED SOLDER TOOL) Fix the component by first soldering two, diagonally opposite, end pins. Apply the heating tool to the flat part of the pin only. Contact time must be limited to 10 s at up to 300 °C. When using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 °C. (Pulse-heated soldering is not recommended for SO packages.) A modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. Using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. For pulse-heated solder tool (resistance) soldering of VSO packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement. BY SOLDER PASTE REFLOW Reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. November 1994 13 Philips Semiconductors Preliminary specification Quadrature demodulator controller TDA8041H NOTES November 1994 14 Philips Semiconductors Preliminary specification Quadrature demodulator controller TDA8041H NOTES November 1994 15 Philips Semiconductors – a worldwide company Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. (01)60 101-1211 Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Tel. (31)40 783 749, Fax. (31)40 788 399 Brazil: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SÃO PAULO-SP, Brazil. P.O. Box 7383 (01064-970). Tel. (011)821-2333, Fax. (011)829-1849 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS: Tel. (800) 234-7381, Fax. (708) 296-8556 Chile: Av. Santa Maria 0760, SANTIAGO, Tel. (02)773 816, Fax. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 513161/1500/01/pp16 Document order number: Date of release: November 1994 9397 743 20011