PHILIPS SAA7707H

INTEGRATED CIRCUITS
DATA SHEET
SAA7707H
Car radio Digital Signal Processor
(CDSP)
Preliminary specification
Supersedes data of 1996 May 22
File under Integrated Circuits, IC01
1997 May 30
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
CONTENTS
SAA7707H
9.9
9.10
9.11
Clock circuit and oscillator
Crystal oscillator supply
External control pins
10
I2S-BUS DESCRIPTION
10.1
10.2
10.3
1
FEATURES
1.1
1.2
Hardware
Software
2
APPLICATIONS
3
GENERAL DESCRIPTION
4
QUICK REFERENCE DATA
5
ORDERING INFORMATION
6
BLOCK DIAGRAM
7
PINNING
10.5
8
FUNCTIONAL DESCRIPTION
8.1
8.2
8.3
10.6
10.7
10.8
10.9
10.10
10.11
10.12
11
LIMITING VALUES
12
THERMAL CHARACTERISTICS
13
DC CHARACTERISTICS
14
AC CHARACTERISTICS
15
I2C-BUS CONTROL AND COMMANDS
15.1
15.2
15.3
15.4
15.5
15.6
Characteristics of the I2C-bus
Bit transfer
START and STOP conditions
Data transfer
Acknowledge
I2C-bus format
16
SOFTWARE DESCRIPTION
17
APPLICATION INFORMATION
18
PACKAGE OUTLINE
19
SOLDERING
8.19
8.20
8.21
Signal path for level information
Level ADC switch mode integrator (pin CINT)
Internal ground reference for the level ADC
(pin VDACNL)
Common mode reference voltage for RDS
ADC, ADC level and buffers (pin VrefRDS)
Signal path for audio/MPX and stereo decoder
Mono/stereo switching
The automatic lock system
Input sensitivity for FM
Common mode reference voltage for MPX
ADC and buffers (pin VrefMPX)
Supply voltages for the switch capacitor DACs
of the FMMPX ADC and FMRDS ADC
(pins VDACNM and VDACPM)
Noise level
TAPE/AUX de-multiplex
Signal-to-noise considerations
Channel separation correction
Input selection switches
Analog inputs supply
Digitally controlled sampling clock (DCS)
Survey of the DCS clock settings in different
modes
Synchronization with the core
Interference absorption circuit
IAC testing
I2C-bus control (SCL and SDA pins)
I2S-bus description
Communication with external digital audio
sources (DCC + CD-WS/CL/Data pins)
Communication with external processors and
other devices (EXWS/CL/EXDAT1 and
EXDAT2)
Relationship between external input and
external output
RDS decoder (RDSCLK and RDSDAT)
Clock and data recovery
Timing of clock and data signals
Buffering of RDS data
Buffer interface
DSP reset
Power supply connection and EMC
9
ANALOG OUTPUTS
19.1
19.2
19.3
19.4
Introduction
Reflow soldering
Wave soldering
Repairing soldered joints
9.1
9.2
9.3
9.4
9.5
9.6
Digital-to-Analog Converters
Upsample filter
Volume control
Power-on mute
Power-off plop suppression
Internal reference buffer amplifier of the DAC
(pin Vref)
Internal DAC current reference
Analog outputs supply
20
DEFINITIONS
21
LIFE SUPPORT APPLICATIONS
22
PURCHASE OF PHILIPS I2C COMPONENTS
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
8.13
8.14
8.15
8.16
8.17
8.18
9.7
9.8
1997 May 30
10.4
2
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
1
1.1
2
FEATURES
APPLICATIONS
• Car radio
Hardware
• Car audio systems.
• Bitstream 3rd-order Sigma-Delta Analog-to-Digital
Converters (ADCs) with anti-aliasing broadband input
filters
3
• Digital-to-Analog Converters (DACs)with four times
oversampling and noise shaping
GENERAL DESCRIPTION
The SAA7707H performs all the signal functions in front of
the power amplifiers and behind the AM and FMMPX
demodulation of a car radio or the tape input.
These functions are:
• Digital stereo decoder
• Improved digital Interference Absorption Circuit (IAC)
• RDS processing with optional 16-bit buffer via separate
channel (two-tuner radio possible)
• Interference absorption
• Auxiliary analog CD input (CD-walkman, speech,
economic CD-changer, etc.)
• RDS decoding
• Stereo decoding
• FM and AM weak signal processing (soft mute, sliding
stereo, etc.)
• Two separate full I2S-bus CD and DCC high
performance interfaces
• Dolby-B tape noise reduction
• Expandable with additional Digital Signal Processors
(DSPs) for sophisticated features through an I2S-bus
gateway
• The audio controls (volume, balance, fader, tone and
dynamics compression).
Some functions have been implemented in hardware
(stereo decoder, RDS decoder and IAC) and are not freely
programmable. Digital audio signals from external sources
with I2S-bus formats are accepted. There are four
independent analog output channels. This enables, in
special system configurations, separate tone and
equalization control for front and rear speakers.
• Audio output short-circuit protected
• I2C-bus controlled
• Analog tape input
• Operating ambient temperature from −40 to +85 °C.
1.2
SAA7707H
Software
The CDSP contains a basic program that enables a set
with:
• Improved FM weak signal processing
• Integrated 19 kHz MPX filter and de-emphasis
• AM/FM reception
• Electronic adjustments: FM/AM level, FM channel
separation and Dolby level
• Sophisticated FM weak signal functions
• Baseband audio processing (treble, bass, balance,
fader and volume)
• Music Search detection for Tape (MSS)
• Dynamic loudness or bass boost
• CD play with compressor function
• Stereo one-band parametric equalizer
• Separate bass and treble tone control and fader/balance
control.
• Dolby-B tape noise reduction system
• Audio level meter for an automatic leveller
(in combination with microcontroller)
For high-end sets with special and more sophisticated
features, an additional Digital Signal Processor (DSP) can
be connected. Examples of such features are:
• Tape equalization (DCC analog playback)
• Music Search detection for Tape (MSS)
• Noise-dependent volume control
• Pause detection for RDS updates
• 10-band graphic equalizer
• Dolby-B tape noise reduction
• Audio spectrum analyzer on display
• Adjustable dynamics compressor
• Signal delay for concert hall effects.
• CD and DCC de-emphasis processing
• Signal level, noise and multi-path detection for RDS
(I2C-bus command)
• Improved AM reception.
1997 May 30
3
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
4
SAA7707H
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDDD(tot)
total DC supply voltage
all supply pins
4.75
5
5.5
V
IDDD(tot)
total DC supply current
maximum activity of the
DSP; fxtal = 36 MHz
−
160
200
mA
Ptot
total power dissipation
maximum activity of the
DSP; fxtal = 36 MHz
−
0.8
1.1
W
S/N
level ADC signal-to-noise
ratio
RMS value;
unweighted;
B = 0 to 29 kHz;
maximum input
48
54
−
dB
ADC signal-to-noise ratio
not multiplexed;
B = 19 kHz;
Vi = 1 V (RMS)
81
85
−
dB
multiplexed;
unweighted;
B = 19 kHz; 1 V (RMS)
72
76
−
dB
ADC signal-to-noise ratio for
FM-RDS
RMS value; B = 6 kHz; 56
unweighted; fc = 57 kHz
−
−
dB
ViFS
ADC full-scale input voltage
VDDA1 = 4.75 to 5.5 V
1.05VDDA1
1.1VDDA1
1.15VDDA1
V
THD
total harmonic distortion
pins 62 and 71 to 75
fi = 1 kHz;
Vi = 1 V (RMS)
−
−71
−61
dB
−
0.03
0.09
%
maximum conversion input
voltage level pins 62 and
71 to 75 (RMS value)
THD < 1%
1.1
−
−
V
−
18
−
bits
−70
−60
dB
Vimc(rms)
RES
DAC resolution
(THD + N)/S
total harmonic distortion plus RL > 5 kΩ AC;
−
noise-to-signal ratio for DAC Rfb = 2.7 kΩ; fi = 1 kHz;
and operational amplifiers
Rref = 18 kΩ;
VoFS = 2.8 V (p-p);
maximum I2S-bus signal
DR
dynamic range of DAC
fi = 1 kHz; −60 dB;
A-weighted
92
102
−
dB
DS
digital silence of DAC
fi = 20 Hz to 17 kHz;
A-weighted
−
−110
−100
dB
fxtalDSP
crystal frequency DSP part
−
36.86
−
MHz
5
ORDERING INFORMATION
PACKAGE
TYPE
NUMBER
NAME
SAA7707H
QFP80
1997 May 30
DESCRIPTION
plastic quad flat package; 80 leads (lead length 1.95 mm);
body 14 × 29 × 2.8 mm
4
VERSION
SOT318-2
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
FM
AUXR
TAPER
TAPEL
5
AUXL
AMAF
FMMPX
FMRDS
1
67 68
5
54 55 34
22 50 51
41 29 56
70
80
VSSO
VDDD1
MSS/P
MUTE
VDDA
VDDO V
DEEM
SSA
VDDA1
VSSD1
STEREO
49 52 53
44 45 42
43 8
15
69
14 6
5
62
EXCLK
Vref
13
SIGNAL
LEVEL
ADC
4
7
40
20
SAA7707H
Iref(int)
18
3
FIOL
19
72
73
71
75
ANALOG
SOURCE
SELECTOR
FIOR
17
FVOR
ADC
INTERFERENCE
ABSORPTION
CIRCUIT
76
79
FVOL
16
SIGNAL
QUALITY
74
DIGITAL
SIGNAL
PROCESSOR
DIGITAL
STEREO
DECODER
QUADRATURE
DAC
11
DIGITAL
SOURCE
SELECTOR
ADC
RIOL
12
RVOL
9
RIOR
10
RVOR
21
RDS
DECODER
32 33 30
66 65
TSCAN
VDDX
SHTCB
VSSX
RTCB
60
61
DIGITALLY
CONTROLLED
SAMPLING
CRYSTAL
OSCILLATOR
64
63 23 24
25 48 47
46 59 57 58 35 36
RDSDAT
RDSCLK
28 27 37
MBH163
A0
SDA
DSPRESET
SCL
SAA7707H
Fig.1 Block diagram.
EXWS
EXDAT1
EXDAT2
38 39 31 26
Preliminary specification
TEST1
CDWS
DCCWS
EXSCL
DCCDAT
EXDAT
CDCLK
TEST2
DCCCLK
CDDAT
XTALI
VSSD10
POM
I2C-BUS
INTERFACE
XTALO
handbook, full pagewidth
AM
2
VSSD1
VSSD5
VDDD3
VSSD8
VDDD4
VSSD6
VSSD9
VSSD7
VDDD2
VDDD5
Car radio Digital Signal Processor (CDSP)
MPXRDS
77
78
VSSD3
VSSD4
BLOCK DIAGRAM
VDACPM
VDACNM
VrefMPX
VrefRDS
VSSD2
Philips Semiconductors
6
1997 May 30
CINT
VDACNL
VSSG
VSSA1
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
7
SAA7707H
PINNING
SYMBOL
PIN
I/O
DESCRIPTION
VDACNL
1
−
CINT
2
FM
3
I
FM level input; via this pin, the level of the received FM radio signal is fed to the
CDSP, the level information is required to enable correct functioning of the weak
signal behaviour
AM
4
I
AM level input; via this pin, the level of the received AM radio signal is fed to the
CDSP
VSSD1
5
−
ground supply 1 for the DACs digital circuitry
VSSA
6
−
ground supply for the DACs analog circuitry
VDDD1
7
−
positive supply 1 for the DACs digital circuitry
VDDA
8
−
positive supply for the DACs analog circuitry
RIOR
9
O
analog audio current output for rear right speaker
RVOR
10
O
analog audio voltage output for rear right speaker
RIOL
11
O
analog audio current output for rear left speaker
RVOL
12
O
analog audio voltage output for rear left speaker
Iref(int)
13
I
internal reference current source input for the DACs
VSSO
14
−
ground supply for DAC output operational amplifiers
VDDO
15
−
positive supply for DAC output operational amplifiers
FIOR
16
O
analog audio current output for front right speaker
FVOR
17
O
analog audio voltage output for front right speaker
FIOL
18
O
analog audio current output for front left speaker
FVOL
19
O
analog audio voltage output for front left speaker
Vref
20
I
voltage input for the internal reference buffer amplifier of the DAC
POM
21
VSSD2
22
−
ground supply 2 for the digital circuitry
CDCLK
23
I
clock input for CD digital audio source (I2S-bus)
CDWS
24
I
Word Select input for CD digital audio source (I2S-bus)
CDDAT
25
I
left/right data input for CD digital audio source (I2S-bus)
internal ground reference voltage for the level ADC
level ADC switch-mode integrator connector
activates the Power-on mute; timing is determined with an external capacitor
DSPRESET
26
I
input to reset DSP core (active LOW)
EXDAT1
27
I
external input data channel 1 (front) from extra DSP chip (I2S-bus)
EXDAT2
28
I
external input data channel 2 (rear) from extra DSP chip (I2S-bus)
VSSD9
29
−
ground supply 9 for the digital circuitry
TSCAN
30
scan control (active HIGH)
A0
31
I2S-bus selection for slave sub-address
RTCB
32
asynchronous reset test control block (active HIGH)
SHTCB
33
VSSD7
34
−
ground supply 7 for the digital circuitry
EXDAT
35
O
output data for extra external DSP chip (I2S-bus)
EXSCL
36
O
output clock for extra external DSP chip (I2S-bus)
EXWS
37
I/O
word select input/output for extra external DSP chip (I2S-bus)
1997 May 30
shift clock test control block (active HIGH)
6
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SYMBOL
PIN
I/O
SAA7707H
DESCRIPTION
SCL
38
I
SDA
39
I/O
EXCLK
40
I
external reference clock input to generate 4fas and fas synchronization; to be
used if the I2S-bus inputs are not suitable
VSSD8
41
−
ground supply 8 for the digital circuitry
STEREO
42
FM stereo indication (active HIGH)
MSS/P
43
FM pause detector/MSS detector (active HIGH); also for IAC trigger output
MUTE
44
DEEM
45
DCCCLK
46
I
DCC digital audio source clock input (I2S-bus)
DCCWS
47
I
DCC digital audio source Word Select input (I2S-bus)
DCCDAT
48
I
DCC digital audio source left/right data input (I2S-bus)
VDDD3
49
−
positive supply 3 for the digital circuitry
VSSD3
50
−
ground supply 3 for the digital circuitry
VSSD4
51
−
ground supply 4 for the digital circuitry
VDDD4
52
−
positive supply 4 for the digital circuitry
VDDD5
53
−
positive supply 5 for the digital circuitry
VSSD5
54
−
ground supply 5 for the digital circuitry
VSSD6
55
−
ground supply 6 for the digital circuitry
VDDD2
56
−
positive supply 2 for the digital circuitry
TEST1
57
VSSD10
58
TEST2
59
RDSCLK
60
I/O
radio data system bit clock input/output
RDSDAT
61
O
radio data system data output
MPXRDS
62
I
in FM mode, selects between FMMPX and RDSMPX input signal to the MPX
decimation filter
XTALI
63
I
crystal oscillator input; can also be used as forced input in slave mode
XTALO
64
O
crystal oscillator output
VDDX
65
−
positive supply crystal circuitry
VSSX
66
−
ground supply crystal circuitry
VSSG
67
−
ground guards for ADCs
VSSA1
68
−
analog ground supply for ADCs
VDDA1
69
−
analog positive supply for ADCs
VrefMPX
70
I
common mode reference voltage input for MPX ADC and buffers
AUXL
71
I
analog input for auxiliary left signal
AUXR
72
I
analog input for auxiliary right signal
TAPEL
73
I
analog input for tape left signal
I
serial clock input
(I2C-bus)
serial data input/output (I2C-bus)
MUTE input pin (active LOW); only for FM mode
de-emphasis; CD and DCC (active HIGH) (I2S-bus)
test pin 1 (this pin should be left open-circuit)
−
ground supply 10 for the digital circuitry
test pin 2 (this pin should be left open-circuit)
TAPER
74
I
analog input for tape right signal
AMAF
75
I
analog input for AM audio frequency
FMMPX
76
I
analog input for FM multiplex signal
1997 May 30
7
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SYMBOL
SAA7707H
PIN
I/O
VDACPM
77
I
supply voltage for the DACs switch capacitor of the FMMPX ADC and
FMRDS ADC
VDACNM
78
I
ground supply for the DACs switch capacitor of the FMMPX ADC and
FMRDS ADC
FMRDS
79
I
analog FMMPX input for RDS decoding
VrefRDS
80
I
common mode reference voltage input for RDS ADC, level ADC and buffers
1997 May 30
DESCRIPTION
8
Philips Semiconductors
Preliminary specification
65 VDDX
66 VSSX
67 VSSG
68 VSSA1
69 VDDA1
SAA7707H
70 VrefMPX
71 AUXL
72 AUXR
73 TAPEL
74 TAPER
75 AMAF
76 FMMPX
77 VDACPM
78 VDACNM
handbook, full pagewidth
79 FMRDS
80 VrefRDS
Car radio Digital Signal Processor (CDSP)
VDACNL
1
64 XTALO
CINT
2
63 XTALI
FM
3
62 MPXRDS
AM
4
61 RDSDAT
VSSD1
5
60 RDSCLK
VSSA
6
59 TEST2
VDDD1
7
58 VSSD10
VDDA
8
57 TEST1
RIOR
9
56 VDDD2
RVOR 10
55 VSSD6
RIOL 11
54 VSSD5
53 VDDD5
RVOL 12
SAA7707H
Iref(int) 13
52 VDDD4
VSSO 14
51 VSSD4
VDDO 15
50 VSSD3
FIOR 16
49 VDDD3
FVOR 17
48 DCCDAT
FIOL 18
47 DCCWS
FVOL 19
46 DCCCLK
Vref 20
45 DEEM
POM 21
44 MUTE
VSSD2 22
43 MSS/P
CDCLK 23
42 STEREO
41 VSSD8
Fig.2 Pin configuration.
1997 May 30
9
EXCLK 40
SDA 39
SCL 38
EXWS 37
EXSCL 36
EXDAT 35
VSSD7 34
SHTCB 33
RTCB 32
A0 31
TSCAN 30
VSSD9 29
EXDAT2 28
EXDAT1 27
DSPRESET 26
CDDAT 25
CDWS 24
MBH162
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
8
8.1
SAA7707H
The decimation filter reduces the bandwidth of the
incoming signal to a frequency range of 0 to 29 kHz, with
a resulting sampling frequency (fs) of 76 kHz.
The response curve is illustrated in Fig.3.
FUNCTIONAL DESCRIPTION
Signal path for level information
An FM and AM level input is implemented for FM weak
signal processing [for AM, FM and RDS search purposes
(absolute level and multi-path)]. A DC input signal is
converted by a bitstream 1st-order Sigma-Delta
analog-to-digital converter and then filtered by a
decimation filter.
The level information is sub-sampled by the DSP core to
obtain a field strength and a multi-path indication.
These values are stored in the coefficient or data RAM.
They can be read and used in other microcontroller
programs via the I2C-bus.
The input signal has to be obtained from the radio part.
Two different circuits for AM and FM reception are
possible:
8.2
Level ADC switch mode integrator (pin CINT)
The level ADC has an internal current summation point of
the input level and the switch capacitor DAC. When used
as an integrator, an external capacitor of 1000 pF should
be connected between this pin and the analog ground at
pin VSSA1. The summation voltage is used as an input for
the analog-to-digital comparator level.
1. A circuit with two separate input signals, one for FM
level and one for AM level
2. A combined circuit with AM and FM level information
on the FM level input. The AM level input can then be
connected to another signal, which can be converted
in the non-radio mode.
8.3
The input is selected via the input selector control register.
The input signal for level control must be in the range of
0 to 5 V. The 11-bit level ADC converts this input voltage
in steps with a resolution better than 10 mV over the 5 V
range. The tolerance on the gain is less than 10%.
The MSB is always logic 0, to represent a positive level.
Internal ground reference for the level ADC
(pin VDACNL)
This pin serves as the internal ground reference for the
switch capacitor DAC and the level ADC and has to be
connected to the analog ground (pin VSSA1).
MBH164
10
handbook, full pagewidth
α
(dB)
0
−10
−20
−30
−40
−50
−60
0
10
20
30
40
50
60
Fig.3 Frequency response of the level ADC and decimation filter.
1997 May 30
10
70
f (kHz)
80
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
8.4
• ‘Left’ and ‘Right’: This is the 18-bit output of the stereo
decoder after the matrix decoding. For AM reception,
the ‘Right’ signal contains the AM-mono signal. For tape
or auxiliary signals, the output of the stereo decoder
contains sum and difference signals, but with other
crosstalk properties than on FM. Therefore, a different
matrix correction, as shown in Table 1, has to be applied
to these signals in the DSP program. The overall
frequency response of the demultiplexed signal at the
output of the stereo decoder is illustrated in Fig.5.
Common mode reference voltage for RDS
ADC, ADC level and buffers (pin VrefRDS)
The middle reference voltage of the RDS ADC can be
filtered via this pin. This middle reference voltage is used
as a positive reference for the level ADC of the switch
capacitor DAC and as half supply reference for the RDS
ADC, the switch capacitor DACs and buffers. An external
capacitor (connected to VSSA1) prevents crosstalk
between the switch capacitor DACs of the RDS ADC, level
ADC and buffers, and improves the power supply rejection
ratio.
8.5
SAA7707H
Table 1
Overview of the signals to the CDSP
MODE
Signal path for audio/MPX and stereo decoder
AM
The SAA7707H has four analog audio source inputs; two
single-multiplex channel inputs for AM and FM radio and
two stereo inputs for tape and auxiliary. The auxiliary input
can be used for functions such as an analog CD changer
or speech applications. The stereo inputs are multiplexed
so that they can share the same filters as the multiplexed
FM signal. The selection between the AM, FM, TAPE and
AUX input is made via the input selector control register.
1⁄
FM
TAPE/AUX
1⁄
LEFT
RIGHT
0
mono
2(R
− L)
2(R + L) × 4/π
R+L
R+L
Apart from the aforementioned theoretical response, the
non-flat frequency response of the ADC must also be
compensated for in the DSP program.
The input signal behind the source selector is digitized by
a bitstream 3rd-order Sigma-Delta ADC. The first
decimation filter reduces the sample rate. This is followed
by the sample-and-hold switch of the IAC and the 19 kHz
regeneration circuit. From here, the wide-band noise
detector signal HP2 (High-Pass 2) with a frequency range
of 60 to 240 kHz is derived. A second decimation filter
reduces the output of the IAC to a lower sample rate.
8.6
Mono/stereo switching
After division, the Digitally Controlled Sampling (DCS)
clock generates a clock signal with a frequency which is a
multiple of 19 kHz plus or minus a few Hertz. For mono
reception, the DCS circuit generates a preset frequency of
n × 19 kHz ±2 Hz. For stereo reception, the frequency is
exactly n × 19 kHz (DCS locked to n × pilot tone).
The detection of the pilot and the stereo indication is
performed in the DSP program.
This filter has two outputs, one for the multiplex signal with
a frequency range of 0 to 60 kHz (low-pass) and one for
the small-band noise detector signal HP1 (High-Pass 1)
with a frequency range of 60 to 120 kHz. The overall
low-pass frequency response of the decimation filters is
illustrated in Fig.4.
8.7
The automatic lock system
In the FM mode, the RDS ADC can be used as an input for
the MPX decimation filter. This can be selected via the
RDSMPX input at pin 62.
The VCO operates at 19 kHz ±2 Hz exactly for no-pilot.
For stereo reception, the phase error is zero for a pilot tone
with a frequency of exactly 19 kHz. Therefore, no switch is
required to preset the clock to 19 kHz. With auxiliary
sources (tape, CD, etc.), the DCS circuit has to be preset
to a fixed value.
The outputs from this signal path to the DSP, which are all
at a sample frequency of 38 kHz, are as follows:
8.8
• Pilot presence indication: Pilot-I. This 1-bit signal is
LOW for a pilot frequency deviation of less than 4 kHz
and HIGH for a pilot frequency deviation greater than
4 kHz. It is AND locked on a pilot tone.
The FM input sensitivity is optimally designed for an FM
front-end with an output voltage of 200 mV (RMS) at a
modulation depth of 22.5 kHz of a 1 kHz tone. Due to the
full-scale 1.2 V (RMS) handling capacity of the ADC, the
maximum allowed modulation depth of a transmitter, for a
THD of 10%, is 135 kHz. Full performance is possible for
transmitters with a modulation depth of up to 110 kHz.
• Pilot quality indication: Pilot-Q. This 10-bit signal
contains information about the signal quality and is
derived from the quadrature component of the pilot-I
signal.
1997 May 30
Input sensitivity for FM
11
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SAA7707H
MBH165
10
handbook, full pagewidth
0
−10
α
(dB)
−30
−50
−70
−90
−110
−130
−150
0
50
100
150
200
250
300
350
400
450 f (kHz) 500
Fig.4 Overall frequency response multiplex ADC and decimation filters.
MBH166
20
handbook, full pagewidth
α
(dB)
0
−20
−40
−60
−80
−100
0
10
20
30
40
50
60
Fig.5 Transfer of MPX signal at the output of the stereo decoder.
1997 May 30
12
70
f (kHz)
80
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
8.9
8.11
Common mode reference voltage for MPX ADC
and buffers (pin VrefMPX)
Noise level
The High-Pass 1 (HP1 or narrow-band noise level filter)
output of the second MPX decimation filter, in a frequency
band from 60 to 120 kHz, is detected with an envelope
detector and decimated to a frequency of 38 kHz.
The middle reference voltage of the MPX ADC can be
filtered via this pin. This middle reference voltage is used
as a half supply voltage reference for the MPX ADC,
switch capacitor DACs and buffers. An external capacitor
(connected to VSSA1) prevents crosstalk between the
switch capacitor DACs and buffers and improves the
power supply rejection ratio.
8.10
SAA7707H
The response time of the detector is 100 ms.
Another option is the High-Pass 2 (HP2 or wide-band
noise level filter). This output from the first MPX decimation
filter is in a frequency band from 60 to 240 kHz. It has the
same properties as the HP1 and is also decimated to
38 kHz. Which signal is used (HP1 or HP2) is determined
by the input selector control register. The noise level can
be detected and filtered in the DSP core and can be used
to optimize the FM weak-signal processing. The transfer
curves of both filters before decimation are illustrated in
Fig.6.
Supply voltages for the switch capacitor DACs
of the FMMPX ADC and FMRDS ADC
(pins VDACNM and VDACPM)
These pins are used as ground and positive supply voltage
reference for the MPX ADC, RDS ADC and the switch
capacitor DACs. For optimum performance they must be
connected directly to VSSA1 and VDDA1.
MBH167
10
handbook, full pagewidth
0
−10
α
(dB)
−30
−50
−70
(2)
−90
(1)
−110
−130
−150
0
50
100
150
200
250
(1) Narrow-band noise level filter.
(2) Wide-band noise level filter.
Fig.6 Frequency response of noise level before decimation.
1997 May 30
13
300
f (kHz)
350
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
8.12
Table 2
TAPE/AUX de-multiplex
The auxiliary and tape inputs also use the stereo decoder.
Because of this, the left and right channels are multiplexed
with a 38 kHz square wave to obtain a signal similar to the
FM multiplexed signal. Auxiliary inputs can be e.g.
TV-sound, remote players (tape deck, CD-changer with
analog output etc.). The signal-to-noise ratio from such
sources is limited by the ADC in the SAA7707H (>75 dB).
The decimation filter of the ADC attenuates the harmonic
signals from this stereo encoder. For an optimum channel
separation, the 38 kHz switch signal has to be phase
corrected to compensate for the delay of the ADC and
decimation filters. This can be adjusted with the 3-bit group
delay compensation in the IAC control register. Signal
frequencies above 19 kHz at the input of the multiplexer
are converted to the audio base-band and are therefore
not allowed.
8.13
AM/FM
0
x
1
0
0
0
1
x
0
x
0
1
0
0
1
0
0
0
1
0
x
1
1
0
0
0
1
Analog inputs supply
The analog input circuit has its own separate power supply
connections to allow maximum filtering. These pins are
VSSA1 for the analog ground and VDDA1 for the analog
power supply. VSSG is the connection to the guard ring
which isolates the analog part from the digital filters.
This pin has to be connected to the analog ground.
Signal-to-noise considerations
8.17
Digitally controlled sampling clock (DCS)
The crystal clock generates a continuous clock signal for
the internal DSP core. In the radio mode, the stereo
decoder, the RDS decoder, the ADCs and the level
decimation filters have to run synchronously with the
19 kHz pilot. Therefore, a clock signal with a controlled
frequency with a multiple of 19 kHz
(9.728 MHz = 512 × 19 kHz) is required.
In the SAA7707H, the patented method of a
non-continuous digitally controlled sampling clock has
been implemented. A frequency of 9.728 MHz is
generated by a special dividing mechanism of the master
crystal clock. Since the dividing mechanism is fixed, only a
crystal frequency of 36.86 MHz can be used.
Channel separation correction
The channel separation is approximately 50 dB at 1 kHz
and 35 dB at 15 kHz. Because the frequency response of
the ADC has some deviation from the flat curve around
38 kHz, a perfect channel separation cannot be obtained.
Therefore, the de-multiplexed signal is corrected for
crosstalk in the DSP program.
The DCS system is controlled by up/down information
from the stereo decoder. For mono transmissions, the
DCS clock is still controlled by the stereo decoder loop.
The output keeps the DCS free-running at a multiple
frequency of 19 kHz ±2 Hz. In TAPE/AUX and AM mode,
the DCS clock must always be put in preset mode by the
input selector control register.
Input selection switches
A schematic diagram of the input selection is illustrated in
Fig.5. The input selection is controlled by bits in the input
selector control register. The relationship between these
bits and the switches is indicated in Table 2.
1997 May 30
SWITCH
AUX/ TAPE/
SFM SAM SAUX SAUX
RADIO AUX
0
8.16
To avoid aliasing into the tape channel, the tape noise from
the pre-amplifier must be attenuated before
analog-to-digital conversion with a 1st-order 10 kHz
low-pass filter. The frequency response is equalized after
the stereo decoder in the DSP program before the Dolby
decoder software. Using this filter, the signal-to-noise ratio
of this channel is degraded by 3 dB. This results in a
signal-to-noise ratio that is overall 6 dB lower than a tape
input with respect to FM stereo.
8.15
Analog input selection
I2C-BUS SELECTION
BIT
Due to the pre-emphasis of FM broadcasts, the theoretical
signal-to-noise ratio is approximately 3 dB higher for FM
stereo in comparison with multiplexed inputs.
8.14
SAA7707H
14
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
8.18
Survey of the DCS clock settings in different
modes
8.20
DCS clock/mode
MODE
FM stereo
locked on 19 kHz pilot of received
FM signal
free running
AM analog inputs
TAPE/AUX
fixed preset
I2C-bus inputs
DCC/CD
fixed preset
8.19
The input signal to the IAC circuit is derived from the output
signal of the decimation filter. The interference detector
analyses the high frequency content of this MPX signal.
The discrimination between interference pulses and other
signals is performed by a special Philips patented fuzzy
logic-like algorithm and is based on probability
calculations. This logic will send appropriate pulses to an
MPX mute switch.
DCS CLOCK
FM mono
At Power-on, the nominal setting for an IAC with good
performance characteristics is selected (all IAC control bits
are 0). If an adjustment is needed, the characteristics can
be adapted as described in the application manual.
Synchronization with the core
A 38 kHz synchronization signal is derived from the DCS
clock and divided by 256.
8.21
If the external I2S-bus DCC CD is selected, the rising edge
of the Word Select input signal is used to synchronize with
the core.
1997 May 30
Interference absorption circuit
The Interference Absorption Circuit (IAC) detects and
suppresses ignition interference. This hardware IAC is a
modified and digital version of the analog circuit that has
already been in use for many years.
The DCS clock behaves as shown in Table 3.
Table 3
SAA7707H
IAC testing
The internal IAC trigger signal is visible on the MSS/P pin
(pin 43) if the IAC trigger output bit of the IAC control
register is set. In this mode, the effect of the parameter
settings on the IAC performance can be verified.
15
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
0
handbook, full pagewidth
FM
SAA7707H
SAMFM
level
ADC
AM
1
0
0
TAPER
1
CLMPX
STAPE
ADC
0
1
TAPEL
1
0
AUXR
1
SAUX
0
0
RDS_MPX
MPX
1
AUXL
1
0
SAM
AM/FM
1
0
FMMPX
1
SFM
0
1
0
SINTEXT
RDS
ADC
FMRDS
MBH168
1
Fig.7 Schematic diagram of input selection.
• The SAMFM switch is controlled by the SEL-LEV-AM/FM bit
• The SINTEXT switch is controlled by the SEL-RDS-EXT/INT bit
• The CLMPX switch is controlled by the 38 kHz clock derived from the DCS, but is not active in FM and AM mode.
In the FM radio mode, the MPXRDS pin overrides the following switches when set to logic HIGH:
If SEL-AM/FM = 0 and SEL-AUX/RADIO = 0 and pin MPXRDS = 1, then SFM = 0, SINTEXT = 1 and MPXRDS = 1.
1997 May 30
16
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
9
9.1
For external digital sources (DCC and CD), a sample
frequency from 32 to 48 kHz is possible. The sample
frequency is automatically adjusted to the I2S-bus input by
dividing the external bit clock. This clock is normally
present in a DCC CD application. An internal digital PLL
divides this clock with the integer factor needed to obtain
the 4fas word clock. Master synchronization of this divided
clock signal is obtained with a reset of the divider on the
Word Select signal (trailing edge) of the I2S-bus.
ANALOG OUTPUTS
Digital-to-analog converters
Each of the four low-noise high dynamic range DACs
consists of a 15-bit signed magnitude DAC with current
output, followed by a buffer operational amplifier.
The five higher bits (bits 10 to 14) are used to control the
total coarse current ratio of the 32 coarse current sources
via a thermometer decoder. The nine lower bits
(bits 1 to 9) are derived from a 512 transistor matrix, which
acts as a passive 9-bit current divider for one of the coarse
currents. The MSB (bit 15) is used as a sign bit for the
signed magnitude converter and controls the direction of
the total output current. A separate converter is used for
each of the four audio output channels. The value of each
coarse current is adjusted by the current through the
external resistor connected to pin 13 (Iref(int)).
In the application, the I2S-bus signal from the external
source should fulfil the following requirements:
• There is a continuous (is part of the basic I2S-bus
specification) n × 4fas (4 < n < 128) I2S-bus bit clock or
• If the I2S-bus bit clock is not continuous, another n × 4fas
(4 < n < 128) continuous clock signal has to be
connected to the EXCLK pin (pin 40). The divide
external clock mode has to be selected using the input
selector control register.
Each converter output is connected to the inverting input
of one of the four internal CMOS operational amplifiers.
The non-inverting input of this operational amplifier is
connected to the internal reference voltage. Together with
an external resistor, the current-to-audio output voltage
conversion is achieved.
9.2
The range of the internal 7-stage programmable divider of
the PLL, to obtain 4fas, is large enough to handle 16-bit
I2S-bus signals as well as master clocks up to 22 MHz
from digital sources (CD, DCC, R-DAT and EBU interface)
without any clock regeneration.
The PLL is used in a free-running mode to ensure that jitter
on the I2S-bus signals (due to asynchronous clocking of
the I2S-bus signals by the DSP core) will not influence the
total harmonic distortion of the audio signal on the analog
DAC part. This will, however, only operate if there is no
jitter on the bit clock or when a crystal clock is used.
Upsample filter
To reduce spectral components above the audio band, a
fixed 4 times oversampling and interpolating 18-bit digital
IIR filter is used. It is realized as a bit serial design and
consists of two consecutive filters. The data path in these
filters is 22 bits, to prevent overflow and to maintain a
theoretical signal-to-noise ratio greater than 105 dB.
The filters give an attenuation of at least 29 dB. The filter
is followed by a 5 bit 1st-order noise shaper, to expand the
dynamic range to more than 105 dB.
9.3
Volume control
The total volume control has a dynamic range of more than
100 dB. With the signed magnitude noise-shaped 15-bit
DAC and the internal 18 bit registers of the DSP core, a
useful digital volume control range of 100 dB is possible by
calculating the corresponding coefficients. The step size is
freely programmable and an additional analog volume
control is not needed in this design. The signal-to-noise
ratio of the audio output, at full-scale, is determined by the
total 15 bits of the converter.
The band around multiples of the sample frequency of the
DAC (4fas) is not affected by the digital filter. A capacitor
can be added in parallel with the output resistor at the DAC
output to further attenuate this out-of-band noise to an
acceptable level.
The overall frequency spectrum at the DAC audio output
without external capacitor/low-pass filter for the audio
sampling frequencies (fas) of 38 kHz is illustrated in Fig.8.
The detailed spectrum around fas is illustrated in Fig.9 for
an fas of 38 kHz, 44.1 kHz and 48 kHz. The pass-band
bandwidth (at −3 dB) is 1⁄2fas.
The noise at low outputs is fully determined by the noise
performance of the DAC. Since it is a signed magnitude
type, the noise at digital silence is also low.
The disadvantage is that the total THD is higher than
conventional DACs. The typical signal and noise levels as
a function of the output level and the typical signal-to-noise
plus THD as a function of the output level are illustrated in
Fig.10.
The word clock for the upsample filter (4fas) is derived from
the audio source timing. If the internal audio source is
selected, the sample frequency is fixed at 38 kHz.
1997 May 30
SAA7707H
17
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
9.4
The operational amplifiers have the VSSO and VDDO pins
as ground and positive supply. These pins also provide the
supply for the reference circuits. The analog DAC part
uses the VSSA and VDDA pins as ground and positive
supply. The upsample filter and digital part of the DAC
share the VSSD1 and VDDD1 as ground and positive supply
connections.
Power-on mute
To avoid any uncontrolled noise at the audio outputs after
Power-on of the IC, the reference current source of the
DAC is switched off. The capacitor connected to pin 21
(POM) determines the time after which this current has a
soft switch-on. Consequently, at Power-on, the current
audio signal outputs are always muted. The voltage output
signals will show a small jump at switch-on due to the
asymmetrical voltage supply of the output operational
amplifiers. These types of disturbances must be
eliminated via the application set-up. The output has to be
set to digital silence before the POM pin is at logic HIGH.
This is achieved via the DSP program control and/or a zero
volume setting. The pin is internally connected to VDDO
with a high-ohmic resistor.
9.5
9.9
Power-off plop suppression
The signal on the XTAL pin is amplified and divided by two.
This 18.43 MHz signal is then used as the DSP clock
signal (PH2). For the high frequency, as used in the
SAA7707H, normally only third overtone crystals are
available. With an external LC notch filter at the
fundamental frequency, oscillation at this frequency can
be avoided.The crystal frequency is chosen in such a way
that the harmonics are outside the normal FM band.
The crystal frequency used is 36.86 MHz.
Internal reference buffer amplifier of the DAC
(pin Vref)
Using two internal resistors, half of the supply voltage
(VDDO) is obtained and coupled to an internal buffer.
This reference voltage is used as a DC voltage for the
output operational amplifiers and as a reference voltage
for the DAC. In order to obtain the lowest noise and to have
the best ripple rejection, a filter capacitor has to be added
between this pin and ground.
9.7
9.10
Crystal oscillator supply
The power supply connections for the oscillator are
separate from the other supply lines. This is to minimize
the feedback from the ground bounce of the chip to the
oscillator circuit. The VSSX pin (pin 66) is used as ground
supply and the VDDX pin (pin 65) as positive supply.
Internal DAC current reference
9.11
As a reference for the current at the DAC current source,
a current is drawn from pin 13 (Iref(int)) to the VSSO ground.
The voltage at this pin is 1⁄2VDDO (typically 2.5 V).
The maximum DAC current is equal to 4.5 times this
current. When a reference resistor of 18 kΩ is used, the
reference current from the DAC is 125 µA. This results in
a peak current from the four current outputs of
4.5 × 125 = 562.5 µA.
9.8
Clock circuit and oscillator
The SAA7707H has an on-board crystal clock oscillator.
The schematic of this Pierce oscillator is illustrated in
Fig.11. The active element needed to compensate for the
loss resistance of the crystal is the block ‘Gm’. This block
is placed between the XTAL (output) and the OSC (sense)
pins. The gain of the oscillator is internally controlled by the
AGC block; this prevents excessive power loss in the
crystal. The higher harmonics are then as low as possible.
To avoid plops in a power amplifier, the supply voltage of
the analog part of the DAC can be fed via a Schottky diode
and an extra capacitor. In this situation, the output voltage
will decrease gradually, allowing the power amplifier some
extra time to switch off without audible plops.
9.6
SAA7707H
For external control, two input pins have been
implemented. The status of these pins can be changed by
applying a logic level, and is recorded in the internal status
register. The functions of each pin are as follows:
• MUTE (pin 44). Mute input (0 = MUTE)
• DEEM (pin 45). This pin activates the de-emphasis for
CD and DCC. (1 = de-emphasis on).
To control external devices, two output pins are
implemented. The status of these pins is controlled by the
DSP program. The functions of each pin are as follows:
Analog outputs supply
For an optimum signal-to-noise performance, supply ripple
rejection and to suppress switch-off plops, the output
operational amplifiers, the analog part of the DACs and the
upsample filter plus digital part have separate power
supply connections.
1997 May 30
External control pins
18
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SAA7707H
• STEREO (pin 42): Indicates whether an FM broadcast is in stereo (1 = stereo)
• MSS/P (pin 43): Indicates a pause in FM or tape search mode (1 = pause). This is also the IAC trigger output for IAC
alignment if the corresponding I2C-bus bit is set.
MBH169
5
handbook, full pagewidth
0
α
−5
(dB)
−15
−25
−35
−45
−55
−65
0
50
100
150
200
250
300
400
350
450 f (kHz) 500
Fig.8 Overall frequency spectrum audio output (fas = 38 kHz).
MBH170
10
handbook, full pagewidth
α
(dB)
0
−10
−20
−30
−40
−50
0
0
0
10000
11605
12632
20000
23211
25263
30000
34815
37895
Fig.9 Detailed frequency spectrum of audio output.
1997 May 30
19
f (Hz)
40000
46420
50528
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SAA7707H
MBH171
100
handbook, full pagewidth
S/(N+THD)
and
S/N (dB)
80
60
(1)
40
(2)
20
0
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
output level (dB)
(1) Signal-to-noise.
(2) Signal-to-noise + total harmonic distortion.
Fig.10 Typical signal-to-noise level and signal-to-noise plus THD as a function of output level.
handbook, full pagewidth
Gm
AGC
/2
PH2
ON CHIP
OFF CHIP
63
64
65
66
OSC
XTAL
VDDX
VSSX
Rbias
Cx1
Cx2
MBH172
Fig.11 Schematic diagram of the oscillator circuit.
1997 May 30
20
0
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
The Word Select line automatically determines the
SAA7707H sampling frequency.
10 I2S-BUS DESCRIPTION
10.1
I2C-bus control (pins SCL and SDA)
Using the Digital Source Selector (see Fig.1), one of the
three possible input sources is selected. The selected
audio data channels are input to two 18-bit wide memory
mapped I/O registers of the DSP named Input Left and
Input Right.
For external control of the SAA7707H, a standard I2C-bus
is implemented. There are two different types of control
instructions:
• Instructions to control the DSP program, programming
the coefficient RAM and reading the values of
parameters (level, multi-path etc.)
Except for the 4fas pulse to control the upsample filter
(see Section 9.2), other synchronization signals such as
internal Word Select are derived from the I2S-bus input
signals.
• Instructions controlling the DATA flow, such as source
selection, IAC control and clock speed.
10.2
The input bit clock is used as a bit clock for the external
processor. As a consequence, a clock pulse input signal
with less than 18 bits will result in a communication with an
external processor of the same number of bits. In this
event, the trailing bits of the 18-bit input registers will be
zero.
I2S-bus description
For communication with external digital sources and/or
additional external processors, the I2S-bus digital interface
is used. It is a serial 3-line bus, having one line for Serial
Data (SD), one line for Serial Clock (SCK) and one line for
the Word Select (WS). For external processors, the CDSP
acts as a master transmitter; for external digital sources
the CDSP acts as a slave. The communication with the
external processor and external digital sources are
separated, to allow both features at the same time.
If the I2S-bus driver outputs of the external digital source
ICs have 3-state outputs, they can all be connected on one
single I2S-bus input.
10.4
Figure 12 shows an extract of the Philips I2S-bus
specification interface report regarding the general timing
and format of the I2S-bus. Word select logic 0 means left
channel word; word select logic 1 means right channel
word.
The SAA7707H acts as the master transmitter and the
external device has to be synchronized with the Word
Select line.
As input for the processed data, two data input lines have
been implemented that are processed synchronously with
the data output to the external processor (see Table 4).
This enables, in total, a feedback of two stereo audio
channels.
As inputs from an external processor for the four audio
channels, two data lines have been implemented.
Communication with external digital audio
sources (DCC + CD-WS/CL/Data pins)
For this communication, the DSP core has the following
18-bit memory mapped I/O registers available:
For communication with external digital audio sources, two
additional I2S-bus inputs are available. They each have
clock, data and Word Select input lines with a maximum
useful data length of 18 bits. The external source is master
and supplies the clock. The input selection and port
selection is controllable via the input selector control
register. The DSP program is synchronized with the
external source via the Word Select signal.
Table 4
DSP core I/O registers
INPUT
EXDAT1 left/right
EXDAT2 left/right
OUTPUT
EXDAT left/right
The DSP program moves data from the two external
I2S-bus data output registers to the external processor and
reads it back from the two or four external I2S-bus data
input registers. The hardware of the bus can be enabled by
the input control register.
The input allows a variety of clock frequencies, sample
frequencies and word lengths.
1997 May 30
Communication with external processors and
other devices (EXWS/CL/EXDAT1 and EXDAT2)
For communication with external processors, delay lines
or other I2S-bus controllable devices, a complete
dual-channel 18-bit output bus is implemented.
The serial data is transmitted in twos complement with the
MSB first. One clock period after the negative edge of the
Word Select line, the MSB of the left channel is
transmitted. Data is synchronized with the negative edge
of the clock and latched at the positive edge.
10.3
SAA7707H
21
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
To minimise electro magnetic interference (EMI), the
output has to be disabled if the output is not used.
In this way, it can be performed without interruption of the
audio program. The MPX signal from the main tuner of the
car radio can be connected to this RDS input via the
built-in source selector.
The timing diagram of the communication is illustrated in
Fig.13.
10.5
The input selection is controlled by the input selector
control register.
Relationship between external input and
external output
For FM stereo reception, the clock of the total chip is
locked to the stereo pilot (19 kHz multiple). For FM mono,
the DCS loop keeps the DCS clock around the same
19 kHz multiple. In all other cases, such as AM reception
or tape, the DCS circuit has to be set to a preset position.
Under these conditions, the RDS system is always clocked
by the DCS clock in a 38 kHz (4 × 9.5 kHz) based
sequence.
The stereo decoder output has an internal I2S-bus format
with 32 clock pulses per channel for 18 valid and 14 zero
data bits. Providing that the stereo decoder output is used,
the communication with the external processor will also
have 32 clock pulses per channel for 18 valid and 14 zero
data bits.
When an external digital source is selected, the number of
valid bits and clock pulses of this source determines the
output to the external processor. This relationship is
shown in Table 5.
Table 5
INPUT
DATA
BITS
OUTPUT
CLOCK
BITS
OUTPUT
DATA
BITS
>32
≥18
32
18
≥18 and ≤32
≥18
as input
18
≥18 and ≤32
<18
as input
18
<18
<18
as input
as input
10.6
10.8
During poor reception, it is possible that errors in phase
may occur. Consequently the duty cycle of the clock and
data signals will vary from a minimum of 0.5 times to a
maximum of 1.5 times the standard clock periods.
Normally, errors in phase do not occur on a cyclic basis.
10.9
RDS decoder (RDSCLK and RDSDAT)
10.10 Buffer interface
The RDS interface buffers 16 data bits. Each time 16 bits
are received, the data line is pulled down and the buffer is
overwritten. The control microcontroller has to monitor the
input data line at least every 13.5 ms. This mode is
selected by the input selector control register.
The interface signals from the RDS decoder and the
microcontroller in the buffer mode are illustrated in Fig.15.
When the buffer is filled with 16 bits, the data line is pulled
down.
The RDS decoder has three different functions:
1. Clock and data recovery from the MPX signal
2. Buffering of 16 bits, if selected
3. Interfacing with the microcontroller.
Clock and data recovery
The RDS chain has a separate input. This enables RDS
updates during tape play and also the use of a second
receiver for monitoring the RDS information of signals from
another transmitter (double tuner concept).
1997 May 30
Buffering of RDS data
The repetition frequency of RDS data is approximately
1187 Hz. This results in an interrupt on the microcontroller
every 842 µs. In a second mode, the RDS interface has a
double 16-bit buffer.
The RDS decoder recovers the additional inaudible RDS
information transmitted by FM radio broadcasting.
The (buffered) data is provided as an output for further
processing by a suitable decoder. The operational
functions of the decoder are in accordance with EBU
specification EN 50067.
10.7
Timing of clock and data signals
The timing of the clock and data output is derived from the
incoming data signal. Under stable conditions, the data will
remain valid for 400 µs after the clock transition.
The timing of the data change is 100 µs before a positive
clock change. This timing is suitable for positive and
negative triggered interrupts on a microcontroller.
The RDS timing is illustrated in Fig.14.
Relationship between external input and
external output.
INPUT
CLOCK
BITS
SAA7707H
The data line will remain LOW until reading from the buffer
is started, by pulling down the clock line. The first data bit
is clocked out.
22
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
After 16 clock pulses, the buffer is read and the data line is
set HIGH until the buffer is filled again. The microcontroller
stops communication by pulling the clock line HIGH.
SAA7707H
Long before the DAC outputs reach their nominal output
voltages, the DSP must be in the working mode (to reset
the output register) therefore, the DSP time constant must
be shorter than the POM time constant. For advised
capacitors, see Figs. 24 and 25.
The data is written out just after the clock HIGH-to-LOW
transition. The data is valid when the clock is HIGH.
The DSP reset has the following functions:
When a new 16-bit buffer is filled before the other buffer is
read from, that buffer will be overwritten and the old data
will be lost.
• The bits of the IAC control register are set to logic 0
• The bits of the input selector control register are set to
logic 0
10.11 DSP reset
• The program counter is set to address $0000.
The reset pin (DSP) is active LOW and has an internal
pull-up resistor. To allow a proper switch-on of the supply
voltage, a capacitor should be connected between this pin
(pin 26) and VSSD. The value of the capacitor is such that
the SAA7707H will remain in reset as long as the power
supply is not stabilized. A more or less fixed relationship
between the DSP reset and the POM (pin 21) time
constant is obligatory. The voltage on the POM pin
determines the current flowing in the DACs. At 0 V
(at pin 21), the DAC currents are zero and therefore the
DACs output voltages are also zero. At 5 V, the DAC
currents are at their nominal (maximum) value.
When the level on the DSP is at logic HIGH, the DSP
program starts to run.
10.12 Power supply connection and EMC
The digital part of the SAA7707H has 5 positive supply
lines (VDDD1 to VDDD5) and 10 ground connections
(VSSD1 to VSSD10). To minimize radiation, the SAA7707H
should be put on a double-layer PCB with, on one side, a
large ground plane. The ground supply lines should have
a short connection to this ground plane. A coil/capacitor
network in the positive supply line can be used as a high
frequency filter.
Tcy
handbook, full pagewidth
tLC≥0.35 T
tHC≥0.35 T
VIH (70%)
SCK
VIL (20%)
tsr≥0.2 T
SD
thr≥0
VIH (70%)
WS
VIL (20%)
SCK
WS
SD
MSB
LEFT
MSB
RIGHT
MBH173
Fig.12 I2S-bus timing and format.
1997 May 30
23
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
handbook, full pagewidth
tHC
SAA7707H
tLC
EXSCL
CL
td1
tr
tf
tf
tr
WS
EXWS
td2
ts2
EXDAT1
EXDAT2
INPUT
EXDAT1
EXDAT2
t3
ta
tr
tf
EXDAT
OUTPUT
EXDAT
MBH174
Fig.13 Timing diagram of the CDSP to external processor.
handbook, full pagewidth
RDSDAT
RDSCLK
ts
tHC
Tcy
tLC
td
MBH175
Fig.14 RDS timing diagram in direct output mode.
1997 May 30
24
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SAA7707H
handbook, full pagewidth
RDSDAT
D0
D1
D2
D13
D14
D15
tLC
RDSCLK
tHC
tw
block ready
MBH176
Tcy
start reading data
Fig.15 Interface signals RDS decoder and microcontroller.
11 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDDD
DC supply voltage
−0.5
+6.5
V
∆VDDD
voltage difference between any two
VDDX pins
−
550
mV
IIK
DC input clamp diode current
VI < −0.5 V or VI > VDDD + 0.5 V
−
±10
mA
IOK
DC output clamp diode current
output type 4 mA;
VO < −0.5 V or VO > VDDD + 0.5 V
−
±20
mA
IO
DC output sink or source current
output type 4 mA;
−0.5 V < VO < VDDD + 0.5 V
−
±20
mA
IDDD
DC supply current per pin
−
±50
mA
−
±50
mA
100
−
mA
power dissipation per output
−
100
mW
Ptot
total power dissipation
−
1600
mW
Tamb
operating ambient temperature
−40
+85
°C
Tstg
storage temperature
−65
+150
°C
VESD
electrostatic handling for all pins
note 1
3000
−
V
note 2
300
−
V
ISSD
DC ground supply current per pin
LTCH
latch-up protection
Po
CIC specification/test method
Notes
1. Human body model: C = 100 pF; R = 1500 Ω; 3 pulses positive plus 3 pulses negative.
2. Machine model: C = 200 pF; L = 2.5 µH; R = 25 Ω; 3 pulses positive plus 3 pulses negative.
1997 May 30
25
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SAA7707H
12 THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
VALUE
UNIT
Rth j-a
from junction to ambient in free air and VSSD lead fingers 50, 51, 54 and 55 of
the QFP80 soldered to a PCB copper plate of 36 cm2
35
K/W
Rth j-a
from junction to ambient in free air and VSSD lead fingers 50, 51, 54 and 55 of
the QFP80 not connected to a PCB copper plate
42
K/W
13 DC CHARACTERISTICS
VDDD = 4.75 to 5.5 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Digital part
DIGITAL INPUTS AND OUTPUTS; NOTE 1
VDDD(tot)
total DC supply voltage
all VDDD pins
4.75
5.0
5.5
V
IDDD(tot)
total DC supply current
maximum activity
of the DSP;
fxtal = 36 MHz
−
160
200
mA
Ptot
total power dissipation
maximum activity
of the DSP;
fxtal = 36 MHz
−
0.8
1.1
W
VIH
HIGH level input voltage;
pins 23 to 25, 27, 28,
30 to 33, 38 to 40,
44 to 48, 60 and 62
0.7VDDD
−
−
V
HIGH level input voltage;
pin 26
0.8VDDD
−
−
V
VIL
LOW level input voltage;
pins 23 to 28, 30 to 33,
38 to 40, 44 to 48, 60
and 62
−
−
0.2VDDD
V
Vhys
hysteresis voltage pin 26
−
0.33VDDD −
V
VOH
HIGH level output
voltage; pins 23,
35 to 37, 42, 43, 48, 57,
60 and 61
VDDD = 4.75 V;
IO = −4 mA
4.25
−
−
V
VOL
LOW level output
voltage;
pins 23, 35 to 37, 39, 42,
43, 48, 57, 60 and 61
VDDD = 4.75 V;
IO = 4 mA
−
−
0.5
V
ILI
input leakage current;
pins 24, 25, 27, 28, 38
and 44 to 47
VI = 0 or VDDD
−
−
±1
µA
IOZ
3-state output leakage
VO = 0 or VDDD
current; pins 23, 35 to 37,
39, 42, 48, 57 and 60
−
−
±5
µA
1997 May 30
26
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SYMBOL
PARAMETER
CONDITIONS
SAA7707H
MIN.
TYP.
MAX.
UNIT
17
−
134
kΩ
Vi = VDDD
17
−
134
kΩ
input rise time
VDDD = 5.5 V
−
6
200
ns
tf
input fall time
VDDD = 5.5 V
−
6
200
ns
tr
output rise time for
LOW-to-HIGH transition
VDDD = 4.75 V;
−
Tamb = 85 °C;
pins 23, 48 and 60
−
1.43 + 0.24CL
ns
VDDD = 4.75 V;
Tamb = 85 °C;
pins 43 and 61
−
−
4.75 + 0.28CL
ns
VDDD = 4.75 V;
Tamb = 85 °C;
pins 35 to 37, 42
and 57
−
−
4.75 + 0.28CL
ns
VDDD = 5.5 V;
0.351 + 0.097CL −
Tamb = −40 °C;
pins 23, 48 and 60
−
ns
VDDD = 5.5 V;
Tamb = −40 °C;
pins 43 and 61
1.302 + 0.101CL −
−
ns
VDDD = 5.5 V;
Tamb = −40 °C;
pins 35 to 37, 42
and 57
1.302 + 0.101CL −
−
ns
Rpu
internal pull-up resistor to
VDDD pin 26
Rpd
internal pull-down
resistor to VSSD pins
30 to 33, 40 and 62
tr
tf
1997 May 30
output fall time for
HIGH-to-LOW transition
VDDD = 4.75 V;
−
Tamb = 85 °C;
pins 23, 48 and 60
−
1.82 + 0.31CL
ns
VDDD = 4.75 V;
Tamb = 85 °C;
pins 43 and 61
−
−
6.44 + 0.36CL
ns
VDDD = 4.75 V;
Tamb = 85 °C;
pins 35 to 37, 42
and 57
−
−
6.44 + 0.36CL
ns
0.386 + 0.097CL −
VDDD = 5.5 V;
Tamb = −40 °C;
pins 23, 48 and 60
−
ns
VDDD = 5.5 V;
Tamb = −40 °C;
pins 43 and 61
0.971 + 0.115CL
−
−
ns
VDDD = 5.5 V;
Tamb = −40 °C;
pins 35 to 37, 42
and 57
0.971 + 0.115CL
−
−
ns
27
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SYMBOL
PARAMETER
CONDITIONS
SAA7707H
MIN.
TYP.
MAX.
UNIT
Analog part
ANALOG INPUTS: VDDA1 = 5 V; Tamb = 25 °C
VDDA1
analog supply voltage
for ADC
4.75
5.0
VrefMPX
common mode
reference voltage MPX
ADC pin 70
VrefRDS
common mode
reference voltage RDS
ADC pin 80
ZO
5.5
V
with respect to
pins 68 and 69
0.47VDDA1
0.5VDDA1 0.53VDDA1
V
with respect to
pins 68 and 69
0.47VDDA1
0.5VDDA1 0.53VDDA1
V
output impedance at pins
70 and 80
−
600
−
Ω
VDACPM
positive reference
voltage for MPX ADC
and RDS ADC
4.75
5.0
5.5
V
IVDACPM
positive reference current
for MPX ADC
−
−20
−
µA
VDACNM
negative reference
voltage for MPX ADC
and RDS ADC
−0.3
0
+0.3
V
IVDACNM
negative reference
current MPX ADC
−
20
−
µA
VDACNL
negative reference
voltage level A/D
−0.3
0
+0.3
V
IVDACNL
negative reference
current for level ADC
−
5
−
µA
VIosMPX
input offset voltage MPX
−
140
−
mV
VIosRDS
input offset voltage RDS
−
140
−
mV
ANALOG OUTPUTS: VDDD = VDDA = VDDO = 5 V; Tamb = 25 °C
VDDD1
digital supply voltage for
upsample filter and
digital DAC
4.75
5.0
5.5
V
VDDA1
analog supply voltage
for DAC
4.75
5.0
5.5
V
VDDO
operational amplifier
supply voltage
4.75
5.0
5.5
V
Vref
input voltage on pin 20
0.47VDDO
0.5VDDO
0.53VDDO
V
Z15-20
impedance between
pins 15 and 20
12
18
25
kΩ
Z14-20
impedance between
pins 14 and 20
12
18
25
kΩ
V13
input voltage on pin 13
0.46VDDA
0.5VDDA
0.54VDDA
V
1997 May 30
with respect to
pins 14 and 15
with respect to
pins 14 and 15
28
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SYMBOL
PARAMETER
CONDITIONS
IO(DAC; max)
maximum output current
from DACs
VO(os)
DC offset voltage at DAC with respect to
output
pin 20
VO(rms)
AC output voltage of
operational amplifier
outputs at maximum
signal pins 10, 12, 17
and 19 (RMS value)
VO(av)
average DC output
voltage at pins 10, 12,
17 and 19
RPOM
pull-up resistor to pin 15
SAA7707H
MIN.
TYP.
MAX.
UNIT
490
570
650
µA
−
5
−
mV
RL > 5 kΩ;
Rfb = 2.7 kΩ;
note 2
0.94
1.09
1.24
V
RL > 5 kΩ;
Rfb = 2.7 kΩ;
note 2
2.25
2.5
2.75
V
64
128
260
kΩ
4.75
5.0
5.5
V
reference
resistance to
pin 14 = 18 kΩ
Crystal oscillator: Tamb = 25 °C
VDD(osc)
oscillator supply voltage
Current per supply pin or pin group: Tamb = 25 °C; VDD = 5 V (typ.); 5.5 V (max.)
IDDD1
digital supply current
DACs pin 7
−
20
50
µA
IDDA
analog supply current
DAC pin 8
−
4
8
mA
IDDO
supply current for
operational amplifiers
pin 15
−
2
4
mA
IDDD
supply current for digital
circuitry and periphery
pins 49, 52, 53 and 56
−
137.5
165
mA
IDDX
supply current for crystal
circuit pin 65
−
1.5
3
mA
IDDA1
supply current for ADCs
pin 69
−
15
20
mA
no load
Notes
1. The values for the capitative load CL are given in pF.
2. RL is the AC impedance of the external circuitry at 1 kHz, connected to the audio outputs in the application. There is
also no DC current flowing through RL.
1997 May 30
29
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SAA7707H
14 AC CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Analog DC inputs (LEVEL-FM, AM): VDDD = VDDA1 = 5 V; Tamb = 25 °C
S/N
signal-to-noise ratio ADC
RMS value;
not weighted;
B = 0 to 29 kHz;
maximum input
48
54
−
dB
RMS value;
not weighted; audio
mode; B = 0 to 19 kHz;
maximum input
52
58
−
dB
200
400
−
kΩ
Ri
input resistance
VFS
full-scale input voltage
VDDA1 = 4.75 to 5.5 V
1.05VDDA1 1.1VDDA1
1.15VDDA1 V
VI(os)
DC offset voltage at
minimum input voltage
with respect to VDACNL
−
−
60
mV
Rext = 5 kΩ
ViADR
input voltage level
−0.3
−
+7.5
V
α
decimation filter attenuation
20
−
−
dB/Dec
fco
pass-band cut-off frequency at −3 dB
−
29
−
kHz
fsr
sample rate after
decimation
radio mode
−
38
76
kHz
audio mode
−
38
76
kHz
1.1
−
−
V
48
60
72
kΩ
−
−71
−61
dB
Analog AC inputs: pins MPX, AM, TAPE and AUX
Vi(con, rms)
maximum conversion input
voltage level (RMS value)
Ri
input resistance
THD
total harmonic distortion
S/NADC
signal-to-noise ratio for
ADC
THD < 1%
fi = 1 kHz; Vi = 1 V (RMS)
fi = 1 kHz; Vi = 1 V (RMS)
−
0.03
0.09
%
not multiplexed;
B = 19 kHz;
Vi = 1 V (RMS)
81
85
−
dB
multiplexed; unweighted;
B = 19 kHz;
Vi = 1 V (RMS)
72
76
−
dB
S/NAM
signal-to-noise ratio for AM
B = 5 kHz;
Vi = 200 mV (RMS);
(M = 30%)
68
72
−
dB
S/NFM(mon)
signal-to-noise-ratio for FM
mono
Vi = 200 mV (RMS);
(∆f = 22.5 kHz);
B = 19 kHz; unweighted;
(M = 30%)
69
72
−
dB
S/NFM(st)
signal-to-noise-ratio for FM
stereo
Vi = 200 mV (RMS);
(∆f = 22.5 kHz);
B = 19 kHz; unweighted;
(M = 30%)
60
63
−
dB
1997 May 30
30
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SYMBOL
PARAMETER
SAA7707H
CONDITIONS
MIN.
TYP.
MAX.
UNIT
S/NTAPE
signal-to-noise-ratio for
TAPE (+10 kHz RC)
B = 19 kHz;
Vi = 1 V (RMS);
unweighted
70
74
−
dB
S/NAUX
signal-to-noise-ratio for
AUX
B = 19 kHz;
Vi = 1 V (RMS);
unweighted
72
76
−
dB
α19
carrier and harmonic
pilot signal fi = 19 kHz
suppression at the output
no modulation
with and without modulation
(for 19 kHz including notch)
−
81
−
dB
−
98
−
dB
carrier and harmonic
subcarrier; fi = 38 kHz
suppression at the output
no modulation
with and without modulation
−
83
−
dB
−
91
−
dB
carrier and harmonic
subcarrier; fi = 57 kHz
suppression at the output
no modulation
with and without modulation
−
83
−
dB
−
96
−
dB
carrier and harmonic
subcarrier; fi = 76 kHz
suppression at the output
no modulation
with and without modulation
−
84
−
dB
−
94
−
dB
IMα10
intermodulation
fmod = 10 kHz;
fspur = 1 kHz; note 1
77
−
−
dB
IMα3
intermodulation
fmod = 13 kHz;
fspur = 1 kHz; note 1
76
−
−
dB
α38
α57
α76
α57(VF)
traffic radio suppression
fi = 57 kHz; note 2
−
110
−
dB
α67
subsidiary communication
authority (SCA)
fi = 67 kHz; note 3
−
110
−
dB
α114
adjacent channel
interference
fi = 114 kHz; note 4
−
110
−
dB
α190
adjacent channel
interference
fi = 190 kHz; note 4
−
110
−
dB
Vpilot(rms)
pilot threshold voltage at
pin 42
stereo ON
−
35.6
−
mV
stereo OFF
−
35.5
−
mV
HYS
hysteresis level of pilot
voltage
−
0
−
dB
fi
input frequency range MPX −3 dB; ADC via bitstream
test output
0
−
55
kHz
αcs
FM stereo channel
separation
fi = 1 kHz
40
45
−
dB
fi = 10 kHz
25
30
−
dB
fresFM
audio frequency response
FM
at −3 dB via DSP at DAC
output
16
−
−
kHz
|∆Gv|
channel unbalance
left/right TAPE, AUX, FM
and AM
−
−
0.5
dB
1997 May 30
31
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SYMBOL
αcs
PARAMETER
CONDITIONS
channel separation TAPE
and AUX
fres
frequency response TAPE
and AUX
αct
crosstalk between inputs
PSRR
SAA7707H
fi = 1 kHz
MIN.
40
TYP.
MAX.
UNIT
45
−
dB
fi = 10 kHz
25
30
−
dB
fi = 1 kHz, software
compensated
−
50
−
dB
at −3 dB
18
−
−
kHz
fi = 1 kHz
65
−
−
dB
fi = 15 kHz
50
−
−
dB
power supply ripple
rejection for MPX and RDS
ADCs
output via
ADC input shorted;
fripple = 1 kHz;
Vripple = 100 mV (peak);
CVrefMPX = 22 µF;
CVrefRDS = 22 µF;
CVDACPM = 10 µF
35
45
−
dB
power supply ripple
rejection for ADC level
output via DAC;
ADC input shorted;
fripple = 1 kHz;
Vripple = 100 mV (peak);
CVrefRDS = 22 µF
29
39
−
dB
THD < 1%
1.1
−
−
V
I2S-bus;
Analog AC inputs: RDS
Vi(rms)
input voltage level
(RMS value)
Ri
input resistance RDS ADC
48
60
72
kΩ
αpilot
pilot attenuation RDS
50
−
−
dB
α
nearby selectivity RDS
neighbouring channel at
200 kHz distance
61
−
−
dB
αmux
multiplex attenuation RDS
mono
70
−
−
dB
stereo
40
−
−
dB
maximum crystal
deviation of 100 ppm
−
−
6
Hz
∆fosc
allowable frequency
deviation 57 kHz RDS
Analog outputs: VDDD = VDDA = VDDO
=5
V; Tamb = 25 °C
PSRR
power supply ripple
rejection DACs
input via I2S-bus;
fripple = 1 kHz;
Vripple = 100 mV (peak);
CVref = 22 µF
35
42
−
dB
∆Vo(DAC)
maximum deviation in
output level (plus or minus)
of the 4 DAC current
outputs
with respect to the
average of the 4 outputs;
tolerance Ro < 0.1%;
full-scale output
−
−
0.38
dB
αct
crosstalk between all
outputs in the audio band
two outputs digital silence
other two maximum
volume; faudio = 10 kHz
−
−
−60
dB
GO
DC open loop gain of
operational amplifiers
−
85
−
dB
1997 May 30
32
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SYMBOL
PARAMETER
SAA7707H
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Zo
AC output impedance of
operational amplifiers
RL > 5 kΩ; note 5
−
1.5
−
Ω
fug
unity gain frequency
operational amplifiers
open loop
−
4.5
−
MHz
Io(sc)
short-circuit current output
output short-circuited to
ground
−
10
25
mA
RES
DAC resolution
−
18
−
bits
(THD + N)/S DAC total harmonic
distortion plus
noise-to-signal ratio of
DAC and operational
amplifiers
fi = 1 kHz;
Vo = 2.8 V (p-p)
(full-scale)
−
−70
−60
dB
fi = 1 kHz; at −60 dB;
A-weighted
−
−38
−28
dBA
DR
dynamic range
Vref(o) = 4.46 V (p-p);
fi = 1 kHz; at −60 dB;
A-weighted
92
102
−
dBA
DS
digital silence
Vref(o) = 4.46 V (p-p);
fi = 20 Hz to 17 kHz;
A-weighted
−
−110
−100
dBA
digital silence noise level at
output
RMS value; B = 20 kHz,
A-weighted
−
5
15
µV
IM
intermodulation
distortion/comparator
fi = 60 Hz and 7 kHz;
ratio 4 : 1
−
−70
−55
dB
fs(max)
maximum sample
frequency
fxtal = 36.9 MHz
48
−
−
kHz
B
bandwidth of DAC
fs = fs − 3 dB
−
1⁄
−
kHz
CL
allowed load capacitance
on DAC voltage outputs
−
−
2.5
nF
RL
allowed load resistor on
DAC voltage outputs
2
−
−
kΩ
2fs
Crystal oscillator at: VDDX = 5 V; Tamb = 25 °C
fxtal
crystal frequency
−
36.860
−
MHz
αf
spurious frequency
attenuation
20
−
−
dB
I64
output current pin 64
−
−
1
mA
Gm
transconductance
Vxtal
voltage across crystal
CL
load capacitance
Rxtal
allowed resistance loss of
crystal
1997 May 30
4
8
−
mS
−
500
−
mV
note 6
−
10
−
pF
Cp = 5 pF; Cx1 = 10 pF;
Cx2 = 10 pF
−
20
100
Ω
at start-up
33
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SYMBOL
PARAMETER
SAA7707H
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Timing at: VDDD = VDDA = VDDA1 = VDDX = 5 V; Tamb = 25 °C
fxtal
crystal frequency
−
36.860
−
MHz
δfxtal/fxtal
frequency adjustment
tolerance
−30
−
+30
ppm
δfxtal/∆T
drift over temperature range
−30
−
+30
ppm
fi(max)
maximum input frequency
of I2C-bus clock
100
−
−
kHz
VDDD = 4.75 V;
Tamb = 85 °C
−
−
4.75 +
0.28CL
ns
VDDD = 5.5 V;
Tamb = −40 °C
1.302 +
0.101CL
−
−
ns
VDDD = 4.75 V;
Tamb = 85 °C
−
−
6.44 +
0.36CL
ns
VDDD = 5.5 V;
Tamb = −40 °C
0.971 +
0.115CL
−
−
ns
112
−
−
ns
I2S-bus inputs and outputs (see Fig.18)
tr
tf
rise time
fall time
tHC
clock output HIGH time
tLC
clock output LOW time
112
−
−
ns
tdWS
Word Select delay time
0
−
−
ns
th
data hold time
0
−
−
ns
ts
data set-up time
25
−
−
ns
td
data delay time
0
−
5
ns
ta
data out access time
−
−
5 + 0.5CL
ns
−
1187.5
−
Hz
RDS; (see Figs.14 and 15)
fclk
nominal clock frequency
RDS-clock
ts
clock set-up time
100
−
−
µs
Tcy
periodic time
−
842
−
µs
tHC
clock HIGH time
220
−
640
µs
tLC
clock LOW time
220
−
640
µs
th
data hold time
100
−
−
µs
tw
wait time
1
−
−
µs
tpb
periodic time
2
−
−
µs
tHC
clock HIGH time
1
−
−
µs
tLC
clock LOW time
1
−
−
µs
input frequency on pin 40
−
−
22
MHz
Other
fEXCLK
1997 May 30
34
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SAA7707H
Notes to the AC characteristics
1. Intermodulation suppression (BFC: Beat Frequency Components).
a) α2 = Vo(signal) (at 1 kHz)/Vo(spurious) (at 1 kHz); fs = (2 × 10 kHz) − 19 kHz.
b) α3 = Vo(signal) (at 1 kHz)/Vo(spurious) (at 1 kHz); fs = (3 × 13 kHz) − 38 kHz.
c) Measured with 91% mono signal; fmod = 10 or 13 kHz; 9% pilot signal.
2. Traffic radio (VF) suppression.
a) α57(VF) = Vo(signal) (at 1 kHz)/Vo(spurious) (at 1 kHz ±23 Hz).
b) Measured with 91% stereo signal; fmod = 1 kHz; 9% pilot signal.
c) 5% traffic subcarrier (f = 57 kHz; fmod = 23 Hz AM, m = 0.6).
3. SCA (Subsidiary Communication Authorization).
a) α67 = Vo(signal) (at 1 kHz)/Vo(spurious) (at 9 kHz); fs = (2 × 38 kHz) − 67 kHz.
b) Measured with 81% mono signal; fmod = 1 kHz; 9% pilot signal.
c) 10% SCA subcarrier (fs = 67 kHz, unmodulated).
4. ACI (Adjacent Channel Interference).
a) α114 = Vo(signal) (at 1 kHz)/Vo(spurious) (at 4 kHz); fs = 110 kHz − (3 × 38 kHz).
b) α190 = Vo(signal) (at 1 kHz)/Vo(spurious) (at 4 kHz); fs = 186 kHz − (5 × 38 kHz).
c) Measured with 90% mono signal; fmod = 1 kHz; 9% pilot signal; 1% spurious signal (fs = 110 kHz or 186 kHz,
unmodulated).
5. RL is the AC impedance of the external circuitry at 1 kHz connected to the audio outputs in the application. There is
also no DC current flowing through RL.
6. The load capacitance is the sum of the series connection of C × 1 and C × 2 (see Fig.11) and the parasitic parallel
capacitor of the crystal Cp.
1997 May 30
35
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
acknowledge on the last byte that has been clocked out of
the slave. In this event, the transmitter must leave the data
line HIGH, to enable the master to generate a STOP
condition (see Fig.19).
15 I2C-BUS CONTROL AND COMMANDS
15.1
Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-line communication between
different ICs or modules. The two lines are a serial data
line (SDA) and a serial clock line (SCL). Both lines must be
connected to VDDD via a pull-up resistor when connected
to the output stages of a microcontroller. Data transfer can
only be initiated when the bus is not busy.
15.2
15.6
Bit transfer
15.6.2
START and STOP conditions
Table 6
Slave address
MSB
0
LSB
0
1
1
1
0
A0
R/W
The sub-address bit A0 corresponds to the hardware
address pin A0, which allows the device to have 1 of 2
different addresses. The A0 input is also used in test mode
as a serial input of the test control block.
Data transfer
A device generating a message is a ‘transmitter’, a device
receiving a message is the ‘receiver’.
The device that controls the message is the ‘master’ and
the devices that are controlled by the master are the
‘slaves’ (see Fig.18).
15.6.3
CDSP WRITE CYCLES
The I2C-bus configuration for a WRITE cycle is illustrated
in Fig.22. The WRITE cycle is used to write in the IAC
register, the input selector control register and to initialize
or update coefficient values in XRAM or YRAM. The data
is transferred from the I2C-bus register to the DSP register
once every DSP cycle.
Acknowledge
The number of data bytes transferred between the START
and STOP conditions from transmitter to receiver is not
limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put
on the bus by the transmitter, whereas the master
generates an extra acknowledge-related clock pulse.
A slave receiver that is addressed must generate an
acknowledge after the reception of each byte. Also, a
master must generate an acknowledge after the reception
of each byte that has been clocked out of the slave
transmitter.
The I2C-bus interface circuitry in the SAA7707H requires
that the LOW period of the SCL line following the
acknowledge bit is at least 1/fs (in seconds); where fs is the
audio sampling frequency (in Hertz). This requirement
must be met for a single write operation and an
auto-incremental operation, but only applies to the
acknowledge bit following each DATA-L
(see Figs 20 and 21).
The data length is 2 or 3 bytes, depending on the
accessed memory. If the Y-memory is addressed the data
length is 2 bytes, If the X-memory is addressed the length
is 3 bytes. The slave receiver detects the address and
adjusts the byte length accordingly.
The device that acknowledges has to pull down the SDA
line during the acknowledge clock pulse, so that the SDA
line is stable LOW during the HIGH period of the
acknowledge-related clock pulse. Set-up and hold times
must be taken into account. A master receiver must signal
an end-of-data to the transmitter by not generating an
1997 May 30
SLAVE ADDRESS (A0 PIN)
The CDSP acts as a slave receiver or slave transmitter.
Therefore, the clock signal SCL is only an input signal.
The data signal SDA is a bi-directional line. The CDSP
slave address is shown in Table 6.
A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as the STOP condition (P) (see Fig.17).
15.5
ADDRESSING
Before any data is transmitted on the I2C-bus, the device
that should respond is addressed first. The addressing is
always done with the first byte transmitted after the START
procedure.
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the START condition (S).
15.4
I2C-bus format
15.6.1
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse, as changes in the data line
at this time will be interpreted as control signals.
The maximum clock frequency is 100 kHz (see Fig.16).
15.3
SAA7707H
36
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
15.6.4
SAA7707H
CDSP READ CYCLES
I2C-bus
The
configuration for a READ cycle is illustrated in Fig.23. The READ cycle is used to read data values from
XRAM or YRAM. The data is transferred from the DSP register to the I2C-bus register at execution of the MPI instruction
in the DSP program. Therefore, an MPI instruction should be added at least once every DSP cycle.
th
SDA
SCL
data line
stable;
data valid
change
of data
allowed
MBC621
Fig.16 Bit transfer on the I2C-bus.
handbook, full pagewidth
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
Fig.17 START and STOP conditions.
1997 May 30
37
MBC622
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SAA7707H
handbook, full pagewidth
SDA
MSB
acknowledgement
signal from receiver
acknowledgement
signal from receiver
byte complete;
interrupt within receiver
clock line held low while
interrupts are serviced
SCL
1
S
2
7
9
8
1
2
3-8
ACK
9
P
ACK
START
CONDITION
MBH177
Fig.18 Data transfer on the I2C-bus.
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
SCL FROM
MASTER
1
2
8
9
S
START
CONDITION
MBH178
Fig.19 Acknowledge on the I2C-bus.
1997 May 30
38
clock pulse for
acknowledgement
STOP
CONDITION
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SAA7707H
handbook, full pagewidth
SDA
SCL
1-7
8
9
1-7
8
9
1-7
8
9
P
DATA-H
ACK
DATA-M
ACK
DATA-L
ACK
STOP
condition
≥1/fs
minimum required LOW period
Fig.20 Minimum required SCL LOW period; single write.
1997 May 30
39
MGK426
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
1-7
8
DATA-H
9
ACK
1-7
8
DATA-M
9
ACK
1-7
8
DATA-L
1-7
9
ACK
8
DATA-H
9
ACK
1-7
8
DATA-M
9
ACK
1-7
8
DATA-L
9
ACK
40
≥1/fs
MGK427
Philips Semiconductors
SCL
Car radio Digital Signal Processor (CDSP)
k, full pagewidth
1997 May 30
SDA
minimum required LOW period
Preliminary specification
SAA7707H
Fig.21 Minimum required SCL LOW period; auto-incremental write.
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
K
ADDR L
A
C
K
DATA H
A
C
K
DATA M
A
C
K
DATA L
A
C P
K
auto increment if repeated n-groups of 3 (2) bytes
address
MGD568
R/W
Fig.22 Master transmitter writes to CDSP registers.
41
A
S 0 0 1 1 1 0 0 0 C
ADDR H
K
A
C
K
ADDR L
A
A
C S 0 0 1 1 1 0 0 1 C
K
K
DATA H
A
C
K
DATA M
A
C
K
DATA L
A
C P
K
Philips Semiconductors
ADDR H
Car radio Digital Signal Processor (CDSP)
1997 May 30
A
C
K
A
S 0 0 1 1 1 0 0 0 C
auto increment if repeated n-groups of 3 (2) bytes
address
R/W
R/W
MGA808 - 1
Fig.23 Master transmitter reads from CDSP registers.
A detailed description of the software feature, complete with operating instructions, is provided in the application manual.
The application diagram illustrated in Figs. 24 and 25 must be considered as one of the examples of a (limited) application of the SAA7707H.
For example, in the application shown, the I2S-bus inputs of the DCC and CD are not used.
SAA7707H
17 APPLICATION INFORMATION
Preliminary specification
16 SOFTWARE DESCRIPTION
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SAA7707H
10 µH
handbook, full pagewidth
+5 V
L1
C1
4.7 µF
BLM21A10
+5 V
+5 V
220 µH
L2
C2
100 µF
L3
+5 V
C3
100 nF
C21
100 nF
470 nF 4.7 kΩ
C8
C15
R4
CDIN-L
470 nF 4.7 kΩ
C9
C16
R5
CASS-R
470 nF 4.7 kΩ
C10
C17
R6
CASS-L
470 nF 4.7 kΩ
C11
R7
RADIO-F (AM)
3.3 kΩ
C12
R7
MPX (FM)
3.3 kΩ
C13
4
3
330
pF
72
71
330
pF
74
72
3.3
nF
3.3
nF C18
330
pF
150
pF
75
220
nF
C19
76
79
1 µF
29
VSSD9
41
VSSD8
34
VSSD7
VSSD6
VSSD5
VSSD4
VSSD3
VSSD2
VSSD1
VDDA1
VSSG
55
VrefMPX
VrefRDS
MPXRDS
AM
FM
SAA7707H
AUXR
AUXL
TAPER
AUXR
AMAF
FMMPX
FMRDS
32
33
30
60
R9
100 Ω
C22
220
pF
C23
R10
100 Ω
RDSCLK
MBH179
65
61
R11
100 Ω
220
pF
100
nF
BLM21A10 L4
R12
100 Ω
RDSDAT
42
64
63
R13
C24
+5 V (e.g.)
L5
4.7 µH
C25
4.7 nF
Fig.24 Application diagram (continued in Fig.25).
1997 May 30
54
100 kΩ
X1
36.86 MHz
C26
10 pF
C27
10 pF
66
CDCLK
CDIN-R
1 nF
62
51
VSSX
4.7 kΩ
C7
R3
80
50
XTALI
C14
22 µF
R2
22
XTALO
LEVEL (AM, FM)
22 µF
VDACNM
5
VDDX
C6
70
69
RDSDAT
C5
VDACPM
VSSA1
78
68
RDSCLK
10 µF
67
TSCAN
C4
CINT
77
1 kΩ
1
SHTCB
+5 V
2
RTCB
R1
VDACNL
C20
1 nF
23
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
RDSMUTE
8
15
14
6
MICROCONTROLLER
VSSA
7
VSSO
43
VDDA
42
VDDD1
MUTE
45
MSS/P
44
DEEM
53
C35
100 nF
R17
220 Ω
VDDO
R16
220 Ω
VDDD5
52
VDDD4
49
VDDD3
VDDD2
56
C36
22 µF
C34
100 pF
C33
100 pF
C32
100 µF
C31
100 nF
+5 V
D1
BAT54
PAUSE
STEREO
BLM32A07
book, full pagewidth
+5 V
L6
SAA7707H
POM
FIOL
FVOL
C37
4.7 µF
21
18
19
R18
2.7 KΩ
C38
2.2 nF
R23
100 Ω
FIOR
FVOR
16
17
R19
2.7 KΩ
C39
2.2 nF
R24
100 Ω
RIOL
SAA7707H
RVOL
11
12
R20
2.7 KΩ
C40
2.2 nF
R25
100 Ω
RIOR
RVOR
EXCLK
24
25
48
47
46
59
57
58
35
36
28
27
37
R14
220 Ω
38
DSPRESET
A0
SDA
SCL
EXWS
EXDAT1
EXDAT2
EXSCL
EXDAT
VSSD10
TEST1
TEST2
DCCCLK
DCCWS
DCCDAT
CDDAT
DCWS
Vref
39
31
R15
220 Ω
C28
100 pF
9
10
R21
2.7 KΩ
C41
2.2 nF
R26
40
100 Ω
20
Iref(int) 13
R22
18 kΩ
C42
22 µF
26
C30
220 nF
C29
100 pF
SCL SDA
MBH180
Fig.25 Application diagram (continued from Fig.24).
1997 May 30
43
C44 2.2 µF
FRONT-LEFT
C43
10 nF
C46 2.2 µF
FRONT-RIGHT
C45
10 nF
C48 2.2 µF
REAR-LEFT
C47
10 nF
C50 2.2 µF
REAR-RIGHT
C49
10 nF
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SAA7707H
18 PACKAGE OUTLINE
QFP80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SOT318-2
c
y
X
64
A
41
40
65
ZE
e
E HE
A
A2
(A 3)
A1
θ
wM
pin 1 index
Lp
bp
80
L
25
detail X
24
1
wM
bp
e
ZD
v M A
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
v
w
y
mm
3.2
0.25
0.05
2.90
2.65
0.25
0.45
0.30
0.25
0.14
20.1
19.9
14.1
13.9
0.8
24.2
23.6
18.2
17.6
1.95
1.0
0.6
0.2
0.2
0.1
Z D (1) Z E (1)
1.0
0.6
1.2
0.8
θ
o
7
0o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
95-02-04
97-08-01
SOT318-2
1997 May 30
EUROPEAN
PROJECTION
44
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SAA7707H
19 SOLDERING
19.3
19.1
Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
If wave soldering cannot be avoided, the following
conditions must be observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
19.2
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
Reflow soldering
Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
QFP100 (SOT382-1) or QFP160 (SOT322-1).
Reflow soldering techniques are suitable for all QFP
packages.
The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9397 750 00192).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
19.4
Repairing soldered joints
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
1997 May 30
Wave soldering
45
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SAA7707H
20 DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
21 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
22 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1997 May 30
46
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
NOTES
1997 May 30
47
SAA7707H
Philips Semiconductors – a worldwide company
Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Tel. +61 2 9805 4455, Fax. +61 2 9805 4466
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101, Fax. +43 1 60 101 1210
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773
Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 689 211, Fax. +359 2 689 102
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Colombia: see South America
Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,
Tel. +45 32 88 2636, Fax. +45 31 57 0044
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615800, Fax. +358 9 61580920
France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex,
Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 23 53 60, Fax. +49 40 23 536 300
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,
Tel. +30 1 4894 339/239, Fax. +30 1 4814 240
Hungary: see Austria
India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.
Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722
Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,
Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381
Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. +48 22 612 2831, Fax. +48 22 612 2327
Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,
Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. +27 11 470 5911, Fax. +27 11 470 5494
South America: Rua do Rocio 220, 5th floor, Suite 51,
04552-903 São Paulo, SÃO PAULO - SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 829 1849
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 3 301 6312, Fax. +34 3 301 4107
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 632 2000, Fax. +46 8 632 2745
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2686, Fax. +41 1 481 7730
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. +90 212 279 2770, Fax. +90 212 282 6707
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1997
SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
547027/1200/02/pp48
Date of release: 1997 May 30
Document order number:
9397 750 02261