FUNCTIONAL BLOCK DIAGRAM HS/VS HDCP KEYS FIELD/DE 36 COMPONENT PROCESSOR LLC DATA HDMI1 TMDS DDC DEEP COLOR HDMI Rx 4 I2S S/PDIF MCLK SCLK LRCLK ADV7610 HS VS/FIELD DE LLC 24-BIT YCbCr/RGB LRCLK I2S MCLK SCLK 10775-001 High-Definition Multimedia Interface (HDMI®) All mandatory and additional 3D video formats supported Extended colorimetry, including sYCC601, Adobe RGB, Adobe YCC 601, and xvYCC extended gamut color CEC 1.4-compatible HDMI receiver 165 MHz maximum transition-minimized differential signaling (TMDS) clock frequency 24-bit output pixel bus High-bandwidth Digital Content Protection (HDCP) 1.4 support with internal high definition copy protocol (HDCP) keys HDCP repeater support: up to 127 KSVs supported Integrated consumer electronics control (CEC) controller Programmable HDMI equalizer 5 V detect and Hot Plug™ assert for HDMI port Audio support S/PDIF (IEC 60958-compatible) digital audio HDMI audio extraction support Advanced audio mute feature I2S, 4 streams for 8 channels General Interrupt controller with two interrupt outputs Standard identification (STDI) circuit Highly flexible 24-bit pixel output interface Internal extended display identification data (EDID) RAM Any-to-any 3 × 3 color space conversion (CSC) matrix 2-layer printed circuit board (PCB) design supported 76-ball, 6 mm × 6 mm, chip-scale package BGA OUTPUT MUX FEATURES OUTPUT MUX Data Sheet Low Power, 165 MHz HDMI Receiver ADV7610 Figure 1. APPLICATIONS Portable applications Pico projectors Digital video cameras Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2012 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADV7610 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Power Supply Sequencing ............................................................. 10 Applications ....................................................................................... 1 Power-Up Sequence ................................................................... 10 Functional Block Diagram .............................................................. 1 Power-Down Sequence .............................................................. 10 Revision History ............................................................................... 2 Functional Overview...................................................................... 11 General Description ......................................................................... 3 HDMI Receiver........................................................................... 11 Detailed Functional Block Diagram .......................................... 3 Component Processor (CP) ...................................................... 11 Specifications..................................................................................... 4 Other Features ............................................................................ 11 Electrical Characteristics ............................................................. 4 Pixel Input/Output Formatting .................................................... 12 Data and I C Timing Characteristics ......................................... 5 Pixel Data Output Modes Features .......................................... 12 Absolute Maximum Ratings ............................................................ 7 Outline Dimensions ....................................................................... 14 Package Thermal Performance ................................................... 7 Ordering Guide .......................................................................... 14 2 ESD Caution .................................................................................. 7 Pin Configuration and Function Descriptions ............................. 8 REVISION HISTORY 12/12—Revision 0: Initial Version Rev. 0 | Page 2 of 16 Data Sheet ADV7610 GENERAL DESCRIPTION The ADV7610 is offered in professional (no HDCP) and industrial versions. The operating temperature range is −40°C to +85°C. The ADV7610 is a high quality, single input HDMI-capable receiver. It incorporates an HDMI-capable receiver that supports all mandatory 3D TV defined in HDMI specification. The ADV7610 supports formats up to UXGA 60 Hz at eight bits. It integrates a CEC controller that supports the capability discovery and control (CDC) feature. The ADV7610 has a 4-channel stereo audio output port for the audio data extracted from the HDMI stream. The HDMI receiver has an advanced mute controller that prevents audible extraneous noise in the audio output. The HDMI port has dedicated 5 V detect and Hot Plug assert pins. The HDMI receiver also includes an integrated equalizer that ensures the robust operation of the interface with long cables. The ADV7610 contains one main component processor (CP) that processes the video signals from the HDMI receiver. It provides features such as contrast, brightness, saturation adjustments, STDI detection block, free run, and synchronization alignment controls. Fabricated in an advanced CMOS process, the ADV7610 is provided in a 6 mm × 6 mm, 76-ball CSP_BGA, RoHS-compliant package and is specified over the −40°C to +85°C temperature range. The following audio formats are accessible: DETAILED FUNCTIONAL BLOCK DIAGRAM DPLL SCL SDA CEC RXA_5V HPA_A/INT2* DDCA_SDA DDCA_SCL RXA_C± RXA_0± RXA_1± RXA_2± CEC CONTROLLER CONTROL INTERFACE I2C CONTROL AND DATA 5V DETECT AND HPD CONTROLLER COMPONENT PROCESSOR HDCP EEPROM PLL SAMPLER HDCP ENGINE A B C DATA PREPROCESOR AND COLORSPACE CONVERSION PACKET/ INFOFRAME MEMORY PACKET PROCESSOR MUTE AUDIO PROCESSOR INT1 INT2* 4 ADV7610 *INT2 CAN BE OUTPUT ON ONE OF THE FOLLOWING PINS ONLY: SCLK/INT2, MCLK/INT2, OR HPA_A/INT2. Figure 2. Detailed Functional Block Diagram Rev. 0 | Page 3 of 16 P0 TO P7 P8 TO P15 P16 TO P23 LLC HS VS/FIELD/ALSB DE INTERRUPT CONTROLLER (INT1, INT2) HDMI PROCESSOR EDID REPEATER CONTROLLER EQUALIZER BACKEND COLORSPACE CONVERSION 12 12 12 I2S0 TO I2S3 LRCLK SCLK/INT2* MCLK/INT2* 10775-002 XTALP XTALN OUTPUT FORMATTER • Four streams from the I2S serializer (eight channels) A stream from the S/PDIF serializer (two uncompressed channels or N compressed channels, for example, AC3) A DST stream AUDIO OUTPUT FORMATTER • • ADV7610 Data Sheet SPECIFICATIONS DVDD = 1.71 V to 1.89 V, DVDDIO = 3.14 V to 3.46 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.14 V to 3.46 V, CVDD = 1.71 V to 1.89 V, TMIN to TMAX = −40°C to +85°C, unless otherwise noted. ELECTRICAL CHARACTERISTICS Table 1. Parameter DIGITAL INPUTS 1 Input High Voltage Input Low Voltage Input Current Symbol Test Conditions/Comments Min VIH VIH VIL VIL IIN XTALN and XTALP Other digital inputs XTALN and XTALP Other digital inputs RESET pin Other digital inputs 1.2 2 Input Capacitance DIGITAL INPUTS (5 V TOLERANT)1, 2 Input High Voltage Input Low Voltage Input Current DIGITAL OUTPUTS1 Output High Voltage Output Low Voltage High Impedance Leakage Current CIN Output Capacitance POWER REQUIREMENTS 3 Digital Core Power Supply Digital I/O Power Supply PLL Power Supply Terminator Power Supply Comparator Power Supply Digital Core Supply Current Digital I/O Supply Current PLL Supply Current Terminator Supply Current Comparator Supply Current POWER-DOWN CURRENTS 4 Digital Core Supply Current Digital I/O Supply Current PLL Supply Current Terminator Supply Current Comparator Supply Current Power-Up Time COUT ±45 ±10 VIH VIL IIN 2.6 VOH VOL ILEAK 2.4 DVDD DVDDIO PVDD TVDD CVDD IDVDD IDVDDIO IPVDD ITVDD ICVDD IDVDD_PD IDVDDIO_PD IPVDD_PD ITVDD_PD ICVDD_PD tPWRUP Typ −82 VS/FIELD/ALSB pin HPA_A/INT2 pin Other Power-Down Mode 1 Power-Down Mode 1 Power-Down Mode 1 Power-Down Mode 1 Power-Down Mode 1 Unit 0.4 0.8 ±60 10 V V V V µA µA pF 0.8 +82 V V µA 20 V V µA µA µA pF 1.8 3.3 1.8 3.3 1.8 95.7 12.9 30.7 50.9 95.8 1.89 3.46 1.89 3.46 1.89 188.1 178.5 36.9 57.6 114.4 V V V V V mA mA mA mA mA 0.2 1.3 1.5 0.1 1.3 25 0.5 1.7 1.8 0.3 1.7 mA mA mA mA mA ms ±35 0.4 ±60 ±82 10 1.71 3.14 1.71 3.14 1.71 UXGA 60 Hz at eight bits UXGA 60 Hz at eight bits UXGA 60 Hz at eight bits UXGA 60 Hz at eight bits UXGA 60 Hz at eight bits Max Data guaranteed by characterization. The following pins are 5 V tolerant: DDCA_SCL, DDCA_SDA, and RXA_5V. 3 Maximum current consumption values are recorded with maximum rated voltage supply levels, Moire X video pattern, and at maximum rated temperature. 4 Power-Down Mode 0 (I/O map, Register 0x0C = 0x62), ring oscillator powered down (HDMI map, Register 0x48 = 0x01), and DDC pads off (HDMI map, Register 0x73 = 0x01). 1 2 Rev. 0 | Page 4 of 16 Data Sheet ADV7610 DATA AND I2C TIMING CHARACTERISTICS Table 2. Parameter CLOCK AND CRYSTAL Crystal Frequency, XTALP Crystal Frequency Stability LLC Frequency Range 1 I2C PORTS SCL Frequency SCL Minimum Pulse Width High 2 SCL Minimum Pulse Width Low2 Start Condition Hold Time2 Start Condition Setup Time2 SDA Setup Time2 SCL and SDA Rise Time2 SCL and SDA Fall Time2 Stop Condition Setup Time2 RESET FEATURE Symbol Test Conditions/Comments I2S PORT, MASTER MODE SCLK Mark:Space Ratio2 LRCLK Data Transition Time2 LRCLK Data Transition Time2 I2S Data Transition Time2 I2S Data Transition Time2 Typ Max Unit ±50 165 MHz ppm MHz 28.63636 13.5 400 t1 t2 t3 t4 t5 t6 t7 t8 0.6 kHz ns µs ns ns ns ns ns µs 5 ms 600 1.3 600 600 100 300 300 RESET Pulse Width CLOCK OUTPUTS LLC Mark:Space Ratio2 DATA AND CONTROL OUTPUTS 3 Data Output Transition Time2, 4 Min t9:t10 45:55 t11 t12 End of valid data to negative clock edge Negative clock edge to start of valid data t15:t16 t17 t18 t19 t20 End of valid data to negative SCLK edge Negative SCLK edge to start of valid data End of valid data to negative SCLK edge Negative SCLK edge to start of valid data 1.0 0.0 45:55 Maximum LLC frequency is limited by the clock frequency of UXGA 60 Hz at eight bits. Data guaranteed by characterization. 3 With the DLL block on the output clock bypassed. 4 DLL bypassed on the clock path. 1 2 Rev. 0 | Page 5 of 16 55:45 % duty cycle 2.2 0.3 ns ns 55:45 10 10 5 5 % duty cycle ns ns ns ns ADV7610 Data Sheet Timing Diagrams t5 t3 t3 SDA t6 t1 t2 t4 t7 10775-003 SCL t8 2 Figure 3. I C Timing t9 t10 LLC t11 10775-004 t12 P0 TO P23, HS, VS/FIELD/ALSB, DE Figure 4. Pixel Port and Control SDR Output Timing t15 SCLK t16 t17 LRCLK t18 t19 MSB MSB – 1 t20 I2S I2S MODE I2S RIGHT-JUSTIFIED MODE t19 MSB MSB – 1 t20 t19 MSB LSB t20 Figure 5. I2S Timing Rev. 0 | Page 6 of 16 10775-005 I2S LEFT-JUSTIFIED MODE Data Sheet ADV7610 ABSOLUTE MAXIMUM RATINGS PACKAGE THERMAL PERFORMANCE Table 3. Parameter DVDD to GND PVDD to GND DVDDIO to GND CVDD to GND TVDD to GND Digital Inputs Voltage to GND 5 V Tolerant Digital Inputs to GND1 Digital Outputs Voltage to GND XTALP, XTALN SCL/SDA Data Pins to DVDDIO Maximum Junction Temperature (TJ MAX) Storage Temperature Range Infrared Reflow Soldering (20 sec) 1 Rating 2.2 V 2.2 V 4.0 V 2.2 V 4.0 V GND − 0.3 V to DVDDIO + 0.3 V 5.3 V GND − 0.3 V to DVDDIO + 0.3 V GND − 0.3 V to PVDD + 0.3 V DVDDIO − 0.3 V to DVDDIO + 3.6 V 125°C −60°C to +150°C 260°C To reduce power consumption when using the ADV7610, turn off the unused sections of the part. Due to the PCB metal variation and, therefore, variation in PCB heat conductivity, the value of θJA may differ for various PCBs. The most efficient measurement solution is obtained using the package surface temperature to estimate the die temperature because this eliminates the variance associated with the θJA value. Do not exceed the maximum junction temperature (TJ MAX) of 125°C. The following equation calculates the junction temperature using the measured package surface temperature, and it applies only when a heat sink is not used on the device under test (DUT): TJ = TS + (ΨJT × WTOTAL) where: TS is the package surface temperature (°C). ΨJT = 0.4°C/W for the 76-ball CSP_BGA. WTOTAL = ((PVDD × IPVDD) + (0.05 × TVDD × ITVDD) + (CVDD × ICVDD) + (DVDD × IDVDD) + (DVDDIO × IDVDDIO)) The following inputs are 3.3 V inputs but are 5 V tolerant: DDCA_SCL, DDCA_SDA, and RXA_5V. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. where 0.05 is 5% of the TVDD power that is dissipated on the device itself. ESD CAUTION Rev. 0 | Page 7 of 16 ADV7610 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 A HPA_A/ INT2 RXA_5V DDCA_SCL PVDD XTALN XTALP INT1 MCLK/ INT2 SCLK/ INT2 DVDD B TVDD TVDD DDCA_SDA CEC CS RESET SDA SCL LRCLK DVDD C RXA_C+ RXA_C– I2S3 I2S1 D RXA_0+ RXA_0– GND DVDD I2S2 I2S0 E RXA_1+ RXA_1– GND DVDD VS/ FIELD/ ALSB DE F RXA_2+ RXA_2– GND DVDDIO HS P0 G CVDD CVDD GND DVDDIO P1 P2 H P23 P22 P3 P4 J P21 P18 P16 P15 P13 P11 P9 P7 P5 DVDDIO K P20 P19 P17 LLC P14 P12 P10 P8 P6 DVDDIO GND GND 10775-006 GND GND Figure 6. Pin Configuration Table 4. Pin Function Descriptions Ball No. D4, D5, D6, E4, F4, G4, G5, G6 A1 Mnemonic GND Type Ground Description Ground. HPA_A/INT2 Miscellaneous digital G1, G2 B1, B2 F7, G7, J10, K10 A10, B10, D7, E7 A4 C2 C1 D2 D1 E2 E1 F2 F1 CVDD TVDD DVDDIO DVDD PVDD RXA_C− RXA_C+ RXA_0− RXA_0+ RXA_1− RXA_1+ RXA_2− RXA_2+ Power Power Power Power Power HDMI input HDMI input HDMI input HDMI input HDMI input HDMI input HDMI input HDMI input A dual function pin that can be configured to output a Hot Plug assert signal (for HDMI Port A) or an Interrupt 2 signal. HDMI Analog Block Supply Voltage (1.8 V). Terminator Supply Voltage (3.3 V). Digital I/O Supply Voltage (3.3 V). Digital Core Supply Voltage (1.8 V). PLL Supply Voltage (1.8 V). Digital Input Clock Complement of Port A in the HDMI Interface. Digital Input Clock True of Port A in the HDMI Interface. Digital Input Channel 0 Complement of Port A in the HDMI Interface. Digital Input Channel 0 True of Port A in the HDMI Interface. Digital Input Channel 1 Complement of Port A in the HDMI Interface. Digital Input Channel 1 True of Port A in the HDMI Interface. Digital Input Channel 2 Complement of Port A in the HDMI Interface. Digital Input Channel 2 True of Port A in the HDMI Interface. Rev. 0 | Page 8 of 16 Data Sheet ADV7610 Ball No. H1 H2 J1 K1 K2 J2 K3 J3 K4 J4 K5 J5 K6 J6 K7 J7 K8 J8 K9 J9 H10 H9 G10 G9 F10 E10 F9 E9 Mnemonic P23 P22 P21 P20 P19 P18 P17 P16 LLC P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 DE HS VS/FIELD/ALSB Type Digital video output Digital video output Digital video output Digital video output Digital video output Digital video output Digital video output Digital video output Digital video output Digital video output Digital video output Digital video output Digital video output Digital video output Digital video output Digital video output Digital video output Digital video output Digital video output Digital video output Digital video output Digital video output Digital video output Digital video output Digital video output Miscellaneous digital Digital video output Digital input/output D10, C10, D9, C9 I2S0 to I2S3 Miscellaneous digital A9 SCLK/INT2 Miscellaneous digital B9 A8 LRCLK MCLK/INT2 Miscellaneous digital Miscellaneous digital B8 B7 A7 SCL SDA INT1 Miscellaneous digital Miscellaneous digital Miscellaneous digital B6 RESET Miscellaneous digital A6 XTALP Miscellaneous analog A5 B4 B5 XTALN CEC CS Miscellaneous analog Digital input/output Miscellaneous digital A3 B3 A2 DDCA_SCL DDCA_SDA RXA_5V HDMI input HDMI input HDMI input Description Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Line Locked Output Clock for the Pixel Data the Range is 13.5 MHz to 162.5 MHz. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Data Enable. DE is a signal that indicates active pixel data. Horizontal Synchronization Output Signal. Vertical Synchronization Output Signal. Field Synchronization Output Signal in All Interlaced Video Modes. VS or FIELD can be configured for this pin. The ALSB allows selection of the I2C address. Audio Output Pins. These pins can be configured to output S/PDIF digital audio (S/PDIF) or I2S. A dual function pin that can be configured to output an audio serial clock or an Interrupt 2 signal. Audio Left/Right Clock. A dual function pin that can be configured to output an audio master clock or an Interrupt 2 signal. I2C Port Serial Clock Input. SCL is the clock line for the control port. I2C Port Serial Data Input/Output Pin. SDA is the data line for the control port. Interrupt 1. This pin can be active low or active high. When status bits change, this pin is triggered. The events that trigger an interrupt are under user configuration. System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset the ADV7610 circuitry. Input Pin for 28.63636 MHz Crystal or an External 1.8 V, 28.63636 MHz Clock Oscillator Source to Clock the ADV7610. Crystal Input. Input pin for 28.63636 MHz crystal. Consumer Electronic Control Channel. Chip Select (Bar). Pulling this line high causes the I2C state machine to ignore the I2C transmission. HDCP Slave Serial Clock Port A. DDCA_SCL is a 3.3 V input that is 5 V tolerant. HDCP Slave Serial Data Port A. DDCA_SDA is a 3.3 V input that is 5 V tolerant. 5 V Detect Pin for Port A in the HDMI Interface. Rev. 0 | Page 9 of 16 ADV7610 Data Sheet POWER SUPPLY SEQUENCING The recommended power-up sequence of the ADV7610 is to power up the 3.3 V supplies first, followed by the 1.8 V supplies. Hold reset low while the supplies are powered up. Alternatively, the ADV7610 can be powered up by asserting all supplies simultaneously. In this case, care must be taken while the supplies are being established to ensure that a lower rated supply does not rise above a higher rated supply level. POWER SUPPLY (V) POWER-UP SEQUENCE 3.3V 3.3V SUPPLIES 1.8V 1.8V SUPPLIES The ADV7610 supplies can be deasserted simultaneously as long as a higher rated supply does not fall below a lower rated supply. 3.3V SUPPLIES POWER-UP 1.8V SUPPLIES POWER-UP Figure 7. Recommended Power-Up Sequence Rev. 0 | Page 10 of 16 10775-007 POWER-DOWN SEQUENCE Data Sheet ADV7610 FUNCTIONAL OVERVIEW HDMI RECEIVER COMPONENT PROCESSOR (CP) The receiver supports all mandatory and many optional 3D formats. It supports HDTV formats up to UXGA at eight bits. The ADV7610 has an any-to-any 3 × 3 CSC matrix. The CSC block is placed in the output section of the component processor. The CSC enables YPrPb-to-RGB and RGB-to-YCrCb conversions. Many other standards of colorspace can be implemented using the colorspace converter. The HDMI-compatible receiver on the ADV7610 incorporates programmable equalization of the HDMI data signals. This equalization compensates for the high frequency losses inherent in HDMI and DVI cabling, especially at longer lengths and higher frequencies. It is capable of equalizing for cable lengths of up to 30 meters to achieve robust receiver performance. With the inclusion of HDCP, displays can receive encrypted video content. The HDMI interface of the ADV7610 allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewability of that authentication during transmission, as specified by the HDCP 1.4 protocol. The ADV7610 has a synchronization regeneration block to regenerate the DE based on the measurement of the video format being displayed and to filter the horizontal and vertical synchronization signals to prevent glitches. The HDMI receiver also supports TERC4 error detection for detection of corrupted HDMI packets following a cable disconnect. The HDMI receiver contains an audio mute controller that can detect a variety of conditions that may result in audible extraneous noise in the audio output. On detection of these conditions, the audio signal can be ramped to prevent audio clicks or pops. Audio output can be formatted to LPCM and IEC 61937. The HDMI receiver features include: • • • • • • • • • • • 162.5 MHz (UXGA at eight bits) maximum TMDS clock frequency 3D format support defined in the HDMI specification Integrated equalizer for cable lengths of up to 30 meters HDCP 1.4 Internal HDCP keys PCM audio packet support TDM I2S audio packet support Repeater support Internal EDID RAM Hot Plug assert output pin for an HDMI port CEC controller CP features include: • • • • • • • • 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and other formats Manual adjustments including gain (contrast) and offset (brightness), hue, and saturation Free run output mode that provides stable timing when no video input is present 162.5 MHz processing rate Contrast, brightness, hue, and saturation controls Standard identification enabled by STDI block RGB that can be color space converted to YCrCb and decimated to a 4:2:2 format for videocentric back-end IC interfacing DE output signal supplied for direct connection to an HDMI/DVI transmitter OTHER FEATURES The ADV7610 has HS, VS, FIELD, and DE output signals with programmable position, polarity, and width. The ADV7610 has programmable interrupt request output pins, including INT1 and INT2 (INT2 is accessible only via one of following pins: MCLK/INT2, SCLK/INT2, or HPA_A/INT2). It also features a low power-down mode. The I2C address of the main map is 0x98 after reset. This can be changed after reset to 0x9A if pull-up is attached to the VS/FIELD/ALSB pin and the I2C command SAMPLE_ALSB is issued. The ADV7610 is provided in a 6 mm × 6 mm, RoHS-compliant BGA package and is specified over the −40°C to +85°C temperature range. For more detailed product information about the ADV7610, contact the local Analog Devices, Inc., sales office. Rev. 0 | Page 11 of 16 ADV7610 Data Sheet PIXEL INPUT/OUTPUT FORMATTING The output section of the ADV7610 is highly flexible. The pixel output bus can support up to 24-bit 4:4:4 YCrCb. The pixel data supports both single data rate mode and double data rate mode. In SDR mode, a 16-/24-bit 4:2:2 or 24-bit 4:4:4 output is possible. In DDR mode, the pixel output port can be configured in an 8-/12bit 4:2:2 YCrCb or 24-bit 4:4:4 RGB. Bus rotation is supported. Table 5 and Table 6 outline the various output formats that are supported. All output modes are controlled via I2C. PIXEL DATA OUTPUT MODES FEATURES The output pixel port features include: • • • • • 8-/12-bit ITU-R BT.656 4:2:2 YCrCb with embedded time codes and/or HS, VS, and FIELD output signals 16-/24-bit YCrCb with embedded time codes and/or HS and VS/FIELD pin timing 24-bit YCrCb/RGB with embedded time codes and/or HS and VS/FIELD pin timing DDR 8-/12-bit 4:2:2 YCrCb DDR 24-bit 4:4:4 RGB Table 5. SDR 4:2:2 and 4:4:4 Output Modes OP_FORMAT_SEL[7:0] Pixel Output P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 0x0 8-Bit SDR ITU-R BT.656 Mode 0 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Y7, Cb7, Cr7 Y6, Cb6, Cr6 Y5, Cb5, Cr5 Y4, Cb4, Cr4 Y3, Cb3, Cr3 Y2, Cb2, Cr2 Y1, Cb1, Cr1 Y0, Cb0, Cr0 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z 0x0A 12-Bit SDR ITU-R BT.656 Mode 2 Y3, Cb3, Cr3 Y2, Cb2, Cr2 Y1, Cb1, Cr1 Y0, Cb0, Cr0 High-Z High-Z High-Z High-Z Y11, Cb11, Cr11 Y10, Cb10, Cr10 Y9, Cb9, Cr9 Y8, Cb8, Cr8 Y7, Cb7, Cr7 Y6, Cb6, Cr6 Y5, Cb5, Cr5 Y4, Cb4, Cr4 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z SDR 4:2:2 0x80 16-Bit SDR ITU-R BT.656 4:2:2 Mode 0 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb7, Cr7 Cb6, Cr6 Cb5, Cr5 Cb4, Cr4 Cb3, Cr3 Cb2, Cr2 Cb1, Cr1 Cb0, Cr0 Rev. 0 | Page 12 of 16 0x8A 24-Bit SDR ITU-R BT.656 4:2:2 Mode 2 Y3 Y2 Y1 Y0 Cb3, Cr3 Cb2, Cr2 Cb1, Cr1 Cb0, Cr0 Y11 Y10 Y9 Y8 Y7 Y6 Y5 Y4 Cb11, Cr11 Cb10, Cr10 Cb9, Cr9 Cb8, Cr8 Cb7, Cr7 Cb6, Cr6 Cb5, Cr5 Cb4, Cr4 SDR 4:4:4 0x40 24-Bit SDR 4:4:4 Mode 0 R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 Data Sheet ADV7610 Table 6. DDR 4:2:2 and 4:4:4 Output Modes OP_FORMAT_SEL[7:0] Pixel Output P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 1 2 DDR 4:2:2 Mode (Clock/2) 0x20 8-Bit DDR ITU-656 (Clock/2 Output) 4:2:2 Mode 0 Clock Rise Clock Fall High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Cb7, Cr7 Y7 Cb6, Cr6 Y6 Cb5, Cr5 Y5 Cb4, Cr4 Y4 Cb3, Cr3 Y3 Cb2, Cr2 Y2 Cb1, Cr1 Y1 Cb0, Cr0 Y0 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z DDR 4:2:2 Mode (Clock/2) 0x2A 12-Bit DDR ITU-656 (Clock/2 Output) 4:2:2 Mode 2 Clock Rise Clock Fall Cb3, Cr3 Y3 Cb2, Cr2 Y2 Cb1, Cr1 Y1 Cb0, Cr0 Y0 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Cb11, Cr11 Y11 Cb12, Cr12 Y12 Cb9, Cr9 Y9 Cb8, Cr8 Y8 Cb7, Cr7 Y7 Cb6, Cr6 Y6 Cb5, Cr5 Y5 Cb4, Cr4 Y4 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z -0 = even samples. -1 = odd samples. Rev. 0 | Page 13 of 16 DDR 4:4:4 Mode (Clock/2) 1, 2 0x60 24-Bit DDR RGB (Clock/2 Output) Clock Rise Clock Fall R7-0 R7-1 R6-0 R6-1 R5-0 R5-1 R4-0 R4-1 R3-0 R3-1 R2-0 R2-1 R1-0 R1-1 R0-0 R0-1 G7-0 G7-1 G6-0 G6-1 G5-0 G5-1 G4-0 G4-1 G3-0 G3-1 G2-0 G2-1 G1-0 G1-1 G0-0 G0-1 B7-0 B7-1 B6-0 B6-1 B5-0 B5-1 B4-0 B4-1 B3-0 B3-1 B2-0 B2-1 B1-0 B1-1 B0-0 B0-1 ADV7610 Data Sheet OUTLINE DIMENSIONS A1 CORNER INDEX AREA 6.10 6.00 SQ 5.90 10 9 8 7 6 5 4 3 2 1 A B BALL A1 PAD CORNER TOP VIEW C 4.50 BSC SQ D E 0.50 BSC F G H J K DETAIL A BOTTOM VIEW 0.75 REF *1.40 MAX DETAIL A 0.65 MIN 0.15 MIN *COMPLIANT TO JEDEC STANDARDS MO-225 WITH THE EXCEPTION TO PACKAGE HEIGHT. COPLANARITY 0.08 MAX 010807-A 0.35 SEATING 0.30 PLANE 0.25 BALL DIAMETER Figure 8. 76-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-76-1) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADV7610BBCZ ADV7610BBCZ-RL ADV7610BBCZ-P ADV7610BBCZ-P-RL 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 76-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 76-Ball Chip Scale Package Ball Grid Array [CSP_BGA], 13” Tape and Reel 76-Ball Chip Scale Package Ball Grid Array [CSP_BGA], NonHDCP Version 76-Ball Chip Scale Package Ball Grid Array [CSP_BGA], 13” Tape and Reel, NonHDCP Version Z = RoHS Compliant Part. Rev. 0 | Page 14 of 16 Package Option BC-76-1 BC-76-1 BC-76-1 BC-76-1 Data Sheet ADV7610 NOTES Rev. 0 | Page 15 of 16 ADV7610 Data Sheet NOTES The terms HDMI and HDMI High-Definition Multimedia Interface, and the HDMI logo are trademarks or registered trademarks of HDMI Licensing LLC in the United States and other countries. ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10775-0-12/12(0) Rev. 0 | Page 16 of 16