HS/VS HDCP KEYS FIELD/DE 36 COMPONENT PROCESSOR LLC DATA HDMI1 TMDS DDC DEEP COLOR HDMI Rx 4 I2S S/PDIF MCLK SCLK LRCLK ADV7611 HS VS/FIELD DE LLC 24-BIT YCbCr/RGB LRCLK AP MCLK SCLK 09305-001 High-Definition Multimedia Interface (HDMI®) 1.4a features supported All mandatory and additional 3D video formats supported Extended colorimetry, including sYCC601, Adobe RGB, Adobe YCC 601, xvYCC extended gamut color CEC 1.4-compatible HDMI receiver 165 MHz maximum TMDS clock frequency 24-bit output pixel bus High-bandwidth Digital Content Protection (HDCP) 1.4 support with internal HDCP keys HDCP repeater support Up to 127 KSVs supported Integrated CEC controller Programmable HDMI equalizer 5 V detect and Hot Plug assert for HDMI port Audio support SPDIF (IEC 60958-compatible) digital audio HDMI audio extraction support Advanced audio mute feature General Interrupt controller with two interrupt outputs Standard identification (STDI) circuit Highly flexible 24-bit pixel output interface Internal EDID RAM Any-to-any 3 × 3 color space conversion (CSC) matrix 2-layer PCB design supported 64-lead LQFP_EP, 10 mm × 10 mm package Qualified for automotive applications FUNCTIONAL BLOCK DIAGRAM OUTPUT MUX FEATURES OUTPUT MUX Data Sheet Low Power 165 MHz HDMI Receiver ADV7611 Figure 1. APPLICATIONS Projectors Automotive Video conferencing HDTVs AVR, HTiB Soundbars Video switches Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010-2012 Analog Devices, Inc. All rights reserved. ADV7611 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Power-Up Sequence ................................................................... 10 Applications ....................................................................................... 1 Power-Down Sequence .............................................................. 10 Functional Block Diagram .............................................................. 1 Functional Overview...................................................................... 11 Revision History ............................................................................... 2 HDMI Receiver........................................................................... 11 General Description ......................................................................... 3 Component Processor ............................................................... 11 Detailed Functional Block Diagram .......................................... 3 Other Features ............................................................................ 11 Specifications..................................................................................... 4 Pixel Input/Output Formatting .................................................... 12 Electrical Characteristics ............................................................. 4 Pixel Data Output Modes Features .......................................... 12 Data and I C Timing Characteristics ......................................... 5 Outline Dimensions ....................................................................... 14 Absolute Maximum Ratings............................................................ 7 Ordering Guide .......................................................................... 14 Package Thermal Performance ................................................... 7 Automotive Products ................................................................. 14 2 ESD Caution .................................................................................. 7 Pin Configuration and Function Descriptions ............................. 8 Power Supply Sequencing .............................................................. 10 REVISION HISTORY 6/12—Rev. C to Rev. D Change to Pin 1 Description, Table 4 ............................................. 8 5/12—Rev. B to Rev. C Changes to Features Section............................................................ 1 Changes to General Description Section ...................................... 3 Added Endnote 3 (Table 1) ............................................................. 4 Deleted TDM Serial Timing Parameter (Table 2) ........................ 5 Deleted Figure 6 ................................................................................ 7 Changed Pin 48 Description (Table 4) .......................................... 9 Changes to HDMI Receiver and Other Features Sections ........ 11 Added Endnote 1 in Pixel Input/Output Formatting Section and Endnote 1 to Table 5 ....................................................................... 12 Deleted Time-Division Multiplexed (TDM) Mode Section and Figure 9 ..................................................................................... 13 Changes to P14 (Table 6) ............................................................... 13 Changes to Ordering Guide .......................................................... 14 Added HDMI Note......................................................................... 16 6/11—Rev. A to Rev. B Changes to Figure 7 .......................................................................... 1 5/11—Rev. 0 to Rev. A Changes to Features Section............................................................ 1 Changes to Ordering Guide .......................................................... 16 Added Automotive Products Section .......................................... 16 11/10—Revision 0: Initial Version Rev. D | Page 2 of 16 Data Sheet ADV7611 GENERAL DESCRIPTION The following audio formats are accessible: The ADV7611 is offered in automotive, professional (no HDCP), and industrial versions. The operating temperature range is −40oC to +85oC. • • The UG-180 contains critical information that must be used in conjunction with the ADV7611. The ADV7611 is a high quality, single input HDMI®-capable receiver. It incorporates an HDMI-capable receiver that supports all mandatory 3D TV defined in HDMI 1.4a. The ADV7611 supports formats up to UXGA 60 Hz at 8 bit. • A stream from the I2S serializer (two audio channels) A stream from the S/PDIF serializer (two uncompressed channels or N compressed channels, for example, AC3) DST stream The HDMI port has dedicated 5 V detect and Hot Plug™ assert pins. The HDMI receiver also includes an integrated equalizer that ensures the robust operation of the interface with long cables. It integrates a CEC controller that supports the capability discovery and control (CDC) feature. The ADV7611 has an audio output port for the audio data extracted from the HDMI stream. The HDMI receiver has an advanced mute controller that prevents audible extraneous noise in the audio output. The ADV7611 contains one main component processor (CP), that processes the video signals from the HDMI receiver. It provides features such as contrast, brightness and saturation adjustments, STDI detection block, free run, and synchronization alignment controls. Fabricated in an advanced CMOS process, the ADV7611 is provided in a 10 mm × 10 mm, 64-lead surface-mount LQFP_EP, RoHS-compliant package and is specified over the −40°C to +85°C temperature range. DETAILED FUNCTIONAL BLOCK DIAGRAM CEC RXA_5V HPA_A/INT2* DDCA_SDA DDCA_SCL RXA_C± RXA_0± RXA_1± RXA_2± CEC CONTROLLER CONTROL INTERFACE I2C CONTROL AND DATA 5V DETECT AND HPD CONTROLLER INTERRUPT CONTROLLER (INT1,INT2) HDMI PROCESSOR EDID REPEATER CONTROLLER COMPONENT PROCESSOR HDCP EEPROM PLL EQUALIZER BACKEND COLORSPACE CONVERSION SAMPLER HDCP ENGINE 12 12 12 A B C DATA PREPROCESOR AND COLOR SPACE CONVERSION PACKET/ INFOFRAME MEMORY PACKET PROCESSOR MUTE AUDIO PROCESSOR ADV7611 *INT2 CAN BE ONLY OUTPUT ON ONE OF THE PINS: SCLK/INT2, MCLK/INT2, OR HPA_A/INT2. Figure 2. Detailed Functional Block Diagram Rev. D | Page 3 of 16 P0 TO P7 P8 TO P15 P16 TO P23 LLC HS VS/FIELD/ALSB DE INT1 INT2* AP LRCLK SCLK/INT2* MCLK/INT2* 09305-002 SCL SDA OUTPUT FORMATTER DPLL AUDIO OUTPUT FORMATTER XTALP XTALN ADV7611 Data Sheet SPECIFICATIONS At DVDD = 1.71 V to 1.89 V, DVDDIO = 3.14 V to 3.46 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.14 V to 3.46 V, CVDD = 1.71 V to 1.89 V, TMIN to TMAX = −40°C to +85°C, unless otherwise noted. ELECTRICAL CHARACTERISTICS Table 1. Parameter DIGITAL INPUTS 1 Input High Voltage Input Low Voltage Input Current Input Capacitance DIGITAL INPUTS (5 V TOLERANT)1, 2 Input High Voltage Input Low Voltage Input Current DIGITAL OUTPUTS1 Output High Voltage Output Low Voltage High Impedance Leakage Current Output Capacitance POWER REQUIREMENTS 3, 4 Digital Core Power Supply Digital I/O Power Supply PLL Power Supply Terminator Power Supply Comparator Power Supply Digital Core Supply Current Digital I/O Supply Current PLL Supply Current Terminator Supply Current Comparator Supply Current POWER-DOWN CURRENTS3, 5 Digital Core Supply Current Digital I/O Supply Current PLL Supply Current Terminator Supply Current Comparator Supply Current Power-Up Time Symbol Test Conditions/Comments Min VIH VIH VIL VIL IIN XTALN and XTALP Other digital inputs XTALN and XTALP Other digital inputs RESET pin Other digital inputs 1.2 2 Typ ±45 ±10 CIN VIH VIL IIN 2.6 VOH VOL ILEAK 2.4 −82 VS/FIELD/ALSB pin ±35 HPA_A/INT2 pin Other 10 IDVDD_PD IDVDDIO_PD IPVDD_PD ITVDD_PD ICVDD_PD tPWRUP 1.71 3.14 1.71 3.14 1.71 UXGA 60 Hz at 8 bit UXGA 60 Hz at 8 bit UXGA 60 Hz at 8 bit UXGA 60 Hz at 8 bit UXGA 60 Hz at 8 bit Power-Down Mode 1 Power-Down Mode 1 Power-Down Mode 1 Power-Down Mode 1 Power-Down Mode 1 Unit 0.4 0.8 ±60 10 V V V V µA µA pF 0.8 +82 V V µA 0.4 ±60 V V µA ±82 20 µA µA pF 1.8 3.3 1.8 3.3 1.8 95.7 12.9 30.7 50.9 95.8 1.89 3.46 1.89 3.46 1.89 188.1 178.5 36.9 57.6 114.4 V V V V V mA mA mA mA mA 0.2 1.3 1.5 0.1 1.3 25 0.5 1.7 1.8 0.3 1.7 mA mA mA mA mA ms COUT DVDD DVDDIO PVDD TVDD CVDD IDVDD IDVDDIO IPVDD ITVDD ICVDD Max Data guaranteed by characterization. The following pins are 5 V tolerant: DDCA_SCL, DDC_SDA, and RXA_5V. Data recorded during lab characterization. 4 Maximum current consumption values are recorded with maximum rated voltage supply levels, MoireX video pattern, and at maximum rated temperature. 5 Power-Down Mode 0 (IO map, Register 0x0C = 0x62), ring oscillator powered down (HDMI map, Register 0x48 = 0x01), and DDC pads off (HDMI map, Register 0x73 = 0x01). 1 2 3 Rev. D | Page 4 of 16 Data Sheet ADV7611 DATA AND I2C TIMING CHARACTERISTICS Table 2. Parameter CLOCK AND CRYSTAL Crystal Frequency, XTALP Crystal Frequency Stability LLC Frequency Range1 2 I C PORTS SCL Frequency SCL Minimum Pulse Width High2 SCL Minimum Pulse Width Low2 Start Condition Hold Time2 Start Condition Setup Time2 SDA Setup Time2 SCL and SDA Rise Time2 SCL and SDA Fall Time2 Stop Condition Setup Time2 RESET FEATURE Reset Pulse Width CLOCK OUTPUTS LLC Mark-Space Ratio2 DATA AND CONTROL OUTPUTS3 Data Output Transition Time2, 4 I2S PORT, MASTER MODE SCLK Mark-Space Ratio2 LRCLK Data Transition Time2 LRCLK Data Transition Time2 I2S Data Transition Time2, 5 I2S Data Transition Time2, 5 Symbol Test Conditions/Comments Min Typ Max Unit ±50 165 MHz ppm MHz 28.63636 13.5 400 t1 t2 t3 t4 t5 t6 t7 t8 ms 45:55 End of valid data to negative clock edge Negative clock edge to start of valid data t15:t16 t17 t18 t19 t20 5 300 300 t9:t10 t11 t12 0.6 kHz ns μs ns ns ns ns ns μs 600 1.3 600 600 100 1.0 0.0 45:55 End of valid data to negative SCLK edge Negative SCLK edge to start of valid data End of valid data to negative SCLK edge Negative SCLK edge to start of valid data 1 Maximum LLC frequency is limited by the clock frequency of UXGA 60 Hz at 8 bit. Data guaranteed by characterization. With the DLL block on output clock bypassed. 4 DLL bypassed on clock path. 5 2 I S is accessible via the AP pin. 2 3 Rev. D | Page 5 of 16 55:45 % duty cycle 2.2 0.3 ns ns 55:45 % duty cycle ns ns ns ns 10 10 5 5 ADV7611 Data Sheet Timing Diagrams t3 t5 t3 SDA t6 t1 t7 t2 t4 09305-003 SCL t8 2 Figure 3. I C Timing t9 t10 LLC t11 09305-004 t12 P0 TO P23, HS, VS/FIELD/ALSB, DE Figure 4. Pixel Port and Control SDR Output Timing t15 SCLK t16 t17 LRCLK t18 t19 LEFT-JUSTIFIED MODE MSB MSB – 1 t20 I2S I2S MODE I2S RIGHT-JUSTIFIED MODE t19 MSB MSB – 1 t20 t19 MSB LSB t20 NOTES 1. I2S IS A SIGNAL ACCESSIBLE VIA THE AP PIN. Figure 5. I2S Timing Rev. D | Page 6 of 16 09305-005 I2S Data Sheet ADV7611 ABSOLUTE MAXIMUM RATINGS PACKAGE THERMAL PERFORMANCE Table 3. Parameter DVDD to GND PVDD to GND DVDDIO to GND CVDD to GND TVDD to GND Digital Inputs Voltage to GND 5 V Tolerant Digital Inputs to GND1 Digital Outputs Voltage to GND XTALP, XTALN SCL/SDA Data Pins to DVDDIO Maximum Junction Temperature (TJ MAX) Storage Temperature Range Infrared Reflow Soldering (20 sec) 1 To reduce power consumption when using the ADV7611, the user is advised to turn off the unused sections of the part. Rating 2.2 V 2.2 V 4.0 V 2.2 V 4.0 V GND − 0.3 V to DVDDIO + 0.3 V 5.3 V Due to the printed circuit board (PCB) metal variation, and, therefore, variation in PCB heat conductivity, the value of θJA may differ for various PCBs. GND − 0.3 V to DVDDIO + 0.3 V GND − 0.3 V to PVDD + 0.3 V DVDDIO − 0.3 V to DVDDIO + 3.6 V 125°C The maximum junction temperature (TJ MAX) of 125°C must not be exceeded. The following equation calculates the junction temperature using the measured package surface temperature and applies only when no heat sink is used on the device under test (DUT): −60°C to +150°C 260°C where: TS is the package surface temperature (°C). ΨJT = 0.4°C/W for the 64-lead LQFP_EP. The following inputs are 3.3 V inputs but are 5 V tolerant: DDCA_SCL and DDCA_SDA. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The most efficient measurement solution is obtained using the package surface temperature to estimate the die temperature because this eliminates the variance associated with the θJA value. ( TJ = TS + Ψ JT × WTOTAL ) WTOTAL = ((PVDD × IPVDD) + (0.05 × TVDD × ITVDD) + (CVDD × ICVDD) + (DVDD × IDVDD) + (DVDDIO × IDVDDIO)) where 0.05 is 5% of the TVDD power that is dissipated on the part itself. ESD CAUTION Rev. D | Page 7 of 16 ADV7611 Data Sheet SCLK/INT2 LRCLK MCLK/INT2 DVDD SCL SDA INT1 RESET PVDD XTALP XTALN DVDD CEC DDCA_SCL DDCA_SDA RXA_5V PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 AP 47 VS/FIELD/ALSB 3 46 HS RXA_C+ 4 45 DE TVDD 5 44 DVDDIO RXA_0– 6 43 P0 RXA_0+ 7 42 P1 TVDD 8 41 P2 RXA_1– 9 40 DVDD RXA_1+ 10 39 P3 TVDD 11 38 P4 RXA_2– 12 37 P5 RXA_2+ 13 36 P6 CVDD 14 35 P7 P23 15 34 DVDDIO P22 16 33 P8 HPA_A/INT2 1 CVDD 2 RXA_C– PIN 1 INDICATOR ADV7611 TOP VIEW (Not to Scale) P10 P9 09305-008 NOTES 1. CONNECT EXPOSED PAD (PIN0) TO GROUND (BOTTOM). P11 P12 P13 P14 P15 LLC DVDD DVDDIO P16 P17 P18 P19 P20 P21 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Figure 6. Pin Configuration Table 4. Pin Function Descriptions Pin No. 0 1 Mnemonic GND HPA_A/INT2 Type Ground Miscellaneous digital 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 CVDD RXA_C− RXA_C+ TVDD RXA_0− RXA_0+ TVDD RXA_1− RXA_1+ TVDD RXA_2− RXA_2+ CVDD P23 P22 P21 P20 P19 P18 P17 P16 DVDDIO DVDD Power HDMI input HDMI input Power HDMI input HDMI input Power HDMI input HDMI input Power HDMI input HDMI input Power Digital video output Digital video output Digital video output Digital video output Digital video output Digital video output Digital video output Digital video output Power Power Description Ground. A dual function pin that can be configured to output a Hot Plug assert signal (for HDMI Port A) or an Interrupt 2 signal. This pin is 5 V tolerant. HDMI Analog Block Supply Voltage (1.8 V). Digital Input Clock Complement of Port A in the HDMI Interface. Digital Input Clock True of Port A in the HDMI Interface. Terminator Supply Voltage (3.3 V). Digital Input Channel 0 Complement of Port A in the HDMI Interface. Digital Input Channel 0 True of Port A in the HDMI Interface. Terminator Supply Voltage (3.3 V). Digital Input Channel 1 Complement of Port A in the HDMI Interface. Digital Input Channel 1 True of Port A in the HDMI Interface. Terminator Supply Voltage (3.3 V). Digital Input Channel 2 Complement of Port A in the HDMI Interface. Digital Input Channel 2 True of Port A in the HDMI Interface. HDMI Analog Block Supply Voltage (1.8 V). Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Digital I/O Supply Voltage (3.3 V). Digital Core Supply Voltage (1.8 V). Rev. D | Page 8 of 16 Data Sheet ADV7611 Pin No. 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Mnemonic LLC P15 P14 P13 P12 P11 P10 P9 P8 DVDDIO P7 P6 P5 P4 P3 DVDD P2 P1 P0 DVDDIO DE HS VS/FIELD/ALS B Type Digital video output Digital video output Digital video output Digital video output Digital video output Digital video output Digital video output Digital video output Digital video output Power Digital video output Digital video output Digital video output Digital video output Digital video output Power Digital video output Digital video output Digital video output Power Miscellaneous digital Digital video output Digital input/output 48 AP Miscellaneous digital 49 SCLK/INT2 Miscellaneous digital 50 51 LRCLK MCLK/INT2 Miscellaneous digital Miscellaneous digital 52 53 54 55 DVDD SCL SDA INT1 Power Miscellaneous digital Miscellaneous digital Miscellaneous digital 56 RESET Miscellaneous digital 57 58 PVDD XTALP Power Miscellaneous analog 59 60 61 62 63 64 XTALN DVDD CEC DDCA_SCL DDCA_SDA RXA_5V Miscellaneous analog Power Digital input/output HDMI input HDMI input HDMI input Description Line-Locked Output Clock for the Pixel Data (Range is 13.5 MHz to 162.5 MHz). Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Digital I/O Supply Voltage (3.3 V). Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Digital Core Supply Voltage (1.8 V). Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Digital I/O Supply Voltage (3.3 V). DE (data enable) is a signal that indicates active pixel data. HS is a horizontal synchronization output signal. VS is a vertical synchronization output signal. FIELD is a field synchronization output signal in all interlaced video modes. VS or FIELD can be configured for this pin. The ALSB allows selection of the I2C address. Audio Output Pin. Pin can be configured to output S/PDIF digital audio output (S/PDIF) or I2S. A dual function pin that can be configured to output an audio serial clock or an Interrupt 2 signal. Audio Left/Right Clock. A dual function pin that can be configured to output an audio master clock or an Interrupt 2 signal. Digital Core Supply Voltage (1.8 V). I2C Port Serial Clock Input. SCL is the clock line for the control port. I2C Port Serial Data Input/Output Pin. SDA is the data line for the control port. Interrupt. This pin can be active low or active high. When status bits change, this pin is triggered. The events that trigger an interrupt are under user configuration. System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset the ADV7611 circuitry. PLL Supply Voltage (1.8 V). Input Pin for 28.63636 MHz Crystal or an External 1.8 V, 28.63636 MHz Clock Oscillator Source to Clock the ADV7611. Crystal Input. Input pin for 28.63636 MHz crystal. Digital Core Supply Voltage (1.8 V). Consumer Electronic Control Channel. HDCP Slave Serial Clock Port A. DDCA_SCL is a 3.3 V input that is 5 V tolerant. HDCP Slave Serial Data Port A. DDCA_SDA is a 3.3 V input that is 5 V tolerant. 5 V Detect Pin for Port A in the HDMI Interface. Rev. D | Page 9 of 16 ADV7611 Data Sheet POWER SUPPLY SEQUENCING The recommended power-up sequence of the ADV7611 is to power up the 3.3 V supplies first, followed by the 1.8 V supplies. Reset should be held low while the supplies are powered up. Alternatively, the ADV7611 may be powered up by asserting all supplies simultaneously. In this case, care must be taken while the supplies are being established to ensure that a lower rated supply does not go above a higher rated supply level. POWER SUPPLY (V) POWER-UP SEQUENCE 3.3V 3.3V SUPPLIES 1.8V 1.8V SUPPLIES The ADV7611 supplies may be deasserted simultaneously as long as a higher rated supply does not go below a lower rated supply. 3.3V SUPPLIES POWER-UP 1.8V SUPPLIES POWER-UP Figure 7. Recommended Power-Up Sequence Rev. D | Page 10 of 16 09305-007 POWER-DOWN SEQUENCE Data Sheet ADV7611 FUNCTIONAL OVERVIEW HDMI RECEIVER COMPONENT PROCESSOR The receiver supports all mandatory and many optional 3D formats. It supports HDTV formats up to UXGA at 8 bit. The ADV7611 has an any-to-any 3 × 3 CSC matrix. The CSC block is placed at the back of the CP section. CSC enables YPrPb-to-RGB and RGB-to-YCrCb conversions. Many other standards of color space can be implemented using the color space converter. The HDMI-compatible receiver on the ADV7611 incorporates programmable equalization of the HDMI data signals. This equalization compensates for the high frequency losses inherent in HDMI and DVI cabling, especially at longer lengths and higher frequencies. It is capable of equalizing for cable lengths up to 30 meters to achieve robust receiver performance. With the inclusion of HDCP, displays can receive encrypted video content. The HDMI interface of the ADV7611 allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewability of that authentication during transmission, as specified by the HDCP 1.4 protocol. The ADV7611 has a synchronization regeneration block used to regenerate the DE based on the measurement of the video format being displayed and to filter the horizontal and vertical synchronization signals to prevent glitches. The HDMI receiver also supports TERC4 error detection, used for detection of corrupted HDMI packets following a cable disconnect. The HDMI receiver contains an audio mute controller that can detect a variety of conditions that may result in audible extraneous noise in the audio output. On detection of these conditions, the audio signal can be ramped to prevent audio clicks or pops. Audio output can be formatted to LPCM and IEC 61937. The HDMI receiver features include: • • • • • • • • • • 162.5 MHz (UXGA at 8 bit) maximum TMDS clock frequency 3D format support defined in HDMI 1.4a specification Integrated equalizer for cable lengths up to 30 meters HDCP 1.4 Internal HDCP keys PCM audio packet support Repeater support Internal EDID RAM Hot Plug assert output pin for an HDMI port CEC controller CP features include: • • • • • • • • 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and other formats Manual adjustments including gain (contrast) and offset (brightness), hue, and saturation Free run output mode that provides stable timing when no video input is present 162.5 MHz processing rate Contrast, brightness, hue, and saturation controls Standard identification enabled by STDI block RGB that can be color space converted to YCrCb and decimated to a 4:2:2 format for video-centric back end IC interfacing DE output signal supplied for direct connection to an HDMI/DVI transmitter OTHER FEATURES The ADV7611 has HS, VS, FIELD, and DE output signals with programmable position, polarity, and width. The ADV7611 has programmable interrupt request output pins, including INT1 and INT2 (INT2 is accessible only via one of following pins: MCLK/INT2, SCLK/INT2, or HPA_A/INT2). It also features a low power-down mode. The I2C address of the main map is 0x98 after reset. This can be changed after reset to 0x9A if pullup is attached to VS/FIELD/ALSB pin and I2C command SAMPLE_ALSB is issued. Refer to the Register Access and Serial Ports Description section in the UG-180. The ADV7611 is provided in a 10 mm × 10 mm, RoHS-compliant LQFP_EP package, and is specified over the −40°C to +85°C temperature range. Rev. D | Page 11 of 16 ADV7611 Data Sheet PIXEL INPUT/OUTPUT FORMATTING The output section of the ADV7611 is highly flexible. The pixel output bus can support up to 24-bit 4:4:4 YCrCb. The pixel data supports both single and double data rates modes. In SDR mode, a 16-/24-bit 4:2:2 or 24-bit 4:4:4 output is possible. In DDR mode 1, the pixel output port can be configured in an 8-/12-bit 4:2:2 YCrCb or 24-bit 4:4:4 RGB. Bus rotation is supported. Table 5 and Table 6 outline the different output formats that are supported. All output modes are controlled via I2C. 1 DDR mode is only supported only up to 50 MHz (an equivalent to data rate clocked 100 MHz clock in SDR mode). PIXEL DATA OUTPUT MODES FEATURES The output pixel port features include: • • • • • 8-/12-bit ITU-R BT.656 4:2:2 YCrCb with embedded time codes and/or HS, VS, and FIELD output signals 16-/24-bit YCrCb with embedded time codes and/or HS and VS/FIELD pin timing 24-bit YCrCb/RGB with embedded time codes and/or HS and VS/FIELD pin timing DDR 8-/12-bit 4:2:2 YCrCb DDR 24-bit 4:4:4 RGB Table 5. SDR 4:2:2 and 4:4:4 Output Modes OP_FORMAT_SEL[7:0] Pixel Output P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 1 0x0 8-Bit SDR ITU-R BT.656 Mode 0 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Y7, Cb7, Cr7 Y6, Cb6, Cr6 Y5, Cb5, Cr5 Y4, Cb4, Cr4 Y3, Cb3, Cr3 Y2, Cb2, Cr2 Y1, Cb1, Cr1 Y0, Cb0, Cr0 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z 1 0x0A 12-Bit SDR ITU-R BT.656 Mode 2 Y3, Cb3, Cr3 Y2, Cb2, Cr2 Y1, Cb1, Cr1 Y0, Cb0, Cr0 High-Z High-Z High-Z High-Z Y11, Cb11, Cr11 Y10, Cb10, Cr10 Y9, Cb9, Cr9 Y8, Cb8, Cr8 Y7, Cb7, Cr7 Y6, Cb6, Cr6 Y5, Cb5, Cr5 Y4, Cb4, Cr4 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z 1 SDR 4:2:2 0x80 16-Bit SDR ITU-R BT.656 4:2:2 Mode 0 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb7, Cr7 Cb6, Cr6 Cb5, Cr5 Cb4, Cr4 Cb3, Cr3 Cb2, Cr2 Cb1, Cr1 Cb0, Cr0 0x8A 24-Bit SDR ITU-R BT.656 4:2:2 Mode 2 Y3 Y2 Y1 Y0 Cb3, Cr3 Cb2, Cr2 Cb1, Cr1 Cb0, Cr0 Y11 Y10 Y9 Y8 Y7 Y6 Y5 Y4 Cb11, Cr11 Cb10, Cr10 Cb9, Cr9 Cb8, Cr8 Cb7, Cr7 Cb6, Cr6 Cb5, Cr5 Cb4, Cr4 Modes 0x00 and 0x0A require additional writes to IO Map Register 0x19[7:6] = 2’b11 and IO Map Register 0x33[6] = 1 Rev. D | Page 12 of 16 SDR 4:4:4 0x40 24-Bit SDR 4:4:4 Mode 0 R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 Data Sheet ADV7611 Table 6. DDR 4:2:2 and 4:4:4 Output Modes OP_FORMAT_SEL[7:0] Pixel Output P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 1 2 DDR 4:2:2 Mode (Clock/2) 0x20 8-Bit DDR ITU-656 (Clock/2 Output) 4:2:2 Mode 0 Clock Rise Clock Fall High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Cb7, Cr7 Y7 Cb6, Cr6 Y6 Cb5, Cr5 Y5 Cb4, Cr4 Y4 Cb3, Cr3 Y3 Cb2, Cr2 Y2 Cb1, Cr1 Y1 Cb0, Cr0 Y0 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z DDR 4:2:2 Mode (Clock/2) 0x2A 12-Bit DDR ITU-656 (Clock/2 Output) 4:2:2 Mode 2 Clock Rise Clock Fall Cb3, Cr3 Y3 Cb2, Cr2 Y2 Cb1, Cr1 Y1 Cb0, Cr0 Y0 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Cb11, Cr11 Y11 Cb10, Cr10 Y10 Cb9, Cr9 Y9 Cb8, Cr8 Y8 Cb7, Cr7 Y7 Cb6, Cr6 Y6 Cb5, Cr5 Y5 Cb4, Cr4 Y4 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z -0 = even samples. -1 = odd samples. Rev. D | Page 13 of 16 DDR 4:4:4 Mode (Clock/2) 1, 2 0x60 24-Bit DDR RGB (Clock/2 Output) Clock Rise Clock Fall R7-0 R7-1 R6-0 R6-1 R5-0 R5-1 R4-0 R4-1 R3-0 R3-1 R2-0 R2-1 R1-0 R1-1 R0-0 R0-1 G7-0 G7-1 G6-0 G6-1 G5-0 G5-1 G4-0 G4-1 G3-0 G3-1 G2-0 G2-1 G1-0 G1-1 G0-0 G0-1 B7-0 B7-1 B6-0 B6-1 B5-0 B5-1 B4-0 B4-1 B3-0 B3-1 B2-0 B2-1 B1-0 B1-1 B0-0 B0-1 ADV7611 Data Sheet OUTLINE DIMENSIONS 0.75 0.60 0.45 12.20 12.00 SQ 11.80 1.60 MAX 10.20 10.00 SQ 9.80 49 49 64 48 1 1.00 REF 64 1 48 PIN 1 SEATING PLANE EXPOSED PAD 5.10 5.00 SQ 4.90 7.50 REF SQ BOTTOM VIEW TOP VIEW 0.20 0.09 0.15 0.05 7° 0° (PINS DOWN) 16 33 32 17 16 33 17 32 VIEW A 0.08 COPLANARITY 0.50 LEAD PITCH VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BCD-HD 0.27 0.22 0.17 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 06-12-2012-A 1.45 1.40 1.35 (PINS UP) Figure 8. 64-Lead Low Profile Quad Flat Package (LQFP_EP) SW-64-2 Dimensions shown in millimeters ORDERING GUIDE Model 1, 2 ADV7611BSWZ ADV7611BSWZ-RL ADV7611BSWZ-P ADV7611BSWZ-P-RL ADV7611WBSWZ ADV7611WBSWZ-RL EVAL-ADV7611EB1Z EVAL-ADV7611EB2Z Notes 3 4 3 3 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 64-Lead LQFP_EP 64-Lead LQFP_EP 64-Lead LQFP_EP 64-Lead LQFP_EP 64-Lead LQFP_EP 64-Lead LQFP_EP Evaluation Board with HDCP Keys Evaluation Board Without HDCP Keys Package Option SW-64-2 SW-64-2 SW-64-2 SW-64-2 SW-64-2 SW-64-2 Z = RoHS Compliant Part. W = Qualified for Automotive Parts. 3 13” Tape and Reel. 4 Non-HDCP version. 1 2 AUTOMOTIVE PRODUCTS The ADV7611W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices, Inc., account representative for specific product ordering information and to obtain the specific Automotive Reliability report for this model. Rev. D | Page 14 of 16 Data Sheet ADV7611 NOTES Rev. D | Page 15 of 16 ADV7611 Data Sheet NOTES HDMI, the HDMI Logo, and High-Definition Multimedia Interface are trademarks or registered trademarks of HDMI Licensing LLC in the United States and other countries. ©2010-2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09305-0-6/12(D) Rev. D | Page 16 of 16