19-4076; Rev 0; 7/08 KIT ATION EVALU E L B A AVAIL Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier Features The MAX9877 combines a high-efficiency Class D audio power amplifier with a stereo Class AB capacitorless DirectDrive® headphone amplifier. Maxim’s 3rd generation, filterless Class D amplifier with active emissions limiting technology provides Class AB performance with Class D efficiency. The MAX9877 delivers up to 725mW from a 3.7V supply into an 8Ω load with 87% efficiency to extend battery life. The filterless modulation scheme combined with active emissions limiting circuitry and spread-spectrum modulation greatly reduces EMI while eliminating the need for output filtering used in traditional Class D devices. The stereo Class AB headphone amplifier in the MAX9877 uses Maxim’s patented DirectDrive architecture, that produces a ground-referenced output from a single supply, eliminating the need for large DC-blocking capacitors, saving cost, space, and component height. The device utilizes a user-defined input architecture, three preamplifier gain settings, an input mixer, volume control, comprehensive click-and-pop suppression, and I2C control. A bypass mode feature disables the integrated Class D amplifier and utilizes an internal DPST switch to allow an external amplifier to drive the speaker that is connected at the outputs of the MAX9877. ♦ Low Emissions, Filterless Class D Amplifier Achieves Better than 10dB Margin Under EN55022 Class B Limits ♦ Low RF Susceptibility Design Rejects TDMA Noise from GSM Radios ♦ Input Mixer with User-Defined Input Mode ♦ 725mW Speaker Output (RSPK = 8Ω, PVDD = 3.7V) ♦ 53mW Headphone Output (RHP = 16Ω, VDD = 3.7V) ♦ Low 0.05% THD+N at 1kHz (Class D Power Amplifier) ♦ Low 0.016% THD+N at 1kHz (Headphone Amplifier) ♦ 87% Efficiency (RSPK = 8Ω, POUT = 750mW) Ω Analog Switch for Speaker Amplifier Bypass ♦ 1.6Ω ♦ High Speaker Amplifier PSRR (72dB at 217Hz) ♦ High Headphone Amplifier PSRR (84dB at 217Hz) ♦ I2C Control ♦ Hardware and Software Shutdown Mode ♦ Click-and-Pop Suppression ♦ Current-Limit and Thermal Protection ♦ Available in a Space-Saving, 2.5mm x 2.0mm WLP Package The MAX9877 is available in a thermally efficient, space-saving 20-bump WLP package. Applications Cell Phones Portable Multimedia Players Ordering Information PART TEMP RANGE PIN-PACKAGE MAX9877EWP+TG45 -40°C to +85°C 20 WLP (5x4) +Denotes a lead-free package. T = Tape and reel. G45 indicates protective die coating. Simplified Block Diagram SINGLE SUPPLY 2.7V TO 5.25V VOLUME CONTROL PREAMPLIFIER Pin Configuration TOP VIEW (BUMP SIDE DOWN) 1 2 3 4 5 HPR HPL VSS C1N C1P VDD BIAS SDA RXIN+ OUT+ INB2 INB1 SCL PGND PVDD INA2 INA1 GND RXIN- OUT- A MIXER/MUX B I2C INTERFACE VOLUME CONTROL BYPASS C D MAX9877 WLP ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9877 General Description MAX9877 Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier ABSOLUTE MAXIMUM RATINGS VDD, PVDD to PGND ..............................................-0.3V to +5.5V VDD to PVDD ..........................................................-0.3V to +0.3V VSS to PGND .........................................................-5.5V to +0.3V C1N to PGND..............................................(VSS - 0.3V) to +0.3V C1P to PGND ...........................................-0.3V to (PVDD + 0.3V) HPL, HPR to VSS (Note 1) ......-0.3V to the lower of (PVDD - (VSS + 0.3V)) or +9V HPL, HPR to PVDD (Note 2) ......+0.3V to the higher of (VSS - (PVDD - 0.3V)) or -9V GND to PGND.....................................................................±0.3V INA1, INA2, INB1, INB2, BIAS..................................-0.3V to +4V SDA, SCL...............................................................-0.3V to +5.5V All Other Pins to GND...............................-0.3V to (PVDD + 0.3V) Continuous Current In/Out of PVDD, PGND, OUT_.........±800mA Continuous Current In/Out of HPR and HPL .....................140mA Continuous Current In/Out of RXIN+ and RXIN- ...............150mA Continuous Input Current VSS ...........................................100mA Continuous Input Current (all other pins) .........................±20mA Duration of OUT_ Short Circuit to GND or PVDD ........Continuous Duration of Short Circuit Between OUT+ and OUT- ..Continuous Duration of HP_ Short Circuit to GND or PVDD ..........Continuous Continuous Power Dissipation (TA = +70°C) 20-Bump WLP, 5 x 4, Multilayer Board (derate 13.0mW/°C above +70°C) ..................................1.04W Junction Temperature ......................................................+150°C Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Note 1: HPR and HPL should be limited to no more than 9V above VSS, or above PVDD + 0.3V, whichever limits first. Note 2: HPR and HPL should be limited to no more than 9V below PVDD, or below VSS - 0.3V, whichever limits first. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = PVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, volume controls = 0dB, OSC = 00, BYPASS = 0, SHDN = 1. Speaker loads (ZSPK) connected between OUT+ and OUT-. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and SCL pullup voltage = 3.3V. ZSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 3) PARAMETER Supply Voltage Range SYMBOL CONDITIONS VDD, PVDD Guaranteed by PSRR test HP mode, OUTMODE = 2 Quiescent Current Shutdown Current IDD ISHDN MIN OSC = 00 5.6 OSC = 10 5.5 SPK mode, OUTMODE = 7 OSC = 00 6.6 OSC = 10 5.7 SPK + HP mode, OUTMODE = 9 OSC = 00 10.4 OSC = 10 9.3 ISHDN = IVDD + IPVDD; SHDN = 0; VSDA = VSCL = logic-high; TA = +25°C 10 OSC = 00 Turn-On Time tON BIAS Release Time tBR Input Resistance RIN Maximum Input Signal Swing 2 TYP 2.7 Time from shutdown to full operation MAX UNITS 5.25 V 9.0 11.0 mA 16.0 22 µA 10 OSC = 01 10 OSC = 10 17.5 After forcing BIAS low, time from BIAS released to I2C reset ms 25 80 TA = +25°C, preamp gain = 0dB or +9dB 11 21 31 TA = +25°C, preamp gain = +20dB 3 5.5 8 Preamp = 0dB 2.30 Preamp = +9dB 0.820 Preamp = +20dB 0.230 _______________________________________________________________________________________ ms kΩ VP-P Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier (VDD = PVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, volume controls = 0dB, OSC = 00, BYPASS = 0, SHDN = 1. Speaker loads (ZSPK) connected between OUT+ and OUT-. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and SCL pullup voltage = 3.3V. ZSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 3) PARAMETER Common-Mode Rejection Ratio SYMBOL CMRR CONDITIONS fIN = 1kHz (differential input mode) MIN Preamp = 0dB 47 Preamp = +9dB 49 Preamp = +20dB Input DC Voltage IN_ inputs Bias Voltage TYP MAX UNITS dB 42 1.22 1.3 1.38 V 1.13 1.2 1.27 V TA = +25°C (volume at mute) ±0.5 ±4 TA = +25°C (volume at 0dB, OUTMODE = 1, ΔIN_ = 0) ±1.5 VBIAS SPEAKER AMPLIFIER (OUTMODE = 1) Output Offset Voltage Click-and-Pop Level VOS KCP Peak voltage, TA = +25°C, A-weighted, 32 samples per second, volume at mute (Note 4) Into shutdown -70 Out of shutdown -70 dBV PVDD = VDD = 2.7V to 5.5V Power-Supply Rejection Ratio (Note 4) Output Power (Note 5) Total Harmonic Distortion Plus Noise PSRR POUT THD+N TA = +25°C, PVDD = VDD THD+N ≤ 1% Signal-to-Noise Ratio SNR A-weighted, OUTMODE = 7, 9 50 76 f = 217Hz, 100mVP-P ripple 72 f = 1kHz, 100mVP-P ripple 68 f = 20kHz, 100mVP-P ripple 55 ZSPK = 8Ω + 68µH, VDD = 3.7V 725 ZSPK = 8Ω + 68µH, VDD = 3.3V 560 ZSPK = 8Ω + 68µH, VDD = 3.0V 465 ZSPK = 4Ω + 33µH, VDD = 3.7V 825 ZSPK = 4Ω + 33µH, VDD = 3.0V 770 f = 1kHz, POUT = 350mW, TA = +25°C, ZSPK = 8Ω + 68µH A-weighted, OUTMODE = 1, 3, 4, 6 mV dB 0.05 ΔIN_ = 0 (single-ended) 92 ΔIN_ = 1 (differential) 94 ΔIN_ = 0 (single-ended) 88 ΔIN_ = 1 (differential) 92 mW % dB _______________________________________________________________________________________ 3 MAX9877 ELECTRICAL CHARACTERISTICS (continued) MAX9877 Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier ELECTRICAL CHARACTERISTICS (continued) (VDD = PVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, volume controls = 0dB, OSC = 00, BYPASS = 0, SHDN = 1. Speaker loads (ZSPK) connected between OUT+ and OUT-. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and SCL pullup voltage = 3.3V. ZSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 3) PARAMETER SYMBOL Output Frequency CONDITIONS MIN Spread-spectrum modulation mode, OSC = 00 1176 ±60 Fixed-frequency mode, OSC = 01 1100 Fixed-frequency mode, OSC = 10 700 Current Limit Efficiency Speaker Gain η POUT = 600mW, f = 1kHz AV 11.5 A-weighted, OUTMODE = 1, ΔIN_ = 0 (Note 4) Output Noise TYP MAX UNITS kHz 1.5 A 87 % 12.0 12.5 63 dB µVRMS HEADPHONE AMPLIFIERS (OUTMODE = 2) Output Offset Voltage Click-and-Pop Level VOS KCP TA = +25°C (volume at mute) ±0.15 TA = +25°C (volume at 0dB) ±1.6 Peak voltage, TA = +25°C, A-weighted, 32 samples per second. volume at mute (Note 4) Into shutdown -80 Out of shutdown -80 Output Power Headphone Gain PSRR POUT THD+N ≤ 1% THD+N f = 1kHz, VRIPPLE = 100mVP-P 80 f = 20kHz, VRIPPLE = 100mVP-P 62 RHP = 16Ω 53 RHP = 32Ω 27 dB mW 0 +0.4 dB TA = +25°C, HPL to HPR, volume at 0dB, OUTMODE = 2, 5; ΔIN_ = 0 ±0.3 ±2.5 % RHP = 32Ω (POUT = 10mW, f = 1kHz) 0.016 RHP = 16Ω (POUT = 10mW, f = 1kHz), TA = +25°C 0.03 SNR A-weighted, RHP = 16Ω, OUTMODE = 8, 9 4 85 84 -0.4 A-weighted, OUTMODE = 2, 3, 5, 6; RHP = 16Ω Signal-to-Noise Ratio 70 f = 217Hz, VRIPPLE = 100mVP-P AV Channel-to-Channel Gain Tracking Total Harmonic Distortion Plus Noise TA = +25°C, PVDD = VDD mV dBV PVDD = VDD = 2.7V to 5.25V Power-Supply Rejection Ratio (Note 4) ±0.6 ΔIN_ = 0 (single-ended) 98 ΔIN_ = 1 (differential) 98 ΔIN_ = 0 (single-ended) 96 ΔIN_ = 1 (differential) 96 _______________________________________________________________________________________ % dB Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier (VDD = PVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, volume controls = 0dB, OSC = 00, BYPASS = 0, SHDN = 1. Speaker loads (ZSPK) connected between OUT+ and OUT-. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and SCL pullup voltage = 3.3V. ZSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Slew Rate SR 0.35 Capacitive Drive CL 100 pF 65 dB Crosstalk HPL to HPR, HPR to HPL, f = 20Hz to 20kHz Spread-spectrum modulation mode, OSC = 00 Charge-Pump Frequency V/µs 588 ±30 Fixed-frequency mode, OSC = 01 430 550 670 Fixed-frequency mode, OSC = 10 220 350 500 kHz VOLUME CONTROL Minimum Setting _VOL = 1 -75 dB Maximum Setting _VOL = 31 0 dB PGAIN_ = 00 Preamp Gain Input A or B Mute Attenuation f = 1kHz, _VOL = 0 Zero-Crossing Detection Timeout ZCD = 1 0 PGAIN_ = 01 9 PGAIN_ = 10 20 Speaker 100 Headphone 110 dB dB 60 ms ANALOG SWITCH On-Resistance RON IRXIN_ = 20mA, RXIN_ = 0V and VDD, BYPASS = 1 VDIF = 2VP-P, VCM = VDD/2, f = 1kHz, BYPASS = 1, TA = +25°C Total Harmonic Distortion TA = +25°C 1.6 Ω TA = TMIN to TMAX 5.2 Series resistance is 9.1Ω per switch 0.05 No series resistors 0.3 0.25 % BYPASS = 0, RXIN+ and RXIN- to GND = 50Ω, ZSPK = 8Ω + 68µH, f = 10kHz, referred to speaker output signal Off-Isolation 4.5 88 dB DIGITAL INPUTS Input-Voltage High (SDA, SCL) VH Input-Voltage Low (SDA, SCL) VL 1.4 0.4 V V Input-Voltage Low (BIAS) VBL 0.15 V Input Hysteresis (SDA, SCL) VHYS 80 SDA, SCL Input Capacitance CIN 4 Input Leakage Current IIN BIAS Pullup Current SDA, SCL; TA = +25°C IBIAS mV pF ±1.0 94 µA µA DIGITAL OUTPUTS (SDA Open Drain) Output Low Voltage SDA VOL ISINK = 3mA 0.4 V Output Fall Time SDA tOF VH(MIN) to VL(MAX) bus capacitance = 10pF to 400pF, ISINK = 3mA 250 ns _______________________________________________________________________________________ 5 MAX9877 ELECTRICAL CHARACTERISTICS (continued) MAX9877 Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier ELECTRICAL CHARACTERISTICS (continued) (VDD = PVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, volume controls = 0dB, OSC = 00, BYPASS = 0, SHDN = 1. Speaker loads (ZSPK) connected between OUT+ and OUT-. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and SCL pullup voltage = 3.3V. ZSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 1.7 3.6 V 400 kHz 2-WIRE INTERFACE TIMING External Pullup Voltage Range: SDA and SCL Serial Clock Frequency fSCL DC Bus Free Time Between STOP and START Conditions tBUF 1.3 µs START Condition Hold tHD:STA 0.6 µs START Condition Setup Time tSU:STA 0.6 µs tLOW 1.3 µs µs Clock Low Period Clock High Period tHIGH 0.6 Data Setup Time tSU:DAT 100 Data Hold Time tHD:DAT 0 ns 900 ns Maximum Receive SCL/SDA Rise Time tR 300 ns Maximum Receive SCL/SDA Fall Time tF 300 ns Setup Time for STOP Condition tSU:STO Capacitive Load for Each Bus Line Cb 0.6 µs 400 pF Note 3: All devices are 100% production tested at room temperature. All temperature limits are guaranteed by design. Note 4: Amplifier inputs are AC-coupled to GND. Note 5: Output levels higher than 825mW are not recommended for extended durations. Production tested with ZSPK = 8Ω + 68µH only. 6 _______________________________________________________________________________________ Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier GENERAL 6 8 7 6 11 10 fOSC = 700kHz 9 4 8 4 3.0 3.5 4.0 4.5 5.5 5.0 fOSC = 1100kHz 7 2.5 SUPPLY VOLTAGE (V) 3.0 3.5 4.0 4.5 5.0 2.5 5.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) VOLUME ATTENUATION vs. _VOL CONTROL CODE SHUTDOWN CURRENT vs. SUPPLY VOLTAGE 12 11 10 9 20 MAX9877 toc05 INPUTS AC-COUPLED TO GND VSDA = VSCL = 3.3V 0 VOLUME ATTENUATION (dB) MAX9877 toc04 14 13 fOSC = 1176kHz SPREAD-SPECTRUM MODE fOSC = 700kHz fOSC = 1100kHz 5 fOSC = 700kHz 2.5 HEADPHONE AND SPEAKER INPUTS AC-COUPLED TO GND OUTMODE = 9 VSDA = VSCL = 3.3V 12 fOSC = 1176kHz SPREAD-SPECTRUM MODE fOSC = 1100kHz 5 13 MAX9877 toc02 SPEAKER ONLY INPUTS AC-COUPLED TO GND OUTMODE = 7 VSDA = VSCL = 3.3V SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 9 fOSC = 1176kHz SREAD-SPECTRUM MODE SHUTDOWN CURRENT (μA) SUPPLY CURRENT (mA) HEADPHONE ONLY INPUTS AC-COUPLED TO GND OUTMODE = 8 VSDA = VSCL = 3.3V 7 10 MAX9877 toc01 9 8 SUPPLY CURRENT vs. SUPPLY VOLTAGE SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX9877 toc03 SUPPLY CURRENT vs. SUPPLY VOLTAGE -20 -40 -60 -80 fIN = 1kHz MEASURED AT HPL AND HPR -100 8 -120 7 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 5.5 35 30 25 20 15 10 5 0 _VOL CONTROL CODE _______________________________________________________________________________________ 7 MAX9877 Typical Operating Characteristics (VDD = PVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, volume controls = 0dB, OSC = 00, BYPASS = 0, SHDN = 1. Speaker loads (ZSPK) connected between OUT+ and OUT-. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = PVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, volume controls = 0dB, OSC = 00, BYPASS = 0, SHDN = 1. Speaker loads (ZSPK) connected between OUT+ and OUT-. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = +25°C, unless otherwise noted.) SPEAKER AMPLIFIER TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY VDD = PVDD = 3.7V ZSPK = 8Ω + 68μH VDD = PVDD = 3.7V ZSPK = 4Ω + 33μH DASHED LINES ARE LIMITED BY THE ABS. MAX RATINGS 10 1 POUT = 675mW THD+N (%) POUT = 200mW POUT = 1100mW 0.1 0.1 VDD = PVDD = 3V ZSPK = 8Ω + 68μH 1 THD+N (%) THD+N (%) 1 MAX9877 toc08 10 MAX9877 toc06 10 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY MAX9877 toc07 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY POUT = 425mW 0.1 POUT = 650mW POUT = 200mW 0.01 0.01 10 100 1k 10k 0.01 10 100k 100 1k 10k 100k 10 100 1k 10k FREQUENCY (Hz) TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER 1 10 MAX9877 toc10 VDD = PVDD = 3V ZSPK = 4Ω + 33μH VDD = PVDD = 3.7V POUT = 200mW ZSPK = 8Ω + 68μH fOSC = 700kHz MAX9877 toc11 FREQUENCY (Hz) 1 VDD = PVDD = 5V ZSPK = 8Ω + 68μH fIN = 6kHz POUT = 700mW THD+N (%) THD+N (%) 1 0.1 fOSC = 1176kHz 0.1 fIN = 20Hz 0.1 POUT = 250mW fOSC = 1100kHz 0.01 1k 100k 10k 10 FREQUENCY (Hz) 100 1k 10k 0.5 1.5 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER 10 MAX9877 toc12 VDD = PVDD = 5V ZSPK = 4Ω + 33μH DASHED LINES ARE LIMITED BY THE ABS. MAX RATINGS 1.0 OUTPUT POWER (W) TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER 10 0 100k FREQUENCY (Hz) 1 MAX9877 toc13 100 fIN = 1kHz 0.01 0.01 10 VDD = PVDD = 3.7V ZSPK = 8Ω + 68μH THD+N (%) THD+N (%) 1 fIN = 20Hz fIN = 6kHz 0.1 fIN = 20Hz 0.1 fIN = 6kHz fIN = 1kHz fIN = 1kHz 0.01 0.01 0 0.5 1.0 1.5 2.0 OUTPUT POWER (W) 8 100k FREQUENCY (Hz) MAX9877 toc09 10 THD+N (%) MAX9877 Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier 2.5 3.0 0 200 400 600 800 OUTPUT POWER (mW) _______________________________________________________________________________________ 1000 2.0 Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier VDD = PVDD = 3.7V ZSPK = 4Ω + 33μH DASHED LINES ARE LIMITED BY THE ABS. MAX RATINGS 1 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER 10 MAX9877 toc15 10 MAX9877 toc14 VDD = PVDD = 3V ZSPK = 8Ω + 68μH fIN = 6kHz 0.1 THD+N (%) 1 THD+N (%) fIN = 20Hz 0.1 fIN = 1kHz fIN = 1kHz 0.01 0.01 0.5 1.0 1.5 0.01 0 200 400 600 0 0.4 0.6 0.8 1.0 OUTPUT POWER (mW) OUTPUT POWER (W) TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER EFFICIENCY vs. OUTPUT POWER 1 100 MAX9877 toc18 VDD = PVDD = 3.7V fIN = 1kHz ZSPK = 8Ω + 68μH fOSC = 1100kHz 90 80 fOSC = 1176kHz SSM 0.1 EFFICIENCY (%) THD+N (%) fOSC = 700kHz 0.1 fOSC = 1176kHz SSM VDD = PVDD = 3.7V fIN = 6kHz ZSPK = 8Ω + 68μH fOSC = 1100kHz 0.01 200 400 800 600 60 40 10 200 400 0 800 600 80 100 ZSPK = 4Ω + 33μH 50 40 2.0 2.5 3.0 80 70 60 fOSC = 1176kHz AND 1100kHz 50 40 30 VDD = PVDD = 3.7V fIN = 1kHz DASHED LINES ARE LIMITED BY THE ABS. MAX RATINGS 10 1.5 fOSC = 700kHz 90 EFFICIENCY (%) 70 ZSPK = 8Ω + 68μH 1.0 EFFICIENCY vs. OUTPUT POWER MAX9877 toc20 90 20 0.5 OUTPUT POWER (W) EFFICIENCY vs. OUTPUT POWER 30 VDD = PVDD = 5V fIN = 1kHz DASHED LINES ARE LIMITED BY THE ABS. MAX RATINGS OUTPUT POWER (mW) 100 ZSPK = 4Ω + 33μH 0 0 OUTPUT POWER (mW) 60 ZSPK = 8Ω + 68μH 50 20 0.01 0 1.2 70 30 fOSC = 700kHz EFFICIENCY (%) THD+N (%) 0.2 OUTPUT POWER (W) MAX9877 toc17 1 fIN = 6kHz 0.1 fIN = 6kHz fIN = 1kHz 0 fIN = 20Hz MAX9877 toc19 THD+N (%) 1 fIN = 20Hz VDD = PVDD = 3V ZSPK = 4Ω + 33μH DASHED LINES ARE LIMITED BY THE ABS. MAX RATINGS MAX9877 toc21 10 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER MAX9877 toc16 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER VDD = PVDD = 3.7V fIN = 1kHz ZSPK = 8Ω + 68μH 20 10 0 0 0 0.5 1.0 OUTPUT POWER (W) 1.5 2.0 0 200 400 600 800 1000 OUTPUT POWER (mW) _______________________________________________________________________________________ 9 MAX9877 Typical Operating Characteristics (continued) (VDD = PVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, volume controls = 0dB, OSC = 00, BYPASS = 0, SHDN = 1. Speaker loads (ZSPK) connected between OUT+ and OUT-. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = PVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, volume controls = 0dB, OSC = 00, BYPASS = 0, SHDN = 1. Speaker loads (ZSPK) connected between OUT+ and OUT-. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = +25°C, unless otherwise noted.) OUTPUT POWER vs. SUPPLY VOLTAGE ZSPK = 4Ω + 33μH ZSPK = 8Ω + 68μH 50 40 30 10 1.5 1.0 VDD = PVDD = 3V fIN = 1kHz DASHED LINES ARE LIMITED BY THE ABS. MAX RATINGS 20 10% THD+N 2.0 1% THD+N 200 400 600 800 10% THD+N 1.0 0.8 1% THD+N 0.6 0 2.5 1000 3.0 3.5 4.0 4.5 5.0 5.5 2.5 3.0 3.5 4.0 4.5 5.0 OUTPUT POWER (mW) SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) OUTPUT POWER vs. LOAD RESISTANCE OUTPUT POWER vs. LOAD RESISTANCE POWER-SUPPLY REJECTION RATIO vs. FREQUENCY 1.0 OUTPUT POWER (W) 1.4 1.2 1.0 10% THD+N 0.6 VDD = PVDD = 3V fIN = 1kHz ZSPK = LOAD + 68μH 0 VDD = PVDD = 3.7V VRIPPLE = 100mVP-P INPUTS AC-COUPLED TO GND -10 -20 5.5 -30 0.8 0.6 PSRR (dB) 1.6 1.2 MAX9877 toc26 VDD = PVDD = 3.7V fIN = 1kHz ZSPK = LOAD + 68μH MAX9877 toc25 1.8 0.8 1.2 0.2 0 0 1.4 0.4 0.5 0 10% THD+N 0.4 1% THD+N -40 -50 -60 -70 1% THD+N 0.4 -80 0.2 0.2 -90 0 -100 0 10 20 30 40 50 60 70 80 90 100 0 LOAD RESISTANCE (Ω) -40 -60 -80 fOSC = 700kHz fIN = 1kHz -20 AMPLITUDE (dBV) AMPLITUDE (dBV) 10k IN-BAND OUTPUT SPECTRUM 0 MAX9877 toc28 fOSC = 1100kHz fIN = 1kHz -20 1k FREQUENCY (Hz) LOAD RESISTANCE (Ω) IN-BAND OUTPUT SPECTRUM 0 100 10 10 20 30 40 50 60 70 80 90 100 MAX9877 toc29 0 -40 -60 -80 -100 -100 -120 -120 -140 -140 0 5 10 FREQUENCY (kHz) 10 1.6 MAX9877 toc27 60 2.5 VDD = PVDD ZSPK = 8Ω + 68μH 1.8 OUTPUT POWER (W) 70 2.0 MAX9877 toc23 80 VDD = PVDD ZSPK = 4Ω + 33μH DASHED LINES ARE LIMITED BY THE ABS. MAX RATINGS 3.0 OUTPUT POWER (W) 90 EFFICIENCY (%) 3.5 MAX9877 toc22 100 OUTPUT POWER vs. SUPPLY VOLTAGE MAX9877 toc24 EFFICIENCY vs. OUTPUT POWER OUTPUT POWER (W) MAX9877 Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier 15 20 0 5 10 15 FREQUENCY (kHz) ______________________________________________________________________________________ 20 100k Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier IN-BAND OUTPUT SPECTRUM -20 AMPLITUDE (dBV) AMPLITUDE (dBV) -40 -60 -80 fOSC = 1100kHz INPUTS AC-COUPLED TO GND -10 MAX9877 toc31 fOSC = 1176kHz fIN = 1kHz -20 WIDEBAND OUTPUT SPECTRUM 0 MAX9877 toc30 0 -30 -40 -50 -60 -70 -100 -80 -120 -90 -140 -100 10 15 20 0.1 FREQUENCY (kHz) WIDEBAND OUTPUT SPECTRUM fOSC = 700kHz INPUTS AC-COUPLED TO GND -10 -40 -50 -60 -30 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 0.1 1 10 fOSC = 1176kHz INPUTS AC-COUPLED TO GND -20 AMPLITUDE (dBV) -30 100 0.1 1 10 FREQUENCY (MHz) FREQUENCY (MHz) HARDWARE SHUTDOWN RESPONSE SOFTWARE SHUTDOWN ON- AND OFF-RESPONSE MAX9877 toc34 AMPLITUDE (dBV) -20 VBIAS 500mV/div OUT+ - OUT1V/div 100 100 MAX9877 toc35 -10 10 WIDEBAND OUTPUT SPECTRUM 0 MAX9877 toc32 0 1 FREQUENCY (MHz) MAX9877 toc33 5 0 VSDA 2V/div OUT+ - OUT1V/div 20ms/div 20ms/div ______________________________________________________________________________________ 11 MAX9877 Typical Operating Characteristics (continued) (VDD = PVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, volume controls = 0dB, OSC = 00, BYPASS = 0, SHDN = 1. Speaker loads (ZSPK) connected between OUT+ and OUT-. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = PVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, volume controls = 0dB, OSC = 00, BYPASS = 0, SHDN = 1. Speaker loads (ZSPK) connected between OUT+ and OUT-. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = +25°C, unless otherwise noted.) HEADPHONE AMPLIFIER TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY VDD = PVDD = 3.7V RHP = 32Ω VDD = PVDD = 3.7V RHP = 16Ω 1 0.1 THD+N (%) POUT = 10mW POUT = 20mW POUT = 10mW 0.01 0.01 POUT = 20mW 0.001 10 100 1k 10k 0.01 POUT = 20mW POUT = 40mW 0.001 10 100k VDD = PVDD = 3V RHP = 32Ω 0.1 THD+N (%) THD+N (%) 0.1 MAX9877 toc38 1 MAX9877 toc36 0 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY MAX9877 toc37 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY 100 1k 0.001 10k 100k 10 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER VDD = PVDD = 3V RHP = 16Ω 10 MAX9877 toc40 10 MAX9877 toc39 1 VDD = PVDD = 3.7V RHP = 32Ω MAX9877 toc41 FREQUENCY (Hz) VDD = PVDD = 3.7V RHP = 16Ω 1 1 POUT = 15mW THD+N (%) THD+N (%) 0.1 THD+N (%) fIN = 20Hz 0.1 fIN = 20Hz AND 1kHz 0.1 0.01 0.01 0.01 0.001 0.001 0.001 100 1k 10k 100k 0 FREQUENCY (Hz) 10 20 0 40 30 10 MAX9877 toc42 VDD = PVDD = 3V RHP = 32Ω 30 40 50 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER 1 VDD = PVDD = 3V RHP = 16Ω THD+N (%) 1 fIN = 20Hz 0.1 0.01 fIN = 20Hz AND 1kHz 0.1 0.01 fIN = 6kHz fIN = 6kHz fIN = 1kHz 0.001 0.001 0 10 20 OUTPUT POWER (mW) 12 20 OUTPUT POWER (mW) TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER 10 10 OUTPUT POWER (mW) MAX9877 toc43 10 fIN = 6kHz fIN = 1kHz fIN = 6kHz POUT = 30mW THD+N (%) MAX9877 Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier 30 40 0 10 20 30 40 OUTPUT POWER (mW) ______________________________________________________________________________________ 50 60 60 70 Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier RHP = 16Ω 200 150 100 VDD = PVDD = 3.7V fIN = 1kHz POUT = PHPL + PHPR RHP = 32Ω 100 50 35 30 25 20 10 5 0 0 0 50 100 150 0 50 100 3.5 4.0 4.5 5.0 OUTPUT POWER (mW) SUPPLY VOLTAGE (V) OUTPUT POWER vs. SUPPLY VOLTAGE OUTPUT POWER vs. LOAD RESISTANCE OUTPUT POWER vs. LOAD RESISTANCE 1% THD+N 30 50 40 30 20 20 10 10 0 0 3.0 3.5 4.0 4.5 5.0 10% THD+N 5.5 70 20 30 40 50 60 70 80 10 90 100 20 30 40 50 60 70 80 90 100 LOAD RESISTANCE (Ω) 0 -10 40 30 VDD = PVDD = 3.7V VRIPPLE = 100mVP-P RHP = 32Ω INPUTS AC-COUPLED TO GND -20 -30 -40 PSRR (dB) C1 = C2 = 2.2μF -50 -60 -70 -80 HPR -90 -100 20 C1 = C2 = 0.47μF -110 -120 0 40 1% THD+N POWER-SUPPLY REJECTION RATIO vs. FREQUENCY 50 30 30 10 MAX9877 toc50 80 20 40 LOAD RESISTANCE (Ω) VDD = PVDD = 3V OSC = 10 fIN = 1kHz 1% THD+N 10 10% THD+N 50 0 10 100 10 60 20 OUTPUT POWER vs. LOAD RESISTANCE 60 70 1% THD+N SUPPLY VOLTAGE (V) 90 5.5 MAX9877 toc51 50 80 70 60 VDD = PVDD = 3V fIN = 1kHz 90 OUTPUT POWER (mW) 60 100 MAX9877 toc48 80 70 40 VDD = PVDD = 3.7V fIN = 1kHz 90 OUTPUT POWER (mW) 10% THD+N 80 100 MAX9877 toc47 fIN = 1kHz RHP = 16Ω 90 OUTPUT POWER (mW) 3.0 2.5 150 OUTPUT POWER (mW) 100 2.5 1% THD+N 15 VDD = PVDD = 3V fIN = 1kHz POUT = PHPL + PHPR RHP = 32Ω 10% THD+N 40 RHP = 16Ω 150 0 OUTPUT POWER (mW) MAX9877 toc45 200 fIN = 1kHz RHP = 32Ω 45 MAX9877 toc49 250 50 OUTPUT POWER (mW) POWER DISSIPATION (mW) 300 POWER DISSIPATION (mW) 250 MAX9877 toc44 350 50 OUTPUT POWER vs. SUPPLY VOLTAGE POWER DISSIPATION vs. OUTPUT POWER MAX9877 toc46 POWER DISSIPATION vs. OUTPUT POWER 50 60 70 LOAD RESISTANCE (Ω) 80 90 100 HPL 10 100 1k 10k 100k FREQUENCY (Hz) ______________________________________________________________________________________ 13 MAX9877 Typical Operating Characteristics (continued) (VDD = PVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, volume controls = 0dB, OSC = 00, BYPASS = 0, SHDN = 1. Speaker loads (ZSPK) connected between OUT+ and OUT-. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = PVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, volume controls = 0dB, OSC = 00, BYPASS = 0, SHDN = 1. Speaker loads (ZSPK) connected between OUT+ and OUT-. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = +25°C, unless otherwise noted.) OUTPUT SPECTRUM -40 -60 -80 -40 -60 -80 -100 -100 -120 -120 -140 -140 5 10 15 20 5 10 15 FREQUENCY (kHz) CROSSTALK vs. FREQUENCY COMMON-MODE REJECTION RATIO vs. FREQUENCY VDD = PVDD = 3.7V VINA_ = 1VP-P RHP = 16Ω 20 80 MAX9877 toc55 0 -10 -20 -30 -40 -50 -60 0 FREQUENCY (kHz) MAX9877 toc54 0 70 +9dB 60 CMRR (dB) HPR TO HPL -70 -80 -90 0dB 50 40 30 +20dB 20 HPL TO HPR -100 -110 -120 VDD = PVDD = 3.7V CMRR = 20log(ADM/ACM) 10 0 100 1k 10k 100k 10 100 1k 10k FREQUENCY (Hz) HARDWARE SHUTDOWN RESPONSE SOFTWARE SHUTDOWN ON- AND OFF-REPSONSE VBIAS 500mV/div VBIAS 500mV/div HPL 500mV/div HPL 500mV/div HPR 500mV/div HPR 500mV/div 20ms/div 100k MAX9877 toc57 FREQUENCY (Hz) MAX9877 toc56 10 14 VDD = PVDD = 3.7V fIN = 1kHz RHP = 16Ω -20 AMPLITUDE (dBV) AMPLITUDE (dBV) MAX9877 toc52 VDD = PVDD = 3.7V fIN = 1kHz RHP = 32Ω -20 0 MAX9877 toc53 OUTPUT SPECTRUM 0 CROSSTALK (dB) MAX9877 Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier 20ms/div ______________________________________________________________________________________ Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier ANALOG SWITCH TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER 10 MAX9877 toc59 EXTERNAL CLASS AB AMPLIFIER CONNECTED DIRECTLY TO RXIN+ AND RXIN- MAX9877 toc58 10 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER 1 1 THD+N (%) THD+N (%) f = 1kHz f = 20Hz AND 1kHz 0.1 0.1 f = 6kHz 0.01 f = 6kHz f = 20Hz EXTERNAL CLASS AB AMPLIFIER CONNECTED WITH 9Ω RESISTORS IN SERIES WITH RXIN+ AND RXIN- 0.01 0.001 0 25 50 OUTPUT POWER (mW) 75 100 0 10 20 30 40 50 60 70 80 OUTPUT POWER (mW) ______________________________________________________________________________________ 15 MAX9877 Typical Operating Characteristics (continued) (VDD = PVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, volume controls = 0dB, OSC = 00, BYPASS = 0, SHDN = 1. Speaker loads (ZSPK) connected between OUT+ and OUT-. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = +25°C, unless otherwise noted.) Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier MAX9877 Pin Description PIN NAME FUNCTION A1 HPR Right Headphone Output A2 HPL Left Headphone Output A3 VSS Headphone Amplifier Negative Power Supply. Bypass with a 1µF capacitor to PGND. A4 C1N Charge-Pump Flying Capacitor Negative Terminal. Connect a 1µF capacitor between C1P and C1N. A5 C1P Charge-Pump Flying Capacitor Positive Terminal. Connect a 1µF capacitor between C1P and C1N. B1 VDD Analog Supply. Connect to PVDD. Bypass with a 1µF capacitor to GND. B2 BIAS Common-Mode Bias. Bypass to GND with a 1µF capacitor. Pulse low to reset the part and place in shutdown (see the Typical Application Circuit). B3 SDA Serial-Data Input. Connect a pullup resistor from SDA to a 1.7V to 3.6V supply. B4 RXIN+ B5 OUT+ Positive Speaker Output C1 INB2 Input B2. Right input or positive input (see the Differential Input Configuration (ΔIN_) section). C2 INB1 Input B1. Left input or negative input (see the Differential Input Configuration (ΔIN_) section). C3 SCL Serial-Clock Input. Connect a pullup resistor from SCL to a 1.7V to 3.6V supply. C4 PGND Power Ground C5 PVDD Class D and Charge-Pump Power Supply. Bypass with a 1µF capacitor to PGND. D1 INA2 Input A2. Right input or positive input (see the Differential Input Configuration (ΔIN_) section). Receiver Bypass Positive Input D2 INA1 Input A1. Left input or negative input (see the Differential Input Configuration (ΔIN_) section). D3 GND Analog Ground D4 RXIN- Receiver Bypass Negative Input D5 OUT- Negative Speaker Output Detailed Description Signal Path The MAX9877 signal path consists of flexible inputs, signal mixing, volume control, and output amplifiers (Figure 1). The inputs can be configured for single-ended or differential signals (Figure 2). The internal preamplifiers feature three programmable gain settings of 0dB, +9dB, and +20dB. Following preamplification, the input signals are mixed, volume adjusted, and routed to the headphone and speaker amplifiers based on the output mode configuration (see Table 7). The volume control stages provide up to 75dB attenuation. The headphone amplifier is configured as a unity-gain 16 buffer while the speaker amplifier provides +12dB of additional gain. When an input is configured as mono differential it can be routed to the speaker or to both headphones. When an input is stereo, it is mixed to mono without attenuation for the speaker and kept stereo for the headphones. When the application does not require the use of both INA_ and INB_, the SNR of the MAX9877 is improved by deselecting the unused input through the I2C output mode register and AC-coupling the unused inputs to ground with a 330pF capacitor. The 330pF capacitor and the input resistance to the MAX9877 form a highpass filter preventing audible noise from coupling into the outputs. ______________________________________________________________________________________ Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier INPUT A 0dB/+9dB/+20dB INA1 INPUT B 0dB/+9dB/+20dB INB1 HPR 0dB HPL -75dB TO 0dB MIXER AND MUX INB2 0dB MAX9877 INA2 -75dB TO 0dB OUT+ +12dB OUT-75dB TO 0dB Figure 1. Signal Path STEREO SINGLE-ENDED IN_2 (R) R TO MIXER IN_1 (L) L DIFFERENTIAL IN_2 (+) IN_1 (-) TO MIXER Figure 2. Differential and Stereo Single-Ended Input Configurations ______________________________________________________________________________________ 17 Volume Control and Mute The MAX9877 features three volume control registers (see Table 4) allowing independent volume control of mono speaker and stereo headphone amplifier outputs. Each volume control register has 31 steps providing 0 to 75dB (typ) of attenuation and a mute function. Class D Speaker Amplifier The MAX9877 integrates a filterless Class D amplifier that offers much higher efficiency than Class AB without the typical disadvantages. The high efficiency of a Class D amplifier is due to the switching operation of the output stage transistors. In a Class D amplifier, the output transistors act as currentsteering switches and consume negligible additional power. Any power loss associated with the Class D output stage is mostly due to the I2R loss of the MOSFET on-resistance, and quiescent current overhead. The theoretical best efficiency of a linear amplifier is 78%, however, that efficiency is only exhibited at peak output power. Under normal operating levels (typical music reproduction levels), efficiency falls below 30%, whereas the MAX9877 still exhibits 70% efficiency under the same conditions (Figure 3). Ultra-Low EMI Filterless Output Stage In traditional Class D amplifiers, the high dV/dt of the rising and falling edge transitions results in increased EMI emissions, which requires the use of external LC filters or shielding to meet EN55022 electromagneticinterference (EMI) regulation standards. Limiting the dV/dt normally results in decreased efficiency. Maxim’s MAX9877 EFFICIENCY vs. IDEAL CLASS EFFICIENCY MAX9877 fig03 100 90 80 EFFICIENCY (%) MAX9877 Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier 70 MAX9877 60 50 IDEAL CLASS AB 40 30 20 VDD = PVDD = 3.7V (MAX9877) VSUPPLY = 3.7V (IDEAL CLASS AB) 10 0 0 0.25 0.50 0.75 1.00 OUTPUT POWER (W) Figure 3. MAX9877 Efficiency vs. Class AB Efficiency 18 active emissions limiting circuitry actively limits the dV/dt of the rising and falling edge transitions, providing reduced EMI emissions, while maintaining up to 87% efficiency. In addition to active emission limiting, the MAX9877 features a patented spread-spectrum modulation mode that flattens the wideband spectral components. Proprietary techniques ensure that the cycle-to-cycle variation of the switching period does not degrade audio reproduction or efficiency (see the Typical Operating Characteristics). Select spread-spectrum modulation mode through the I2C interface (Table 6). In spread-spectrum modulation mode, the switching frequency varies randomly by ±60kHz around the center frequency (1.176MHz). The effect is to reduce the peak energy at harmonics of the switching frequency. Above 10MHz, the wideband spectrum looks like white noise for EMI purposes (see Figure 4). Speaker Current Limit Most applications will not enter current limit unless the output is short circuited or connected incorrectly. When the output current of the speaker amplifier exceeds the current limit (1.5A, typ) the MAX9877 disables the outputs for approximately 250µs. At the end of 250µs, the outputs are re-enabled, if the fault condition still exists, the MAX9877 will continue to disable and reenable the outputs until the fault condition is removed. Bypass Mode The integrated DPST analog audio switch allows the MAX9877’s Class D amplifier to be bypassed. In bypass mode, the Class D amplifier is automatically disabled allowing an external amplifier to drive the speaker connected between OUT+ and OUT- through RXIN+ and RXIN- (see the Typical Application Circuit). The bypass switch is enabled at startup. The switch can be opened or closed even when the MAX9877 is in software shutdown (see the I2C Register Description section). Unlike discrete solutions, the switch design reduces coupling of Class D switching noise to the RXIN_ inputs. This eliminates the need for a costly T-switch. The bypass switch is typically used with two 9.1Ω resistors connected to each input. These resistors, in combination with the switch on-resistance and an 8Ω load, approximate the 32Ω load expected by the external amplifier. Although not required, using the resistors optimizes THD+N. Drive RXIN+ and RXIN- with a low-impedance source to minimize noise on the pins. In applications that do not require the bypass mode, leave RXIN+ and RXINunconnected. ______________________________________________________________________________________ Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier MAX9877 40 TEST LIMIT AMPLITUDE (dBμV/m) 35 30 25 20 MAX9877 OUTPUT 15 10 5 30 60 80 100 120 140 160 180 200 220 240 260 280 300 FREQUENCY (MHz) TEST LIMIT AMPLITUDE (dBμV/m) 40 35 25 MAX9877 OUTPUT 20 15 10 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 FREQUENCY (MHz) Figure 4. EMI with 152mm of Speaker Cable DirectDrive Headphone Amplifier Traditional single-supply headphone amplifiers have outputs biased at a nominal DC voltage (typically half the supply). Large coupling capacitors are needed to block this DC bias from the headphone. Without these capacitors, a significant amount of DC current flows to the headphone, resulting in unnecessary power dissipation and possible damage to both the headphone and headphone amplifier. Maxim’s patented DirectDrive architecture uses a charge pump to create an internal negative supply voltage. This allows the headphone outputs of the MAX9877 to be biased at GND while operating from a single supply (Figure 5). Without a DC component, there is no need for the large DC-blocking capacitors. Instead of two large (220µF, typ) capacitors, the MAX9877 charge pump requires two small ceramic capacitors, conserving board space, reducing cost, and improving the frequency response of the headphone amplifier. See the Output Power vs. Load Resistance graph in the Typical Operating Characteristics for details of the possible capacitor sizes. There is a low DC voltage on the amplifier outputs due to amplifier offset. However, the offset of the MAX9877 is typically ±0.15mV, which, when combined with a 32Ω load, results in less than 10µA of DC current flow to the headphones. In addition to the cost and size disadvantages of the DC-blocking capacitors required by conventional headphone amplifiers, these capacitors limit the amplifier’s low-frequency response and can distort the audio signal. Previous attempts at eliminating the output-coupling capacitors involved biasing the headphone return (sleeve) to the DC bias voltage of the headphone amplifiers. This method raises some issues: ______________________________________________________________________________________ 19 MAX9877 Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier 1) The sleeve is typically grounded to the chassis. Using the midrail biasing approach, the sleeve must be isolated from system ground, complicating product design. 2) During an ESD strike, the amplifier’s ESD structures are the only path to system ground. Thus, the amplifier must be able to withstand the full energy from an ESD strike. 3) When using the headphone jack as a line out to other equipment, the bias voltage on the sleeve may conflict with the ground potential from other equipment, resulting in possible damage to the amplifiers. The MAX9877 features a low-noise charge pump. The switching frequency of the charge pump is 1/2 of the Class D switching frequency, regardless of the operating mode. When the Class D amplifiers are operated in spread-spectrum mode, the charge pump also switches with a spread-spectrum pattern. The nominal switching frequency is well beyond the audio range, and thus does not interfere with audio signals. The switch drivers feature a controlled switching speed that minimizes noise generated by turn-on and turn-off transients. By limiting the switching speed of the charge pump, the di/dt noise VDD VDD/2 GND CONVENTIONAL AMPLIFIER BIASING SCHEME +VDD GND DirectDrive AMPLIFIER BIASING SCHEME -VDD (VSS) Figure 5. Traditional Amplifier Output vs. MAX9877 DirectDrive Output 20 caused by the parasitic trace inductance is minimized. Although not typically required, additional high-frequency noise attenuation can be achieved by increasing the size of C2 (see the Typical Application Circuit). The charge pump is active only in headphone modes. Headphone Current Limit The headphone amplifier current is limited to 140mA (typ). The current limit clamps the output current, which appears as clipping when the maximum current is exceeded. Shutdown Mode The MAX9877 features two ways of entering low-power shutdown. The hardware shutdown function is controlled by pulsing BIAS low for 1ms. While BIAS is low the amplifiers are shut down. Following an 80ms reset period, the MAX9877 reverts to its power-on-reset condition. Pull BIAS low using an open-drain output that is not pulled up with a resistor (see the Typical Application Circuit). The open-drain output leakage must not exceed 100nA and must be able to sink at least 1mA. The device can also be placed in shutdown mode by writing to the SHDN bit in the Output Control Register. Click-and-Pop Suppression The MAX9877 features click-and-pop suppression that eliminates audible transients from occurring at startup and shutdown. Use the following procedure to start up the MAX9877: 1) Configure the desired output mode and preamplifier gain. 2) Set the SHDN bit to 1 to start up the amplifier. 3) Wait 10ms for the startup time to pass. 4) Increase the output volume to the desired level. To disable the device simply set SHDN to 0. During the startup period, the MAX9877 precharges the input capacitors to prevent clicks and pops. If the output amplifiers have been programmed to be active they are held in shutdown until the precharge period is complete. When power is initially applied to the MAX9877, the power-on-reset state of all three volume control registers is mute. For most applications, the volume can be set to the desired level once the device is active. If the clickand-pop is too high, step through intermediate volume settings with zero-crossing detection disabled. Stepping through higher volume settings has a greater impact on click-and-pop than lower volume settings. For the lowest possible click-and-pop, start up the device at minimum volume and then step through each volume setting until the desired setting is reached. Disable zerocrossing detection if no input signal is expected. ______________________________________________________________________________________ Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier The MAX9877 is controlled through five I2C programmable registers. Table 1 shows the MAX9877’s complete register map. Tables 2, 3, and 5 show the individual registers. I2C Address The slave address of the MAX9877 is 1001101R/(W). Table 1. Register Map REGISTER ADDRESS POR STATE B7 B6 B5 B4 Input Mode Control 0x00 0x40 0 ZCD ΔINA ΔINB Speaker Volume Control 0x01 0x00 0 0 0 SVOL (Table 4) Left Headphone Volume Control 0x02 0x00 0 0 0 HPLVOL (Table 4) Right Headphone Volume Control 0x03 0x00 0 0 0 HPRVOL (Table 4) Output Mode Control 0x04 0x49 SHDN BYPASS OSC (Table 6) B3 REGISTER B3 B2 B1 PGAINA B0 PGAINB OUTMODE (Table 7) Table 2. Input Mode Control REGISTER 0x00 B7 B6 B5 B4 0 ZCD ΔINA ΔINB I2C Register Description Zero-Crossing Detection (ZCD) Zero-crossing detection limits distortion in the output signal during volume transitions by delaying the transition until the mixer output crosses the internal bias voltage. A timeout period (typically 60ms) forces the volume transition if the mixer output signal does not cross the bias voltage. 1 = Zero-crossing detection is enabled. 0 = Zero-crossing detection is disabled. Differential Input Configuration (ΔIN_) The inputs INA_ and INB_ can be configured for mono differential or stereo single-ended operation. B2 PGAINA B1 B0 PGAINB 1 = IN_ is configured as a mono differential input with IN_2 as the positive and IN_1 as the negative input. 0 = IN_ is configured as a stereo single-ended input with IN_2 as the right and IN_1 as the left input. Preamplifier Gain (PGAIN_) The preamplifier gain of INA_ and INB_ can be programmed by writing to PGAIN_. 00 = 0dB 01 = +9dB 10 = +20dB 11 = Reserved ______________________________________________________________________________________ 21 MAX9877 I2C Interface MAX9877 Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier Table 3. Speaker/Left Headphone/Right Headphone Volume Control REGISTER B7 B6 B5 0x01 0 0 0 B4 B3 B2 B1 0x02 0 0 0 HPLVOL (Table 4) 0x03 0 0 0 HPRVOL (Table 4) B0 SVOL (Table 4) Volume Control The device has a separate volume control for left headphone, right headphone, and speaker amplifiers. The total system gain is a combination of the input gain, the volume control, and the output amplifier gain. Table 4 shows the volume settings for each volume control. Table 4. Volume Control Settings CODE _VOL B2 B1 B0 GAIN (dB) CODE _VOL B4 B3 B2 B1 B0 GAIN (dB) B4 B3 0 0 0 0 0 0 MUTE 16 1 0 0 0 0 -23 1 0 0 0 0 1 -75 17 1 0 0 0 1 -21 1 0 0 1 0 -19 2 0 0 0 1 0 -71 18 3 0 0 0 1 1 -67 19 1 0 0 1 1 -17 4 0 0 1 0 0 -63 20 1 0 1 0 0 -15 1 0 1 0 1 -13 5 0 0 1 0 1 -59 21 6 0 0 1 1 0 -55 22 1 0 1 1 0 -11 7 0 0 1 1 1 -51 23 1 0 1 1 1 -9 1 1 0 0 0 -7 8 0 1 0 0 0 -47 24 9 0 1 0 0 1 -44 25 1 1 0 0 1 -6 10 0 1 0 1 0 -41 26 1 1 0 1 0 -5 11 0 1 0 1 1 -38 27 1 1 0 1 1 -4 12 0 1 1 0 0 -35 28 1 1 1 0 0 -3 13 0 1 1 0 1 -32 29 1 1 1 0 1 -2 14 0 1 1 1 0 -29 30 1 1 1 1 0 -1 15 0 1 1 1 1 -26 31 1 1 1 1 1 0 Table 5. Output Mode Control REGISTER 0x04 B7 B6 SHDN BYPASS B5 SHDN) Shutdown (S 1 = MAX9877 operational. 0 = MAX9877 in low-power shutdown mode. 22 B4 OSC (Table 6 ) B3 B2 B1 B0 OUTMODE (Table 7) SHDN is an active-low shutdown bit that overrides all settings and places the entire device in low-power shutdown mode. The I2C interface is fully active in this shutdown mode and bypass mode remains operational. All register settings are preserved while in shutdown. ______________________________________________________________________________________ Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier Output Configuration (OUTMODE) The MAX9877 has a stereo DirectDrive headphone amplifier and a mono Class D amplifier. Table 7 shows how each of the output amplifiers can be configured and connected to the input signals. For simplicity, not all possible combinations of ΔINA and ΔINB are shown. 0 = Bypass mode disabled. This mode does not control headphone operation. Table 6. Oscillator Modes OSC CLASS D OSCILLATOR MODE (kHz) CHARGE-PUMP OSCILLATOR MODE (kHz) 0 1176, spread spectrum 588, spread spectrum 0 1 1100, fixed frequency 550, fixed frequency 1 0 700, fixed frequency 1 1 B1 B0 0 350, fixed frequency Reserved Table 7. Output Modes ΔIN_ = 0 (THE SINGLE-ENDED INPUT SIGNALS ARE DEFINED AS IN_1 = LEFT AND IN_2 = RIGHT) OUTMODE MODE B3 B2 B1 B0 0 0 0 0 0 1 0 0 0 1 2 0 0 1 3 0 0 1 4 0 1 5 0 6 0 7 SPK LEFT HP RIGHT HP ΔIN_ = 1 (THE DIFFERENTIAL INPUT SIGNAL IS DEFINED AS IN_Δ = IN_2 - IN_1) SPK Reserved LEFT HP RIGHT HP Reserved INA1+INA2 — — 0 — INA1 INA2 — INAΔ INAΔ 1 INA1+INA2 INA1 INA2 INAΔ INAΔ INAΔ 0 0 INB1+INB2 — — INBΔ — — 1 0 1 — INB1 INB2 — INBΔ INBΔ 1 1 0 INB1+INB2 INB1 INB2 INBΔ INBΔ INBΔ 0 1 1 1 INA1+INA2 +INB1+INB2 — — INAΔ+INBΔ — — 8 1 0 0 0 — INA1+INB1 INA2+INB2 — INAΔ +INBΔ INAΔ +INBΔ 9 1 0 0 1 INA1+INA2 +INB1+INB2 INA1+INB1 INA2+INB2 INAΔ+INBΔ INAΔ +INB_ INAΔ +INBΔ 10–15 Reserved INAΔ — — Reserved — = Amplifier Off ______________________________________________________________________________________ 23 MAX9877 Bypass Mode (BYPASS) 1 = MAX9877 bypass switches are closed and the Class D amplifier is disabled. MAX9877 Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier I2C Interface Specification The MAX9877 features an I2C/SMBus™-compatible, 2wire serial interface consisting of a serial-data line (SDA) and a serial-clock line (SCL). SDA and SCL facilitate communication between the MAX9877 and the master at clock rates up to 400kHz. Figure 6 shows the 2-wire interface timing diagram. The master generates SCL and initiates data transfer on the bus. The master device writes data to the MAX9877 by transmitting the proper slave address followed by the register address and then the data word. Each transmit sequence is framed by a START (S) or REPEATED START (Sr) condition and a STOP (P) condition. Each word transmitted to the MAX9877 is 8 bits long and is followed by an acknowledge clock pulse. A master reading data from the MAX9877 transmits the proper slave address followed by a series of nine SCL pulses. The MAX9877 transmits data on SDA in sync with the master-generated SCL pulses. The master acknowledges receipt of each byte of data. Each read sequence is framed by a START (S) or REPEATED START (Sr) condition, a not acknowledge, and a STOP (P) condition. SDA operates as both an input and an open-drain output. A pullup resistor, typically greater than 500Ω, is required on SDA. SCL operates only as an input. A pullup resistor, typically greater than 500Ω, is required on SCL if there are multiple masters on the bus, or if the single master has an open-drain SCL output. Series resistors in line with SDA and SCL are optional. Series resistors protect the digital inputs of the MAX9877 from high voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals. Bit Transfer One data bit is transferred during each SCL cycle. The data on SDA must remain stable during the high period of the SCL pulse. Changes in SDA while SCL is high are control signals (see the START and STOP Conditions section). START and STOP Conditions SDA and SCL idle high when the bus is not in use. A master initiates communication by issuing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA while SCL is high (Figure 7). A START condition from the master signals the beginning of a transmission to the MAX9877. The master terminates transmission, and frees the bus, by issuing a STOP condition. The bus remains active if a REPEATED START condition is generated instead of a STOP condition. SDA tBUF tSU:STA tSU:DAT tSU:STA tHD:DAT tLOW tSU:STO SCL tHIGH tHD:STA tR tF REPEATED START CONDITION START CONDITION STOP CONDITION Figure 6. 2-Wire Interface Timing Diagram S Sr P SCL SDA Figure 7. START, STOP, and REPEATED START Conditions SMBus is a trademark of Intel Corp. 24 ______________________________________________________________________________________ START CONDITION Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier Slave Address The MAX9877 is preprogrammed with a slave address of 1001101R/(W). The address is defined as the seven most significant bits (MSBs) followed by the Read/Write bit. Setting the Read/Write bit to 1 configures the MAX9877 for read mode. Setting the Read/Write bit to 0 configures the MAX9877 for write mode. The address is the first byte of information sent to the MAX9877 after the START condition. Acknowledge The acknowledge bit (ACK) is a clocked 9th bit that the MAX9877 uses to handshake receipt each byte of data when in write mode (see Figure 8). The MAX9877 pulls down SDA during the entire master-generated 9th clock pulse if the previous byte is successfully received. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master may retry communication. The master pulls down SDA during the ninth clock cycle to acknowledge receipt of data when the MAX9877 is in read mode. An acknowledge is sent by the master after each read byte to allow data transfer to continue. A not acknowledge is sent when the master reads the final byte of data from the MAX9877, followed by a STOP condition. Write Data Format A write to the MAX9877 includes transmission of a START condition, the slave address with the R/W bit set to 0, one byte of data to configure the internal register address pointer, one or more bytes of data, and a STOP condition. Figure 9 illustrates the proper frame format for writing one byte of data to the MAX9877. Figure 10 illustrates the frame format for writing n-bytes of data to the MAX9877. The slave address with the R/W bit set to 0 indicates that the master intends to write data to the MAX9877. The MAX9877 acknowledges receipt of the address byte during the master-generated 9th SCL pulse. CLOCK PULSE FOR ACKNOWLEDGMENT START CONDITION SCL 1 2 8 9 NOT ACKNOWLEDGE SDA ACKNOWLEDGE Figure 8. Acknowledge ACKNOWLEDGE FROM MAX9877 B7 ACKNOWLEDGE FROM MAX9877 S SLAVE ADDRESS 0 B6 B5 B4 B3 B2 B1 B0 ACKNOWLEDGE FROM MAX9877 A R/W REGISTER ADDRESS A DATA BYTE A P 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 9. Writing One Byte of Data to the MAX9877 ______________________________________________________________________________________ 25 MAX9877 Early STOP Conditions The MAX9877 recognizes a STOP condition at any point during data transmission except if the STOP condition occurs in the same high pulse as a START condition. For proper operation, do not send a STOP condition during the same SCL high pulse as the START condition. MAX9877 Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier The second byte transmitted from the master configures the MAX9877’s internal register address pointer. The pointer tells the MAX9877 where to write the next byte of data. An acknowledge pulse is sent by the MAX9877 upon receipt of the address pointer data. The third byte sent to the MAX9877 contains the data that will be written to the chosen register. An acknowledge pulse from the MAX9877 signals receipt of the data byte. The address pointer autoincrements to the next register address after each received data byte. This autoincrement feature allows a master to write to sequential registers within one continuous frame. Figure 10 illustrates how to write to multiple registers with one frame. The master signals the end of transmission by issuing a STOP condition. contents of register 0x00. Transmitted data is valid on the rising edge of SCL. The address pointer autoincrements after each read data byte. This autoincrement feature allows all registers to be read sequentially within one continuous frame. A STOP condition can be issued after any number of read data bytes. If a STOP condition is issued followed by another read operation, the first data byte to be read will be from register 0x00. The address pointer can be preset to a specific register before a read command is issued. The master presets the address pointer by first sending the MAX9877‘s slave address with the R/W bit set to 0 followed by the register address. A REPEATED START condition is then sent followed by the slave address with the R/W bit set to 1. The MAX9877 then transmits the contents of the specified register. The address pointer autoincrements after transmitting the first byte. The master acknowledges receipt of each read byte during the acknowledge clock pulse. The master must acknowledge all correctly received bytes except the last byte. The final byte must be followed by a not acknowledge from the master and then a STOP condition. Figure 11 illustrates the frame format for reading one byte from the MAX9877. Figure 12 illustrates the frame format for reading multiple bytes from the MAX9877. Register addresses greater than 0x04 are reserved. Do not write to these addresses. Read Data Format Send the slave address with the R/W bit set to 1 to initiate a read operation. The MAX9877 acknowledges receipt of its slave address by pulling SDA low during the 9th SCL clock pulse. A START command followed by a read command resets the address pointer to register 0x00. The first byte transmitted from the MAX9877 will be the ACKNOWLEDGE FROM MAX9877 ACKNOWLEDGE FROM MAX9877 S SLAVE ADDRESS B7 B6 B5 B4 B3 B2 B1 B0 ACKNOWLEDGE FROM MAX9877 0 A REGISTER ADDRESS ACKNOWLEDGE FROM MAX9877 A A DATA BYTE 1 R/W B7 B6 B5 B4 B3 B2 B1 B0 DATA BYTE n 1 BYTE A P 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 10. Writing n-Bytes of Data to the MAX9877 NOT ACKNOWLEDGE FROM MASTER ACKNOWLEDGE FROM MAX9877 ACKNOWLEDGE FROM MAX9877 S SLAVE ADDRESS 0 R/W A REGISTER ADDRESS ACKNOWLEDGE FROM MAX9877 A REPEATED START Sr SLAVE ADDRESS 1 R/W A DATA BYTE A P 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 11. Reading One Indexed Byte of Data from the MAX9877 26 ______________________________________________________________________________________ Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier SLAVE ADDRESS 0 R/W A REGISTER ADDRESS A Sr REPEATED START SLAVE ADDRESS 1 DATA BYTE A R/W A P 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 12. Reading n-Bytes of Indexed Data from the MAX9877 Applications Information OUT+ Filterless Class D Operation Traditional Class D amplifiers require an output filter to recover the audio signal from the amplifier’s output. The filters add cost, increase the solution size of the amplifier, and can decrease efficiency and THD+N performance. The traditional PWM scheme uses large differential output swings (2 x VDD(P-P)) and causes large ripple currents. Any parasitic resistance in the filter components results in a loss of power, lowering the efficiency. The MAX9877 does not require an output filter. The device relies on the inherent inductance of the speaker coil and the natural filtering of both the speaker and the human ear to recover the audio component of the square-wave output. Eliminating the output filter results in a smaller, less costly, more efficient solution. Because the frequency of the MAX9877 output is well beyond the bandwidth of most speakers, voice coil movement due to the square-wave frequency is very small. Although this movement is small, a speaker not designed to handle the additional power can be damaged. For optimum results, use a speaker with a series inductance > 10µH. Typical 8Ω speakers exhibit series inductances in the 20µH to 100µH range. Component Selection Optional Ferrite Bead Filter In applications where speaker leads exceed 20mm, additional EMI suppression can be achieved by using a filter constructed from a ferrite bead and a capacitor to ground. A ferrite bead with low DC resistance, highfrequency (> 1.176MHz) impedance of 100Ω to 600Ω, and rated for at least 1A should be used. The capacitor value varies based on the ferrite bead chosen and the actual speaker lead length. Select a capacitor less than 1nF based on EMI performance. Input Capacitor An input capacitor, CIN, in conjunction with the input impedance of the MAX9877 forms a highpass filter that removes the DC bias from an incoming signal. The AC- MAX9877 OUT- Figure 13. Optional Ferrite Bead Filter coupling capacitor allows the amplifier to automatically bias the signal to an optimum DC level. Assuming zero source impedance, the -3dB point of the highpass filter is given by: 1 f−3dB = 2πRINCIN Choose CIN so that f-3dB is well below the lowest frequency of interest. Use capacitors whose dielectrics have low-voltage coefficients, such as tantalum or aluminum electrolytic. Capacitors with high-voltage coefficients, such as ceramics, may result in increased distortion at low frequencies. BIAS Capacitor BIAS is the output of the internally generated DC bias voltage. The BIAS bypass capacitor, CBIAS, reduces power supply and other noise sources at the common-mode bias node. Bypass BIAS with a 1µF capacitor to GND. Charge-Pump Capacitor Selection Use capacitors with an ESR less than 100mΩ for optimum performance. Low-ESR ceramic capacitors minimize the output resistance of the charge pump. Most surfacemount ceramic capacitors satisfy the ESR requirement. For best performance over the extended temperature range, select capacitors with an X7R dielectric. Flying Capacitor (C1) The value of the flying capacitor (C1) affects the output resistance of the charge pump. A C1 value that is too small degrades the device’s ability to provide sufficient current drive, which leads to a loss of output voltage. ______________________________________________________________________________________ 27 MAX9877 S ACKNOWLEDGE FROM MAX9877 ACKNOWLEDGE FROM MAX9877 ACKNOWLEDGE FROM MAX9877 Increasing the value of C1 reduces the charge-pump output resistance to an extent. Above 1µF, the on-resistance of the switches and the ESR of C1 and C2 dominate. PVDD Bulk Capacitor (C3) In addition to the recommended PVDD bypass capacitance, bulk capacitance equal to C3 should be used. Place the bulk capacitor as close to the device as possible. MAX9877 fig14 Output Holding Capacitor (C2) The output capacitor value and ESR directly affect the ripple at VSS. Increasing the value of C2 reduces output ripple. Likewise, decreasing the ESR of C2 reduces both ripple and output resistance. Lower capacitance values can be used in systems with low maximum output power levels. See the Output Power vs. Load Resistance graph in the Typical Operating Characteristics. RF SUSCEPTIBILITY -10 -30 EFFICIENCY (dBμ) MAX9877 Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier -50 THRESHOLD OF HEARING -70 MAX9877 -90 -110 -130 NOISE FLOOR -150 10 Proper layout and grounding are essential for optimum performance. Use wide traces for the power-supply inputs and amplifier outputs to minimize losses due to parasitic trace resistance. Wide traces also aid in moving heat away from the package. Proper grounding improves audio performance, minimizes crosstalk between channels, and prevents any switching noise from coupling into the audio signal. Connect PGND and GND together at a single point on the PCB. Route all traces that carry switching transients away from GND and the traces/components in the audio signal path. Connect PVDD to a 2.7V to 5.25V source. Bypass PVDD to the PGND pin with a 1µF ceramic capacitor. Additional bulk capacitance should be used to prevent power-supply pumping. Place the bypass capacitors as close to the MAX9877 as possible. Connect VDD to PVDD. Bypass VDD to GND with a 1µF capacitor. Place the bypass capacitors as close to the MAX9877 as possible. RF Susceptibility GSM radios transmit using time-division multiple access (TDMA) with 217Hz intervals. The result is an RF signal with strong amplitude modulation at 217Hz that is easily demodulated by audio amplifiers. Figure 14 shows the susceptibility of the MAX9877 to a transmitting GSM radio placed in close proximity. Although there is measurable noise at 217Hz and its harmonics, the noise is well below the threshold of hearing using typical headphones. In RF applications, improvements to both layout and component selection decreases the MAX9877’s sus- 28 100 1k 10k 100k FREQUENCY (Hz) Supply Bypassing, Layout, and Grounding Figure 14. MAX9877 Susceptibility to a GSM Cell Phone Radio ceptibility to RF noise and prevent RF signals from being demodulated into audible noise. Trace lengths should be kept below 1/4 the wavelength of the RF frequency of interest. Minimizing the trace lengths prevents them from functioning as antennas and coupling RF signals into the MAX9877. The wavelength λ in meters is given by: 108 λ = c/f m/s, and f = the RF frequency of where c = 3 x interest. Route audio signals on middle layers of the PCB to allow ground planes above and below shield them from RF interference. Ideally the top and bottom layers of the PCB should primarily be ground planes to create effective shielding. Additional RF immunity can also be obtained from relying on the self-resonant frequency of capacitors as it exhibits the frequency response similar to a notch filter. Depending on the manufacturer, 10pF to 20pF capacitors typically exhibit self resonance at RF frequencies. These capacitors, when placed at the input pins, can effectively shunt the RF noise at the inputs of the MAX9877. For these capacitors to be effective, they must have a low-impedance, low-inductance path to the ground plane. Do not use microvias to connect to the ground plane as these vias do not conduct well at RF frequencies. ______________________________________________________________________________________ Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier MAX9877 WLP Applications Information For the latest application details on WLP construction, dimensions, tape carrier information, PCB techniques, bump-pad layout, and recommended reflow temperature profile, as well as the latest information on reliability testing results, refer to the Application Note: UCSP—A Wafer-Level Chip-Scale Package on Maxim’s website at www.maxim-ic.com/ucsp. See Figure 15 for the recommended PCB footprint for the MAX9877. 45±5μm 250μm Figure 15. PCB Footprint Recommendation Diagram ______________________________________________________________________________________ 29 MAX9877 Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier Typical Application Circuit VBATT VBATT C2 1μF VSS PVDD VDD A3 C3 1μF 1μF C5 B1 C1N A4 C1 1μF MAX9877 CHARGE PUMP C1P A5 1μF -75dB TO 0dB 0dB INPUT A 0dB/+9dB/+20dB 1μF 0dB MIXER AND MUX INA1 D2 A2 HPL B5 OUT+ D5 OUT- -75dB TO 0dB INB2 C1 INPUT B 0dB/+9dB/+20dB INPUT B 1μF HPR INA2 D1 INPUT A 1μF A1 CLASS D MODULATOR +12dB INB1 C2 -75dB TO 0dB OPEN-DRAIN GPIO BIAS B2 1μF SDA SCL B3 I2C CONTROL C3 BYPASS 9.1Ω RxIN+ B4 BASEBAND RECEIVER AMPLIFIER 9.1Ω RxIN- D4 D3 C4 GND PGND Chip Information Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 20 WLP W202A2+2 21-0059 PROCESS: BiCMOS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 30 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.