ICS ICS1889

ICS1889
Integrated
Circuit
Systems, Inc.
100Base-FX Integrated PHYceiverTM
General Description
Features
The ICS1889 is a fully integrated physical layer device
supporting 100 Megabits per second CSMA/CD Fast
Ethernet fiber optic applications. It is designed to support
the requirements of DTEs (adapter cards), repeaters and
switches. It is compliant with the ISO/IEC 8802 Fast
Ethernet standard for 100Base-FX. It provides a Media
Independent Interface (MII) allowing direct chip-to-chip
connection, motherboard-to-daughter board connection or
connection via a cable in a similar manner to the AUI
approach used with 10Base-Tsystems. A station
management interface is provided to receive command
information and send status information. It transmits and
receives NRZI data and interfaces directly to the optical
transceiver. It can operate in either half duplex or full
duplex.
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One chip integrated physical layer
All CMOS, low power design
ISO/IEC 8802-3 CSMA/CD compliant
100Base-FX Half & Full Duplex
Far end fault detection
Media Independent Interface (MII)
Station management interface
Extended register set including QuickPollTM detailed
status monitoring
Transmit clock synthesis
Receive clock and data recovery
Detailed receive error reporting
Extended Test Modes
52-pin MQFP package with 2.0 mil body thickness
Block Diagram
PHYceiver and QuickPoll are trademarks of Integrated Circuit Systems, Inc.
ICS1889RevF092497P
ICS1889
Block Diagram
When transmitting, the ICS1889 encapsulates the MAC
frame (including the preamble) with the start-of-stream
(SSD) and end-of-stream (ESD) delimiters. When receiving,
it strips off the SSD and substitutes the normal preamble
pattern and then presents this and subsequent preamble
nibbles to the MII. When it encounters the ESD it ends the
presentation of nibbles to the MII. Thus, the MAC
reconciliation layer sees an exact copy of the transmitted
frame.
Functional Description
Introduction
The ICS1889 is a nibble to bit stream and bit stream to nibble
processor. When transmitting, it takes sequential nibbles
presented at the Media Independent Interface (MII) and
translates them to a serial bit stream for transmission on the
media. When receiving, it takes the serial bit stream from the
media and translates it to sequential nibbles for presentation
to the MII. It has no knowledge of the underlying structure of
the MAC frame it is conveying.
During periods when no frames are being transmitted or
received, there is a requirement to signal and detect the idle
condition. This allows the higher levels to determine the
integrity of the connection between the node and the hub. A
continuous stream of ones is transmitted to signify the idle
condition, the receive channel includes logic that monitors
the IDLE data stream to look for this pattern and thereby
establish the link integrity.
2
ICS1889
Media Independent Interface (MII)
clock for synchronous transfer, a receive data valid signal and
a receive error signal. Both the transmit clock and receive
clock are sourced by the ICS1889. The ICS1889 provides the
MII signals carrier sense and collision detect. In half duplex
mode, carrier sense indicates that data is being transmitted or
received, and in full duplex mode it indicates that data is
being received. Collision detect indicates that data has been
received while a transmission is in progress.
The ICS1889 implements a fully compliant IEEE 802.3µ
Media Independent Interface for connection to MACs or
repeaters which allows connections between the ICS1889
and MAC on the same board, motherboard/daughter board or
via a cable in a similar manner to AUI connections.
The MII is a specification of signals and protocols which
formalizes the interfacing of a 10/100 Mbps Ethernet Media
Access Controller (MAC) to the underlying physical layer.
The specification is such that different physical media may be
supported (such as 100Base-TX, 100Base-T4 and 100BaseFX) transparently to the MAC.
The MII also specifies a two wire interface and a protocol
between station management and the physical layer. The
ICS1889 implements this interface providing a bidirectional
data line and a clock input for synchronizing the data
transfers. This interface allows station management to read
and write all of the ICS1889 registers.
The MII specifies transmit and receive data paths. Each path
is 4-bits wide allowing for transmission of a nibble or single
symbol. The transmit data path includes a transmit clock for
synchronous transfer, a transmit enable signal and a transmit
error signal. The receive data path includes a receive data
The ICS1889 is designed to allow hot insertion of an MII
cable into the MAC. During the power-up phase, the
ICS1889 will isolate the MII and the transmit pair by
tristating the PHY outputs.
3
ICS1889
Transmit Clock Synthesizer
Carrier Detector & Framer
The ICS1889 synthesizes the transmit clock using a PLL to
produce 25 MHz and 125 MHz clocks. This allows the use of
a low cost 25 MHz crystal or a low jitter reference frequency
source.
The carrier detector examines the receive serial bit stream
looking for the SSD, the “JK” symbol pair. In the idle state,
IDLE symbols (all logic ones) will be received. If the carrier
detector detects a logic zero in the bit stream, it examines the
following bits looking for the first two non-contiguous zeroes,
confirms that the first 5-bits form the “J” symbol (11000) and
asserts carrier detect. At this point the serial data is framed
and the second symbol is checked to confirm the “K” symbol
(10001). If successful, the following framed data (symbols)
are presented to the 4B5B decoder. If the “JK” pair is not
confirmed, the false carrier detect bit is asserted in the
QuickPoll Register and the idle state is reentered.
Receive Clock Recovery
The receive clock recovery logic monitors the receive line and
detects a “receive signal.” The logic, which includes a PLL,
extracts data and clock from the 100Base-FX, 125 Mbps,
NRZI bit stream. In the event that the PLL is unable to lock on
to the receive signal, it generates a “not locked signal.” The
transmit clock synthesizer provides a center frequency
reference for operation of the clock recovery circuit in the
absence of data. The “receive signal detected” and “not
locked” signals are both used by the logic which monitors the
receive channel for errors.
4
ICS1889
The ICS1889 replaces the first two nibbles with the start-ofstream delimiter (the “JK” symbol pair). Following the last
nibble, the ICS1889 adds the end-of-stream delimiter (the
“TR” symbol pair).
4B/5B Encoder/Decoder
The ICS1889 uses a 4B5B coding scheme. This maps a 4-bit
nibble to a 5-bit code group called a symbol. Five bits allow
32 possible symbols, 16 are used for data encoding, 6 are used
for control and 10 are not used and are invalid. The control
symbols used are “JK” as the SSD, “TR” as the ESD, “I” as
the IDLE symbol and “H” to signal an error. All other
symbols are invalid and, if detected, will set the receive error
bit in the status register, and cause the RXER signal to be
asserted (see Table 1 below).
When receiving, 5-bit code groups are converted to nibbles
and presented to the MII. If the ICS1889 detects one or more
invalid symbols, it sets the Invalid Symbol bit (17:7) in the
QuickPoll Status Register. When receiving a frame, the first
two 5-bit code groups received are the start-of-stream
delimiter (the “JK” symbol pair), the ICS1889 strips them
and substitutes two nibbles of the normal preamble pattern.
The last two 5-bit code groups are the end-of-stream delimiter
(the “TR” symbol pair), these are stripped from the nibbles
presented to the MAC.
When transmitting, nibbles from the MII are converted to a 5bit code groups. During transmission, the first 16 nibbles
obtained from the MII are the MAC frame preamble.
Table 1: 4B5B Encoding
0
1
2
3
4
5
6
7
Data
Data
Data
Data
Data
Data
Data
Data
0
1
2
3
4
5
6
7
4B Code
3210
0000
0001
0010
0011
0100
0101
0110
0111
I
J
K
T
R
H
V
V
Idle
SSD
SSD
ESD
ESD
Error
Invalid
Invalid
Undefined
0101
0101
Undefined
Undefined
Undefined
Undefined
Undefined
Symbol
I
J
K
T
R
H
V
V
Meaning
Idle
SSD
SSD
ESD
ESD
Error
Invalid
Invalid
1
1
1
1
0
0
0
0
5B Code
43210
11110
01001
10100
10101
01010
01011
01110
01111
1
1
1
0
0
0
0
0
1
1
0
1
0
0
0
0
1
0
0
1
1
1
0
0
1
0
0
0
1
0
0
0
Symbol
1
0
1
1
1
0
0
1
Invalid Error Code Test
111
11111
110
11000
011
10001
001
01101
111
00111
100
00100
000
00000
001
00001
1. The IDLE symbol is sent continuously between frames.
2. J and K are the SSD and are always sent in pairs.
3. K always follows J.
Meaning
8
9
A
B
C
D
E
F
Data
Data
Data
Data
Data
Data
Data
Data
8
9
A
B
C
D
E
F
V
V
V
V
V
V
V
V
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
4B Code
3210
1000
1001
1010
1011
1100
1101
1110
1111
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
TXER asserted
V
Invalid
V
Invalid
V
Invalid
V
Invalid
V
Invalid
V
Invalid
V
Invalid
V
Invalid
4. T and R are the ESD and are always sent in pairs.
5. R always follows T.
6. A HALT symbol is used to signal an error condition.
5
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
1
1
0
1
0
1
0
0
0
1
1
0
0
0
0
1
5B Code
43210
10010
10011
10110
10111
11010
11011
11100
11101
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
0
0
0
1
1
0
0
0
0
1
ICS1889
Line Transmitter
Signal Error Detector
The differential driver for the TX ± is current mode and is
designed to drive resistive terminations in a complementary
fashion. The output is current-sinking only, with the amount
of sink current programmable via the IPRG1 pin. The sink
current is equal to four times the IPRG1 current. For most
applications, an 910Ω resistor from VDD to IPRG1 will set
the current to the necessary precision.
Remote Fault Signaling
The Line Transmitter output pair is a differential positive ECL
(PECL) interface designed to connect directly to a standard
fiber optic transceiver. The differential driver for the transmit
signal is a programmable current source designed for resistive
termination. Using an external resistor connected to the IPRG
pin, the output current may be preset.
The ICS1889 Signal Error Detector is part of the clock
recovery PLL. It detects a Receive Signal Error if no receive
signal is received and detects a PLL Lock Error if the PLL is
unable to lock on to the receive channel signal. A receive
channel error is defined as the loss of receive signal or the loss
of PLL lock.
Remote fault signaling allows a node to indicate receive
channel errors to its Link Partner using its transmit channel.
When used by both nodes on a link segment, the integrity of
both the transmit and receive channels can be verified.
Since 100Base-FX systems do not use auto-negotiation, an
alternative, in-band signaling scheme is used to signal remote
fault conditions. This scheme, Far End Fault Indication, relies
on the characteristics of the quiescent state, (a continuous
IDLE stream). The IDLE stream is a continuous stream of
logic ones and a carrier is defined as the receipt of two
noncontiguous logic zeroes. A Far End Fault is signaled with
84 logic ones followed by one logic zero, with the pattern
repeated at least three times.
The TX± pins are incapable for sourcing current, so VOH must
be set by the ratios of the Thevenin termination resistors for
each of the lines. R1 is a pull-up resistor connected from the
PECL output to VDD. R2 is a pull-down resistor connected
from the PECL output to VSS. R1 and R2 are electrically in
parallel from an AC standpoint. If we pick a target impedance
of 50Ω for our transmission line impedance, a value of 62Ω
for R1 and a value of 300Ω for R2 would yield a Thevenin
equivalent characteristic impedance of 49.7Ω and a VOH
value of VDD -.88 volts, compatible with PECL circuits.
A Far End Fault will be signaled under three conditions; the
first is when no activity is received from the Link Partner,
since this can indicate a broken receive wire. The second is
when the clock recovery circuit detects a Receive Signal Error
or PLL Lock Error. The third is when a management entity
sets the Transmit Far End Fault bit (16:3).
To set a value for VOL, we must determine a value for I prg
that will cause the output FET’s to sink an appropriate current.
We desire VOL to be VDD -1.81 or greater. Setting up a sink
current of 19 milliamperes would guarantee this through our
output termination resistors. As this is controlled by
4/1 current mirror, 4.75mA into I prg should set this current
properly. A 910Ω resistor from VDD to I prg should work fine.
Far End Fault signaling continues until the condition causing
the fault ceases.
Far End Fault Detection
The Far End Fault detector monitors the receive data serial bit
stream looking for a repetitive pattern of 84 logic ones
followed by a logic zero. Non-ICS1889 PHYs may have
different definitions of what constitutes a remote fault.
However, an ICS1889 will always respond to the in-band
error signaling scheme. If the ICS1889 detects three
consecutive patterns described above, it will signal a far end
fault to the Link Monitor.
Line Receiver
The Line Receiver is a differential input pair designed to
interface directly to a standard fiber optic transceiver. It is a
differential PECL input buffer.
Link Monitor
If the Link Monitor receives a far end fault indication or a
local receive channel error, it causes the ICS1889 to enter the
IDLE mode, isolate the MII and assert the Link Status bit in
the Status Register. Once the far end fault condition is deasserted, the Link Monitor will return to the Link OK
condition if the local receive channel is clear of errors. Once
detected, a receive channel error signal will be indicated from
330 to 1000 microseconds.
6
ICS1889
Management Interface
Register Address
The ICS1889 uses this field to select one of the registers
within the set. If a nonexistent register is specified, the
ICS1889 ignores the command.
The ICS1889 provides a management interface to connect to
a management entity. The two wire serial interface is part of
the MII and is described in the MII section. The interface
allows the transport of status information from the ICS1889
to the management entity and the transport of command
words to the ICS1889. It includes a register set, a frame
format, and a protocol.
TA
This 2-bit field is used by the ICS1889 to avoid contention
during read transactions. When writing to the ICS1889, the
TA bits should be set to 10. When reading from the ICS1889,
the device will tristate during this time.
Management Register Set
The register set includes the mandatory basic control and
status registers and an extended set. The ICS1889 implements
the following registers.
Data
This is a 16-bit field with bit 15 being the first bit sent or
received.
Control
Status
PHY Identifier
PHY Identifier
Extended Control
QuickPoll Status
Idle
The ICS1889 is in the high impedance state during the idle
condition.
(register 0)
(register 1)
(register 2)
(register 3)
(register 16)
(register 17)
Register Access Rules
RO
CW
RW/0
RW
Management Frame Structure
The management interface uses a serial bit stream with a
specified frame structure and protocol as defined below.
Preamble
SOF
Op Code
Address
Register
TA
Data
Idle
11...11
01
10 (read), 01 (write)
AAAAA
RRRRR
NN
DD...DD
Zo
–
–
–
–
Read Only, writes ignored
Command Override Writable
Read/Write only logic zero
Read/Write
Four types of register access are supported by the device.
Read Only (RO) bits may be read, but writes are ignored.
Command Override Writable (CW) bits may be read, but
writes are ignored unless preceded by writing a logic one to
the Command Register Override bit (16:15). Read Write Zero
(RW/0) bits may be read, but must only be written with a logic
zero value. Writing a logic one to this type of bit may prevent
the device from operating normally. Read Write (RW) bits
may be read and may be written to any value.
(32 ones)
(5 bits)
(5 bits)
(2 bits)
(16 bits)
high impedance
Default Values
Preamble
The ICS1889 looks for a pattern of 32 logic ones followed by
the SOF delimiter before responding to a transaction.
—
0
1
Pin
Start of Frame
Following the preamble a start of frame delimiter of zero-one
initiates a transaction.
Modifier
Operation Code
The valid codes are 10 for a read operation and 01 for a write
operation. Other codes are ignored.
SC
LL
LH
Address
There may be up to 32 PHYs attached to the MII. This 5 bit
address is compared to the internal address of the ICS1889, as
set by the P[0...4]* pins, for a match.
–
–
–
–
No default value
Default to logic zero
Default to logic one
Default depends on the state of
the named pin
–
–
–
Self Clearing
Latching Low
Latching High
Self clearing bits will clear without any further writes after a
specified amount of time. Latching bits are used to capture an
event. To obtain the current status of a latching bit, the bit
must be read twice in succession. If the special condition still
persists, the bit will be the same on the second read;
otherwise, the condition indication will not be present.
7
ICS1889
Control Register (register 0)
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Function
Reset
Loop Back
Data Rate
Auto-Negotiate Enable
Power-Down
Isolate
Effect when bit = 0
No Effect
Disable loop back mode
Always set to a logic one
No Effect
Normal Mode
No Effect
Effect when bit = 1
Reset PHY
Enable loop back mode
100 Mpbs operation
Always set to logic zero
Reduced power consumption
Isolate PHY from MII
Restart Auto-Negotitation
Duplex Mode
Collision Test
Reserved
Reserved
Reserved
No Effect
Half Duplex
No Effect
Always set to logic zero
Full Duplex
Enable collision signal test
Reserved
Reserved
Reserved
If read, bits 0-6 and bits 9 and 12 will return logic
zeroes and bit 13 will return a logic one.
Writes to these bits will have no effect.
Control Register (register 0)
Access
RW/SC
RW
RO
RO
RW
RW
RO
RW
RW
RO
RO
RO
RO
RO
RO
RO
Default
0
0
1
0
0
0 if PHY
Address
< >0,
1 if PHY
Address=0
0
0
0
0
0
0
0
0
0
0
Data Rate (bit 13)
The control register is a 16-bit read/write register used to set
the basic configuration modes of the ICS1889. It is accessed
through the management interface of the MII.
This bit is permanently set to a logic one indicating that only
the 100 Mbps mode is supported.
Auto-Negotiation Enable (bit 12)
Reset (bit 15) default = 0
This feature is not available with fiber optic solutions. This bit
is permanently set to a logic zero indicating that it is not
supported.
Setting this bit to a logic 1 will result in the ICS1889 setting
all its status and control registers to their default values.
During this process the ICS1889 may change internal states
and the states of physical links attached to it. While in process,
the bit will remain set and no other write commands to the
control register will be accepted. The reset process will be
completed within 500 ms and the bit will be cleared indicating
that the reset process is complete.
Power-Down (bit 11)
Setting it to logic one will cause the ICS1889 to isolate its
transmit data output and its MII interface with the exception
of the management interface. The ICS1889 will then enter a
power-down mode where only the management interface and
logic remain active. Setting this bit to logic zero after it has
been set to a logic one will cause the ICS1889 to power-up its
logic and then reset all error conditions. It then enables
transmit data and the MII interface. This process takes 500 ms
to complete.
Loop Back (bit 14)
Setting this bit to a logic one causes the ICS1889 to tristate
the transmit circuitry from sending data and the receive
circuitry from receiving data. The collision detection circuitry
is also disabled unless the collision test command bit is set.
Data presented to the MII transmit data path is returned to the
MII receive data path (see ICS1889 Block Diagram, page 2).
8
ICS1889
Isolate (bit 10)
Setting this bit to a logic one causes the ICS1889 to isolate its
data paths from the MII. In this mode, sourced signals
(TXCLK, RXCLK, RXDV, RXER, RXD0-3, COL and CRS)
are in a high impedance state and input signals (TXD0-3,
TXEN and TXER) are ignored. The management interface is
unaffected by this command.
When the PHY address is set to 0, the device will power-up in
the isolated mode (bit 10=1). For all other addresses, the
default will be bit 10 = 0.
Restart Auto-Negotiation (bit 9)
This feature is not available with fiber optic solutions. This
bit is permanently set to a logic zero indicating that it is not
supported.
Duplex Mode (bit 8)
Setting this bit to a logic one causes the ICS1889 to operate in
the full duplex mode and setting this bit to a logic zero causes
it to operate in the half duplex mode. If the ICS1889 is
operating in loop back mode, this bit will have no effect on
the operation.
Collision Test (bit 7)
This command bit is used to test that the collision circuitry is
working when the ICS1889 is operating in the loop back
mode. Setting this bit to a logic one causes the ICS1889 to
assert the collision signal within 512 bit times of TXEN being
asserted and to de-assert it within 4-bit times of TXEN being
de-asserted. Setting this bit to a logic zero causes the
ICS1889 to operate in the normal mode.
Reserved (Bits 6 through 0)
These bits are reserved for future IEEE standards. When read,
logic zeroes are returned. Writing has no effect on ICS1889
operation.
9
ICS1889
Control Register (register 1)
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Definition
OUI bit 19 | s
OUI bit 20 | t
OUI bit 21 | u
OUI bit 22 | v
OUI bit 23 | w
OUI bit 24 | x
Manufacturer’s Model Number
Manufacturer’s Model Number
Manufacturer’s Model Number
Manufacturer’s Model Number
Manufacturer’s Model Number
Manufacturer’s Model Number
Revision Number bit 3
Revision Number bit 2
Revision Number bit 1
Revision Number bit 0
When bit = 0
bit
bit
bit
bit
bit
bit
When bit = 1
5
4
3
2
1
0
Status Register (register 1)
Access
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
Default
0
1
1
0
0
0
0
0
0
0
0
1
0
1
0
1
Reserved (bits 10 through 6)
The ICS1889 status register is a 16 bit read only register
used to indicate the basic status of the ICS1889. It is
accessed via the management interface of the MII. It is
initialized during a power-up or reset to predefined default
values. If the ICS1889 is enabled for auto-configuration,
certain bits in the status register may be set to zero as defined
below.
These bits are reserved for future IEEE standards. When read,
logic zeroes are returned. Writing has no effect on ICS1889
operation.
Auto-Negotiation Complete (bit 5)
This bit is permanently set to a logic zero.
Remote Fault (bit 4)
100Base-T4 (bit 15)
When set to a logic one, this bit indicates that a remote fault
(Far End Fault) has been detected by the Link Monitor. This
bit remains set to a logic one until it is cleared by reading the
status register or by a reset command
This bit is permanently set to a logic zero indicating that the
ICS1889 is not able to support 100Base-T4 operation.
100Base-X Full Duplex (bit 14)
This bit defaults to a logic one indicating that the ICS1889 is
able to support 100Base-X Full Duplex operation.
If the link partner is implemented with a non-ICS1889 device,
the causes of a link failure will be specified by that PHY
vendor. If the link partner is implemented with an ICS1889, a
remote fault indication means a receive channel error
occurred.
100Base-X Half Duplex (bit 13)
This bit defaults to a logic one indicating that the ICS1889 is
able to support 100Base-X Half Duplex operation.
Auto-Negotiation Ability (bit 3)
10 Mbps Full Duplex (bit 12)
This feature is not available with fiber optic solutions. This bit
is permanently set to a logic zero indicating that it is not
supported.
This bit is permanently set to a logic zero indicating that
10Base-T is not supported.
10 Mbps Half Duplex (bit 11)
This bit is permanently set to a logic zero indicating that
10Base-T is not supported.
10
ICS1889
Link Status (bit 2)
When set to a logic one, this bit indicates that the Link
Monitor has established a valid link. If the Link Monitor
detects a link failure, this bit is set to a logic zero and remains
zero through the next read of the status register. A link failure
may be due to an error in the receive channel or an error in the
receive channel of the link partner (that is, a “remote fault”).
Jabber detect (bit 1)
This bit is permanently set to a logic zero.
Extended Capability (bit 0)
This bit is permanently set to a logic one indicating that the
ICS1889 has an extended register set.
11
ICS1889
PHY Identifier Register (register 2)
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OUI
OUI
OUI
OUI
OUI
OUI
OUI
OUI
OUI
OUI
OUI
OUI
OUI
OUI
OUI
OUI
Definition
bit 3 | c
bit 4 | d
bit 5 | e
bit 6 | f
bit 7 | g
bit 8 | h
bit 9 | i
bit 10 | j
bit 11 | k
bit 12 | l
bit 13 | m
bit 14 | n
bit 15 | o
bit 16 | p
bit 17 | q
bit 18 | r
When bit = 0
When bit = 1
Access
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
PHY Identifier Register (register 2)
Binary Format:
Organizationally Unique Identifier
bits 3-18(bits 15-0)
IEEE Standard 802 Lettered Format
Register 2 and Register 3 contain the 24-bit Organizationally
Unique Identifier (OUI), Manufacturers Model Number and
Revision Number. Integrated Circuit Systems’s OUI is used as
the default for registers 2 and 3. These values may be
overridden using the Command Override bit (16:15).
0
0
0000 0000


lsb
msb
(I/G)
0000
abcd
This field contains the lowest 16 bits of the IEEE OUI
excluding bits 0, 1, and 2. Bit 3 of the OUI maps to bit 15 of
the register.
0000
efgh
0
0000

lsb
A
0101

msb
0000 0101
ijkl
mnop
E
0111

lsb
0111
qrst
Default
0
1
1
0
0
0
0
0
0
0
0
1
0
1
0
1
B
1101

msb
1101
uvwx
Model and Revision Information
Model
Part
1
ICS1889
2
ICS1890
The revision number will be incremented each time the silicon
is significantly revised.
OUI Formatting Information
The ICS OUI is shown below with information on mapping
the OUI value into registers 2 and 3.
Octet Format:
These two registers can always be read and may be written by
setting the Command Override bit in the Configuration
register (16:15) and then performing a write operation. At
power-up and reset they are set to Integrated Circuit
Systems’s OUI. By allowing these registers to be written, a
systems vendor may substitute their own OUI.
00
A0
BE
|
|
Third octet
|
Second octet
First octet
12
ICS1889
PHY Identifier Register (register 3)
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Definition
OUI bit 19 | s
OUI bit 20 | t
OUI bit 21 | u
OUI bit 22 | v
OUI bit 23 | w
OUI bit 24 | x
Manufacturer’s Model Number
Manufacturer’s Model Number
Manufacturer’s Model Number
Manufacturer’s Model Number
Manufacturer’s Model Number
Manufacturer’s Model Number
Revision Number bit 3
Revision Number bit 2
Revision Number bit 1
Revision Number bit 0
When bit = 0
bit
bit
bit
bit
bit
bit
When bit = 1
5
4
3
2
1
0
PHY Identifier Register (register 3)
Access
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
Default
0
1
1
0
0
0
0
0
0
0
0
1
0
1
0
1
Manufacturer’s Model Number bits 5-0 (bits 9-4)
Register 2 and Register 3 contain the 24 bit Organizationally
Unique Identifier (OUI), Manufacturers Model Number and
Revision Number. Integrated Circuit Systems’s OUI is used as
the default for registers 2 and 3.
Model
1
2
Part
ICS1889
ICS1890
Revision Number bits 3-0 (bits 3-0)
These two registers can always be read and may be written by
setting the Command Override bit in the Configuration
register (16:15) and then performing a write operation. At
power-up and reset they are set to Integrated Circuit Systems’
OUI. By allowing these registers to be written, a systems
vendor may substitute their own OUI.
The revision number will be incremented each time the silicon
is significantly revised. Currently the device is at revision 1.
See register 2 for OUI formatting information.
Organizationally Unique Identifier
bits 19-24 (bits 15-10)
This field contains the upper 6 bits of the IEEE OUI. Bit 19 of
the OUI maps to bit 15 of the register.
13
ICS1889
Extended Control Register (register 16)
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Definition
Command Register Override
Reserved for ICS
Reserved for ICS
Reserved for ICS
Reserved for ICS
PHY address - S4
PHY address - S3
PHY address - S2
PHY address - S1
PHY address - S0
Reserved for ICS
Far End Fault
Transmit Far End Fault
Invalid Error Code Test
Reserved for ICS
Reserved for ICS
When bit = 0
When bit = 1
Don’t allow write
Allow write
Write logic zero. Read unspecified.
Write logic zero. Read unspecified.
Write logic zero. Read unspecified.
Write logic zero. Read unspecified.
MII management
Register address code
0 - 31 Read Only
Write logic zero. Read unspecified.
Disabled
Enabled
No fault transmitted
Fault transmitted
Disabled
Enabled
Write logic zero. Read unspecified.
Write logic zero. Read unspecified.
Extended Control Register (register 16)
Access
RW
RW/0
RW/0
RW/0
RW/0
CW
CW
CW
CW
CW
RW/0
RW
RW
RW
RW/0
RW/0
Default
0
—
—
—
—
P4RD
P3TD
P2LI
P1CL
P0FD
—
1
0
0
—
—
Reserved (bit 12)
The Extended Control Register is a 16-bit read write register
used to pre-program the ICS1889. At power-up and reset, this
register will be loaded to the default values specified. It may
subsequently be read or written. If written, the result is bit
dependent as discussed below.
This bit is reserved for ICS use. It must always be written with
a logic zero. The value of this bit when read is unspecified and
may be a logic zero or one.
Reserved (bit 11)
This bit is reserved for ICS use. It must always be written with
a logic zero. The value of this bit when read is unspecified and
may be a logic zero or one.
Command Register Override (bit 15)
If set to a logic one, this bit allows a subsequent write to the
Status Register (register 1) and the PHY identifier registers 2
and 3. The contents of registers 2 and 3 may be set to any
value. The Status Register may have certain specified bits set
or reset. The first write to registers 1, 2 or 3 after this bit is set
will reset it preventing subsequent writes from having any
effect.
PHY Address (Bits 10 through 6)
These 5 bits are used to indicate the address of the ICS1889
on the management port of the MII (any number in the range
0 - 31). A read returns the address. Extra care should be taken
if a command override write is performed on these bits, as a
change in the PHY address must be accounted for by the
device reading and writing to the MII Management interface.
Reserved (bit 14)
This bit is reserved for ICS use. It must always be written with
a logic zero. The value of this bit when read is unspecified and
may be a logic zero or one.
Reserved (bit 5)
This bit is reserved for ICS use. It must always be written with
a logic zero. The value of this bit when read is unspecified and
may be a logic zero or one.
Reserved (bit 13)
This bit is reserved for ICS use. It must always be written with
a logic zero. The value of this bit, when read, is unspecified
and may be a logic zero or one.
14
ICS1889
Enable Far End Fault (bit 4)
If this bit is set to a logic one, the far end fault logic becomes
active resulting in faults being signaled and recognized via the
“in-band” signaling scheme. If this bit is set to a logic zero,
the far end fault logic is disabled.
Transmit Far End Fault (bit 3)
Management may indicate a fault has occurred to its link
partner by setting this bit to a logic one. Indicating a fault
brings the link down and disables the reception of data until
this bit is cleared and the link is reestablished.
Invalid Error Code Test (bit 2)
If this bit is set to a logic one, the 4B5B encoder operates as a
5B5B encoder obtaining the fifth bit of the code group from
the value of TXER.
Reserved (bit 1)
This bit is reserved for ICS use. It must always be written with
a logic zero. A read always returns a logic zero.
Reserved (bit 0)
This bit is reserved for ICS use. It must always be written with
a logic zero. A read always returns a logic zero.
15
ICS1889
QuickPoll Status Register (register 17)
BIT
15
14
Definition
Data Rate
Duplex
When bit = 0
Always a logic one
Half duplex selected
When bit = 1
100 Mbps selected
Full duplex selected
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved for ICS
Reserved for ICS
Reserved for ICS
Receive Signal Error
PLL Lock Error
False Carrier Detect
Invalid Symbol
Halt Symbol
Premature End
Reserved for ICS
Reserved for ICS
Priority Pin State
Remote Fault
Link Status
Read unspecified
Read unspecified
Read unspecified
Signal
PLL locked
Normal carrier or idle
Valid symbols
Normal symbols
Normal stream
Read unspecified
Read unspecified
Hardware
No remote fault detected
Link is not valid
QuickPoll Status Register (register 17)
The QuickPoll status register is a 16-bit read only register
used to indicate the comprehensive status of the ICS1889. All
register status bits that might need to be repetitively examined
at run time are located in this register, even though some bits
duplicate functionality from other registers. This allows the
device status to be rapidly obtained with a single register
access.
The register is accessed via the management interface of the
MII. It can always be read and may be written by setting the
override bit in the Configuration Register (register 16, bit 15)
and then performing a write operation. It is initialized during a
power-up or reset to predefined default values.
16
Loss of signal
PLL failed to lock
False carrier detected
Invalid symbol detected
HALT symbol detected
Stream with two IDLES
Software
Remote fault detected
Link is valid
Access
RO
RO
RO
RO
RO
RO/LH
RO/LH
RO/LH
RO/LH
RO/LH
RO/LH
RO
RO
RO
RO/LH
RO/LL
Default
1
0 if PRIO=1 or
DPEN if PRIO=0
—
—
—
0
0
0
0
0
0
—
—
PRIO
0
0
ICS1889
Halt Symbol (bit 6)
Data Rate (bit 15)
If set to a logic one, the halt symbol (bit 6) indicates that the
ICS1889 has detected the halt symbol in a frame since bit 11
was last reset. This bit will remain set until cleared by reading
the contents of register 17. It is initialized to logic zero.
This bit is permanently set to a logic one indicating it only
operates at 100 Mbps.
Duplex (bit 14)
If set to a logic one, this bit indicates that the full duplex mode
has been selected. If set to a logic zero, it indicates that the
half duplex mode has been selected. It is initialized to logic
zero.
Premature End (bit 5)
This bit is normally a logic zero indicating normal data
streams. If two IDLE symbols are detected during the
reception of a receive data stream, this bit is set to a logic one
and the ICS1889 returns to the idle state This bit is initialized
to a logic zero.
Reserved (bit 13)
This bit is reserved for ICS use. The value of this bit is
unspecified and may be a logic zero or one.
Reserved (bit 4)
Reserved (bit 12)
This bit is reserved for ICS use. The value of this bit is
unspecified and may be a logic zero or one.
This bit is reserved for ICS use. The value of this bit is
unspecified and may be a logic zero or one.
Reserved (bit 3)
Reserved (bit 11)
This bit is reserved for ICS use. The value of this bit is
unspecified and may be a logic zero or one.
This bit is reserved for ICS use. The value of this bit is
unspecified and may be a logic zero or one.
Priority Pin State (bit 2)
Receive Signal Error (bit 10)
This bit reflects the setting of the Priority Pin (pin 17). When
this bit is a logic zero, duplex mode is controlled by the
Duplex Enable pin (pin 18). When this bit is a logic one,
duplex mode is controlled by the Duplex Mode bit (0:8).
If set to a logic one, the Receive Signal error bit indicates that
the ICS1889 read channel has at some point been unable to
detect the receive channel signal. This bit will remain set until
cleared by reading the contents of register 17. It is initialized
to logic zero.
Remote Fault (bit 1)
This is a copy of the Remote Fault bit of the Status Register
(register 1).
PLL Lock Error (bit 9)
If set to a logic one, the loss of PLL lock (bit 9) indicates that
the ICS1889 read channel PLL has failed to lock on to the
read channel signal. This bit will remain set until cleared by
reading the contents of register 17. It is initialized to logic
zero.
Link Status (bit 0)
This is a copy of the Link Status bit of the Status Register
(register 1).
False Carrier (bit 8)
If set to a logic one, the false carrier (bit 8) indicates that the
ICS1889 has detected a false carrier sometime since this bit
was last reset. This bit will remain set until cleared by reading
the contents of register 17. It is initialized to logic zero.
Invalid Symbol (bit 7)
If set to a logic one, the invalid symbol (bit 7) indicates that an
invalid symbol has been detected in a received frame since the
bit was last reset. This bit will remain set until cleared by
reading the contents of register 17. It is initialized to logic
zero.
17
ICS1889
Pin Definitions
Signal
TXCLK
TXEN
TXD3
TXD2
TXD1
TXD0
TXER
RXCLK
RXDV
RXD3
RXD2
RXD1
RXD0
RXER
CRS
COL
MDC
MDIO
Meaning
Signal
TX+
TX–
IPRG
RX+
RX–
REF+
REF–
SD+
SD–
Transmit Clock
Transmit Enable
Transmit Data 3
Transmit Data 2
Transmit Data 1
Transmit Data 0
Transmit Error
Receive Clock
Receive Data Valid
Receive Data 3
Receive Data 2
Receive Data 1
Receive Data 0
Receive Error
Carrier Sense
Collision Detect
SYSR
PRIO
DPEN
LSTA
P4RD
P3TD
P2LI
P1CL
P0FD
NOD/REP
Management Data Clock
Management Data Input/Output
Meaning
Transmitted data positive
Transmitted Data negative
Current program
Receive Data positive
Receive Data negative
Frequency reference
Frequency reference
Signal Detect
Signal Detect
System reset
Priority
Duplex Enable
Link Status
Receive data LED
Transmit data LED
Link Integrity LED
Collision detect LED
Full duplex LED
Node or Repeater Mode Selection
MII Interface Pin Descriptions
Transmit Clock TXCLK
Transmit Data 3 TXD3
The Transmit Clock (TXCLK) is a continuous clock signal
generated by the ICS1889 to synchronize the Transmit
Enable, Transmit Data and Transmit Error lines. The
ICS1889 clock frequency is 25% of the nominal transmit data
rate. At 100 Mbps its frequency is 25 MHz. The TXCLK
clock duty cycle is in the range 35% to 65%.
Transmit Data 3 (TXD3) is the most significant bit of the
transmit data nibble. TXD3 is sampled by the ICS1889
synchronously with the Transmit Data Clock when TXEN is
asserted. When TXEN is de-asserted the ICS1889 is
unaffected by the state of TXD3
Transmit Data 2 TXD2
Transmit Enable TXEN
Transmit Data 2 (TXD2) is sampled by the ICS1889
synchronously with the Transmit Data Clock when TXEN is
asserted. When TXEN is de-asserted the ICS1889 is
unaffected by the state of TXD2.
Transmit Enable (TXEN) indicates to the ICS1889 that the
MAC is sending valid data nibbles for transmission on the
physical media. Synchronous with its assertion the ICS1889
will begin reading the data nibbles on the transmit data lines.
It is the responsibility of the MAC to order the nibbles so that
the preamble is sent first, followed by destination, source,
length, data and CFS fields since the ICS1889 has no
knowledge of the frame structure and is merely a “nibble”
processor. The ICS1889 terminates transmission of nibbles
following the deassertion of Transmit Enable (TXEN).
Transmit Data 1 TXD1
Transmit Data 1 (TXD1) is sampled by the ICS1889
synchronously with the Transmit Data Clock when TXEN is
asserted. When TXEN is de-asserted the ICS1889 is
unaffected by the state of TXD1.
18
ICS1889
Receive Data Valid RXDV
Transmit Data 0 TXD0
Receive Data Valid (RXDV) is generated by the ICS1889. It
indicates that the ICS1889 is recovering and decoding data
nibbles on the Receive Data (RXD) data lines synchronous
with the Receive Data Clock (RXCLK). It is the responsibility
of the MAC to assemble nibbles into MAC frames since the
ICS1889 has no knowledge of the frame structure and is
merely a “nibble” processor. The ICS1889 asserts RXDV
when it detects a start of stream delimiter (SSD) and deasserts it following the last data nibble or upon detection of a
signal error. RXDV is synchronous with the Receive Data
Clock (RXCLK).
Transmit Data 0 (TXD0) is the least significant bit of the
transmit data nibble. TXD0 is sampled by the ICS1889
synchronously with the Transmit Data Clock when TXEN is
asserted. When TXEN is de-asserted the ICS1889 is
unaffected by the state of TXD0.
Transmit Error TXER
The assertion of Transmit Error (TXER) for one or more clock
periods will cause the ICS1889 to emit one or more HALT
symbols. The signal is synchronous with TXCLK. In the
normal operating mode, a HALT symbol will be substituted
for the next nibble encoded. If the invalid error code test bit in
the Configuration Register is set (register 16, bit 2), TXER
becomes an additional input to the 4B5B encoder. This allows
the ICS1889 to send the full set of 32 symbols including the
invalid symbols. Table 1 shows the modified 4B5B encoding
in the test mode. A timing diagram for TXER is shown in
Figure xxx.
Receive Data RXD3
Receive Data 3 (RXD3) is the most significant bit of the
receive data nibble. RXD is sourced by the ICS1889. When
Receive Data Valid (RXDV) is asserted by the ICS1889, it
will transfer the fourth bit of the symbol synchronously with
Receive Clock (RXCLK).
Receive Data RXD2
Receive Clock RXCLK
Receive Data 2 (RXD2) is sourced by the ICS1889. When
Receive Data Valid (RXDV) is asserted by the ICS1889, it
will transfer the third bit of the symbol synchronously with
Receive Clock (RXCLK).
The Receive Clock (RXCLK) is sourced by the ICS1889.
There are two possible sources for the Receive Clock
(RXCLK). When a carrier is present on the receive pair, the
source is the recovered clock from the data stream. When no
carrier is present on the receive pair, the source is
synchronized to the transmit PLL. The IDLE symbol is sent
during periods of inactivity and the Recovered clock will be
selected.
Receive Data RXD1
Receive Data 1 (RXD1) is sourced by the ICS1889. When
Receive Data Valid (RXDV) is asserted by the ICS1889, it
will transfer the second bit of the symbol synchronously with
Receive Clock (RXCLK).
The ICS1889 will only switch between clock sources when
Receive Data Valid (RXDV) is de-asserted. During the period
between Carrier Sense (CRS) being asserted and Receive
Data Valid being asserted, a clock phase change of up to 360
degrees may occur. Following the de-assertion of Receive
Data Valid a clock phase of 360 degrees may occur.
Receive Data RXD0
Receive Data 0 (RXD0) is the least significant bit of the
receive data nibble. RXD0 is sourced by the ICS1889. When
Receive Data Valid (RXDV) is asserted by the ICS1889, it
will transfer the first bit of the symbol synchronously with
Receive Clock (RXCLK).
When Receive Data Valid is asserted, the Receive Clock
frequency is 25% of the data rate, 25 MHz. The minimum low
and high times of the clock are guaranteed to be 35% under all
conditions and the duty cycle between 35% and 65% except
during the clock transition conditions specified above. The
ICS1889 synchronizes Receive Data Valid, Received Data
and Receive Error with Receive Clock (RXCLK).
19
ICS1889
Receive Error (RXER)
Management Data Clock (MDC)
The ICS1889 detects two types of receive errors, errors
occurring during the reception of valid frames and an error
condition known as false carrier detect. False carrier detect is
signaled so that repeater applications can prevent the
propagation of false carrier detection. RXER always
transitions synchronously with RXCLK.
The Management Data Clock (MDC) is used by the ICS1889
to synchronize the transfer of management information to or
from the ICS1889. The ICS1889 requires minimum high and
low times of 160 ns and a minimum clock period of 400 ns.
Management Data Input/Output
The Management Data Input/Output (MDIO) is a tristate line
driven by station management to transfer command
information or driven by the ICS1889 to transfer status
information. All transfers and sampling are synchronous with
MDC. If the ICS1889 is to be used in an application which
uses the mechanical MII specification, MDIO must have a
pull-up at the ICS1889 end and a pull-down at the station
management end. This enables station management to
determine if the connection is intact.
The assertion of Receive Error (RXER) for one or more clock
periods during the period when RXDV is asserted (receiving
a frame) indicates that the ICS1889 has detected a read
channel error. There are three sources of read channel error
loss of receive signal, failure of the PLL to lock and invalid
symbol detection (including the HALT symbol). Timing
diagram xxx (RXER Timing Diagram) shows the relationship
of RXER to RXCLK, RXEN and receive channel error
conditions.
Transmit and Receive Pin Descriptions
RXER may also be asserted when RXDV is de-asserted. The
ICS1889 will assert RXER and set RXD(3:0) to 1110 if a
false carrier is detected. For a good carrier to be detected, the
ICS1889 looks continuously at the incoming IDLE stream
(1111...) for two non-contiguous logic zeros and then checks
for the SSD of “JK.” In the event that two non-contiguous
logic zeroes are detected but the JK symbol pair is not, then a
false carrier condition is signaled and the IDLE condition is
reentered.
Transmit Pair (TX+ & TX-)
The Transmit pair TX+ and TX- carries the NRZI serial bit
stream for conversion to optical signals.
Receive Pair (RX+ & RX-)
The Receive pair RX+ and RX- carries the NRZI serial bit
stream from the optical converter.
Transmit Current Program (IPRG)
This pin is connected to a resistor and sets the current drive of
the transmitter.
Carrier Sense (CRS)
The ICS1889 asserts Carrier Sense (CRS) when it detects that
receive channel is non-idle in the full duplex mode or when it
detects that either the receive or transmit channels are nonidle in the half duplex mode. A receive channel non-idle
condition is detected by two non-contiguous zeros in any 10
bits (“IJ”). CRS is not synchronous to either the transmit or
receive clocks.
Frequency Reference (REF_IN and REF_OUT)
A 25 MHz crystal oscillator or reference source should be fed
into the REF_IN input, while leaving REF-OUT not
connected.
Signal Detect (SD+ & SD-)
This PECL input pair provides a signal detect indication from
the optical transceiver. The ICS1889 will indicate a receive
channel error if this signal is de-asserted. A receive channel
error is also indicated if either a PLL lock error or a receive
signal error is detected.
Collision Detected (COL)
The ICS1889 asserts Collision Detected (COL) when it
detects a receive carrier (non-idle) condition while
transmitting (TXEN asserted) in the half duplex mode. The
COL is not synchronous to either the transmit or receive
clocks. In full duplex mode, collision will be disabled.
20
ICS1889
Initialization & LED Pin Descriptions
A set of five pins is dual purpose. At power-up and reset they
define the MII PHY address of this ICS1889. Subsequent to
power-up and reset, they become LED status indicators. The
five pins are used to set the PHY address by connecting them
to Vss to indicate a logic one and ground to indicate a logic
zero. They must be connected to either Vss or ground using an
LED (see Figure xxx). At power-up or reset, the ICS1889 will
determine weather the pin is tied to ground or Vss and set the
appropriate value in the configuration register. It will then
determine the polarity of the signal required to drive the LED
and enter the status indicating mode. It will stay in this state
until a reset occurs.
The ICS1889 sets this bit to the appropriate value to turn on
the LED when a collision is detected. This signal is sticky and
will ensure that a single collision will be seen. If the collisions
are continuous, the LED will appear permanently on.
PHY Address 4 - Receive Data LED (P4RD)
Priority (PRIO)
PHY Address 0 - Full Duplex LED (P0FD)
At power-up and reset this pin is sampled for a logic high or
zero. If a logic one is detected, a value of 1 is set in the
configuration register.
The ICS1889 sets this bit to the appropriate value to turn on
the LED when the Full Duplex mode is selected.
At power-up and reset this pin is sampled for a logic high or
zero. If a logic one is detected, a value of 16 is set in the
configuration register.
When connected to ground, this pin enables the Duplex
Enable Pin (DPEN) to select the duplex mode. When this pin
is high, DPEN becomes an output indicating the duplex mode
selected.
The ICS1889 sets this bit to the appropriate value to turn on
the LED when receive data is detected. This signal is sticky
and will ensure that a single packet will be seen. If the packet
stream is continuous, the LED will appear permanently on.
Duplex Enable (DPEN)
If the Priority pin (PRIO) is high, Duplex Enable (DPEN) is
an output indicating the selected duplex mode. A logic one
indicates full duplex and a logic zero indicates half duplex. If
the Priority Pin is grounded, this pin becomes an input that
sets the duplex mode, a logic one setting the full duplex mode
and a logic zero setting the half duplex mode.
PHY Address 3 - Transmit Data LED (P3TD)
At power-up and reset this pin is sampled for a logic high or
zero. If a logic one is detected, a value of 8 is set in the
configuration register.
Link Status (LSTA)
The ICS1889 sets this bit to the appropriate value to turn on
the LED when transmit data is detected. This signal is sticky
and will ensure that a single packet will be seen. If the packet
stream is continuous, the LED will appear permanently on.
This signal indicates the status of the link monitor. A logic one
indicates that the link integrity is OK.
System Reset (SYSR)
When grounded for more than 80ns, this pin causes the
ICS1889 to enter a reset cycle. Upon completion of a reset, the
ICS1889 will be initialized to the same state as that following a
power-up cycle. If SYSR is held low, the ICS1889 remains in
the reset state.
PHY Address 2 - Link Integrity LED (P2LI)
At power-up and reset this pin is sampled for a logic high or
zero. If a logic one is detected, a value of 4 is set in the
configuration register.
Node/Repeater (NOD/REP)
The ICS1889 sets this bit to the appropriate value to turn on
the LED when the Link Integrity status is OK.
When this input is logic zero, the device will default to Node
operation. SQE test will default to on.
PHY Address 1 - Collision LED (P1CL)
When this input is logic one, the device will default to
Repeater operation. SQE test will default to off and Carrier
Sense will be determined by receive activity only.
At power-up and reset this pin is sampled for a logic high or
zero. If a logic one is detected, a value of 2 is set in the
configuration register.
The NOD/REP pin does not have a default configuration and
must be tied either to ground or supply.
21
ICS1889
Packaging
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Signal
VDD
NOD/REP
TX–
TX+
IPRG
VSS
VSS
RX+
RX–
SD+
SD–
N/C
N/C
VDD
LSTA
SYSR
PRIO
DPEN
N/C
N/C
N/C
VSS
MDIO
MDC
RXD3
RXD2
Pin Assignments
Meaning
VDD (LEDs)
Node or Repeater Mode Selection
Transmitted Data negative
Transmitted Data positive
Current program
VSS (Transmit Data)
VSS
Receive Data positive
Receive Data negative
Signal Detect
Signal Detect
No Connect
No Connect
VDD (Receive)
Link Status
System reset
Priority
Duplex Enable
No Connect
No Connect
No Connect
VSS (Receive)
Management Data Input/Output
Management Data Clock
Receive Data 3
Receive Data 2
Pin Diagram
22
PIN
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Signal
RXD1
RXD0
RXDV
RXCLK
RXER
VSS
VDD
TXER
TXCLK
TXEN
TXD0
TXD1
TXD2
TXD3
COL
CRS
VSS
REF_OUT
REF_IN
VDD
VSS
P0FD
P1CL
P2LI
P3TD
P4RD
Meaning
Receive Data 1
Receive Data 0
Receive Data Valid
Receive Clock
Receive Error
VSS (MII I/O)
VDD (MII I/O)
Transmit Error
Transmit Clock
Transmit Enable
Transmit Data 0
Transmit Data 1
Transmit Data 2
Transmit Data 3
Collision Detect
Carrier Sense
VSS (Transmit)
Frequency reference out
Frequency reference in
VDD (Transmit)
VSS (LEDs)
Full duplex LED
Collision detect LED
Link Integrity LED
Transmit data LED
Receive data LED
ICS1889
System Diagram
23
ICS1889
Absolute Maximum Ratings
VDD (measured to VSS) . . . . . . . . . . . . . . . . . 7.0 V
Digital Inputs /Outputs . . . . . . . . . . . . . . . . . VSS – 0.5 V to VDD + 0.5 V
Ambient Operating Temperature . . . . . . . . . – 55° C to +125° C
Storage Temperature . . . . . . . . . . . . . . . . . . . – 65° C to +150° C
Junction Temperature . . . . . . . . . . . . . . . . . . 175° C
Soldering Temperature . . . . . . . . . . . . . . . . . 265° C
Stresses above those listed under Absolute Maximum Ratings above may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those listed in the operational sections
of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
Recommended Operating Conditions
PARAMETER
Ambient Operating Temp.
Using a Positive Supply
SYMBOL TEST CONDITIONS
TA
VSS
VDD
24
MIN
0
0.0
+4.75
MAX
+70
0.0
+5.25
UNITS
ºC
V
V
ICS1889
DC Characteristics
VDD = VMIN to VMAX , VSS = 0V, TA = TMIN to TMAX
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
VDD = +5.0V, VSS = 0.0V
SYMBOL
VI H
VI L
VOH
VOL
CONDITIONS
MIN
—
MAX
80
UNITS
mA
ECL Input / Output
ECL
ECL
ECL
ECL
PARAMETER
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
MIN
VDD -1.16
VDD -1.81
VDD -1.02
—
MAX
VDD -0.88
VDD -1.47
—
VDD -1.62
UNITS
V
V
V
V
TTL Input / Output
PARAMETER
TTL Input High Voltage
TTL Input Low Voltage
TTL Output High Voltage
TTL Output Low Voltage
TTL Driving CMOS
Output High Voltage
TTL Driving CMOS
Output Low Voltage
TTL / CMOS Output
Sink Current
TTL / CMOS Output
Source Current
SYMBOL
VIH
VI L
VOH
VOL
0.0V
0.0V
0.0V
0.0V
MIN
2.0
—
2.4
—
MAX
—
0.8
—
0.4
UNITS
V
V
V
V
VOH
VDD = 5.0V, VSS = 0.0V
3.68
—
V
VOL
VDD = 5.0V, VSS = 0.0V
—
0.4
V
IOL
VDD = 5.0V, VSS = 0.0V
8
—
mA
IOH
VDD = 5.0V, VSS = 0.0V
—
-0.4
mA
CONDITIONS
VDD = 5.0V, VSS = 0.0V
VDD = 5.0V, VSS = 0.0V
MIN
3.5
—
MAX
—
1.5
UNITS
V
V
VDD
VDD
VDD
VDD
CONDITIONS
= 5.0V, VSS =
= 5.0V, VSS =
= 5.0V, VSS =
= 5.0V, VSS =
REF_IN Input
PARAMETER
Input High Voltage
Input Low Voltage
SYMBOL
VIH
VI L
Note: REF_IN Input switch point is 50% of VDD.
25
ICS1889
Additional DC Electrical Specifications
THE TIMING VALUES ARE PRELIMINARY AND SUBJECT TO CHANGE.
T#
t1
t2
t3
PARAMETER (conditions)
MII Input Pin Capacitance
MII Output Pin Capacitance
MII Input Pin Impedance
MIN
—
—
—
TYP
8
14
33
MAX
—
—
—
UNITS
pF
pF
Ohms
Clocks — Reference In (REF-IN/REF+) To Transmit Clock TXCLK
T#
t1
t2
t3
PARAMETER (conditions)
REF_IN Duty Cycle
REF_IN Period
REF_IN rise to TXCLK rise
MIN
40
—
0
Note: REF-IN switching point is 50% of VDD.
26
TYP
50
40
1.5
MAX
60
—
3
UNITS
%
ns
ns
ICS1889
Clocks — Transmit Clock Tolerance
T#
t1
t2
PARAMETER (conditions)
TXCLK Duty Cycle
TXCLK Period
MIN
35
—
TYP
50
40
MAX
65
—
UNITS
%
ns
Note: TXCLK Duty Cycle = REF_IN Duty Cycle ± 5%.
Clocks — Receive Clock Behavior
T#
t1
t2
t3
t4
PARAMETER (conditions)
RXCLK Duty Cycle
RTXCLK Period
RXDV De-asserted Recovered Clock to Nominal
Clock Cycle Extension (No Extension)
RXDV De-asserted Nominal Clock to Recovered
Clock Cycle Extension
27
MIN
45
—
TYP
50
40
MAX
55
—
UNITS
%
ns
—
—
—
—
—
—
60
ns
ICS1889
Clocks — Synchrous Transmit Timing
T#
t1
t2
PARAMETER (conditions)
TXD, TXEN, TXER Setup to TXCLK rise
TXD, TXEN, TXER hold after TXCLK rise
MIN
10
0
TYP
—
—
MAX
—
—
UNITS
ns
ns
MIN
13.0
12.5
TYP
—
—
MAX
—
—
UNITS
ns
ns
Clocks — Synchrous Receive Timing
T#
t1
t2
PARAMETER (conditions)
RXD, RXDV, RXER Setup to RXCLK rise
RXD, RXDV, RXER Hold after RXCLK rise
28
ICS1889
Clocks — Transmit Clock Tolerance
T#
t1
t2
t3
t4
t5
t6
t7
PARAMETER (conditions)
MDC Minimum High Time
MDC Minimum Low Time
MDC Period
MDC rise to MDIO valid
MDIO Setup to MDC
MDIO Hold after MDC
Maximum allowable frequency (50pF Loading)
29
MIN
160
160
400
0
15
0
—
TYP
—
—
—
—
—
—
—
MAX
—
—
—
300
—
—
20
UNITS
ns
ns
ns
ns
ns
ns
MHz
ICS1889
MII — Transmit Latency
T#
t1
PARAMETER (conditions)
TXEN sampled to MDI Output
(1st bit of /J/ MII IF)*
MIN
TYP
MAX
UNITS
—
8
9
bits
MAX
5
5
UNITS
bits
bits
*Note: The IEEE maximum is 18 bits.
MII — Carrier Assertion / De-assertion on Transmission
T#
t1
t2
PARAMETER (conditions)
TXEN sampled to CRS assert
TXEN sampled to CRS de-assert
MIN
0
0
30
TYP
4
4
ICS1889
MII — Receive Latency
T#
t1
PARAMETER (conditions)
1st bit of /J/ into TP_RX to /J/
on RXD (100M MII IF)
*Note: The IEEE maximum is 23 bits.
31
MIN
TYP
MAX
UNITS
—
—
16
bits
ICS1889
MDI Input to Carrier Assertion / De-asseration
T#
t1
t2
t3
t4
PARAMETER (conditions)
1st bit of /J/ into TP_RX to CRS assert*
1st bit of /J/ into TP_RX while transmitting
data to COL assert (Half Duplex Mode)*
1st bit of /T/ into TP_RX to CRS de-assert**
1st bit of /T/ into TP_RX to COL de-assert
(Half Duplex Mode)**
MIN
—
TYP
—
MAX
8
UNITS
bits
—
—
8
bits
—
—
14
bits
—
—
14
bits
*Note: The IEEE maximum is 20 bit times.
**Note: The IEEE minimum is 13 bit times and the maximum is 24 bit times.
32
ICS1889
Reset — Power On Reset
T#
t1
PARAMETER (conditions)
VDD to 4V to Reset Complete
MIN
—
TYP
20
MAX
—
UNITS
µs
MIN
—
80
—
TYP
—
—
—
MAX
200
—
640
UNITS
ns
ns
ns
Reset — Hardware Reset & Power-down
T#
t1
t2
t3
PARAMETER (conditions)
Reset active to device isolation & initialization
Minimum RESET poulse width
RESET released to device ready
33
ICS1889
Clock Recovery
T#
t1
t2
t3
t4
PARAMETER (conditions)
Ideal data recovery window
Actual data recovery window
Data recovery window truncation
SD assert to data acquired
MIN
—
6
0
—
34
TYP
—
—
—
—
MAX
8
8
1
100
UNITS
ns
ns
ns
ns
ICS1889
MQFP PACKAGE
Ordering Information
ICS1889
Example:
ICS XXXX Y
LEAD COUNT (N)
BODY THICKNESS
FOOTPRINT (BODY+)
DIMENSIONS
TOLERANCE
A
MAX.
A1
MAX.
A2
+0.10 / -0.05
D
±0.25
D1
±0.10
E
±0.25
E1
±0.10
L
+0.15 / -0.10
e
BASIC
b
±0.05
ccc
MAX.
—
∝
52L
2.00
3.20
2.45
0.25
2.0
17.20
14.00
17.20
14.00
0.88
1.00
0.35
0.10
0° - 7°C
Package Type
Y = MQFP
Device Type (consists of 3 or 4 digit numbers)
Prefix
ADVANCE INFORMATION documents contain information
ICS, AV = Standard Device
on new products in the sampling or preproduction phase of
development. Characteristic data and other specifications
are subject to change without notice.
35