H IR 3/16 Encode/Decode IC Technical Data HSDL-7000 Features Description • Compliant with IrDA Physical Layer Specs • Interfaces with IrDA Compliant HSDL-1000 IR Transceiver • 1 Micron CMOS Gate Array • Used in Conjunction with Standard 16550 UART • Pin Compatible with PLX-1000 The HSDL-7000 performs the modulation/demodulation function used to both encode and decode the electrical pulses from the IR transceiver. These pulses are then sent to a standard UART which has a BAUDOUT signal available externally. This signal is 16 times the selected baud rate. In applications where the 16XCLK is not available, an external means of generating the 16XCLK must be designed. Applications Interfaces with HSDL-1000 to perform: • Serial Half-Duplex Data Transfer Between: Notebook Computers Subnotebooks Desktops PCs PDAs Printers Other Peripheral Devices • Telecom Applications in: Modems Fax Machines Pagers Phones • Industrial Applications in: Data Collection Devices • Medical Applications in: Patient and Pharmaceutical Data Collection 5964-9278E The HSDL-7000 is comprised of two state machines – the serial IR encode and the serial IR decode blocks. Each of these blocks derives their timing from the 16XCLK input signal from the UART. The Encode block is driven by the negative edge triggered TXD signal from the UART. This initiates the modulation state machine resulting in the 3/16 modulated IR_TXD signal which drives the IR transceiver module, HSDL-1000. The IR Decode block is driven by the negative edge triggered IR_RCV signal from the HSDL-1000. After this signal is demodulated and stretched, it drives the RCV signal to the UART. Schematic HSDL-7000 TXD IR_TXD IR ENCODE RCV IR_RCV IR DECODE NRST Pin Out 16XCLK 1 TXD 2 RCV 3 GND 4 HP 7000 YYWW 8 VCC 7 IR_TXD 6 IR_RCV 5 NRST 4-43 Pin Description RCV - Output signal which is usually tied to a UART’s SIN signal (received serial data). 16XCLK - Positive edge triggered input clock that is set to 16 times the data transmission baud rate. The encode and decode schemes require this signal. The signal is usually tied to a UART’s BAUDOUT signal. IR_RCV - A 3/16th pulse width input signal from the HSDL-1000. The signal is a demodulated (pulse stretched) to generate the RCV output signal. GND - Chip ground. NRST - Active low signal used to reset the decode state machine. This signal can be tied to POR (Power on reset) or VCC. This signal can also be used to disable any data reception. TXD - Negative edge triggered input signal; usually tied to a UART’s SOUT signal (serial data to be transmitted). IR_TXD - This signal is the modulated 3/16ths TXD signal which is input to the HSDL-1000. VCC - Power. Package Dimensions 1.05 (0.041) 6.65 (0.26) MAX. 5 8 0.10 (0.004) SCALE 5 0.15 + 0.10/-0.00 (0.006 + 0.004/-0.00) 0.6 ± 0.2 (0.024 ± 0.008) DETAIL A, SCALE 20 1 4 1.42 (0.056) MAX. 5.60 (0.22) 1.55 (0.06) SEE DETAIL A 0.40 + 0.10/-0.00 (0.016 + 0.004/-0.000) 1.27 (0.05) NOTE: DIMENSIONS IN MILLIMETERS (INCHES). 4-44 7.7 ± 0.3 (0.30 ± 0.012) Encoding Scheme 16 CLOCK CYCLES 16 X CLOCK TXD 7 cs IRTXD 3 cs The encoder sends a pulse for every space or “0” that is sent on the TXD line. On a high to low transition of the TXD line, the generation of the pulse is delayed for 7 clock cycles of the 16XCLK before the pulse is set high for 3 clock cycles (or 3/16th of a bit time) and then subsequently pulled low. Decoding Scheme 16 CLOCK CYCLES 16 X CLOCK IR_RXD 3 cs RXD A high to low transition of the IR_RXD line from the HSDL-1000 signifies a 3/16th pulse. This pulse is stretched to accommodate 1 bit time (16 clock cycles). Every pulse that is received is translated into a “0” or space on the RXD line equal to 1 bit time. Note: The stretched pulse must be at least 3/4 of a bit time in duration to be correctly interpreted by a UART. 4-45 Absolute Maximum Ratings Parameter Storage Temperature Operating Temperature Output Current Power Dissipation Input/Output Voltage Power Supply Voltage Symbol TS TA IO PMAX VI /VO VCC Min. -65 -40 Max. +150 +85 10 0.22 VCC + 0.5 +6.5 -0.5 -0.5 Units °C °C mA W V V Conditions Switching Specifications (VCC = 5 Volts ± 10%, TA= -40 to +85°C) Parameter Toggle Frequency Propagation Delay Time Output Fall Time Output Rise Time Symbol ftog tpd Min. tf tr Typ. 120 0.5 1.0 2.0 1.42 1.54 Max. Units Mhz ns ns ns ns ns Conditions Internal Gate Input Buffer Output Buffer Output Buffer (CL = 15 pF) Output Buffer (CL = 15 pF) Note: ftog represents the maximum internal D-Type Flip Flop toggle rate Capacitance (VCC = 0 Volts, TA= -40 to +85°C) Parameter Input Capacitance Output Capacitance Output Fall Time 4-46 Symbol CIN COUT Min. Typ. 10 10 10 Max. 20 20 20 Units pF pF pF Conditions f = 1 MHz - Unmeasured Pins Returned to 0 Volts Recommended Operating Conditions (TA= -40 to +85°C) Parameter Supply Voltage Input Voltage Ambient Temperature High Level Input Voltage Low Level Input Voltage Positive Trigger Voltage Negative Trigger Voltage Hysteresis Voltage Power Dissipation Input Rise Time Input Fall Time Max Clk Frequency (16XCLK) Minimum Pulse Width (IR_TXD)* Symbol VCC VI TA VIH VIL VP VN VH PDISS tri tfa f16XCLK tmpx Min. 2.7 0.0 -40 0.7 VCC 0.0 1.61 0.55 0.50 Typ. 5.0 4.9 Max. 5.5 VCC +85 VCC 0.3 VCC 4.00 3.10 2.00 220 200 200 2 250 Units V V °C V V V V V mW ns ns MHz ns Conditions CMOS level CMOS level CMOS level CMOS level CMOS level CMOS level CMOS level CMOS level f16XCLK = 2 MHz f16XCLK = 2 MHz f16XCLK = 2 MHz f16XCLK = 2 MHz *IrDA Parameters. The Max Clk Frequency represents the maximum clock frequency to drive the HSDL-7000’s internal state machine. Under normal circumstances, this clock input should not exceed 16 * 115.2 Kbp/s or 1.8432 MHz. This product can operate at higher clock rates, but the above is the recommended rate. The Minimum Pulse Width represents the minimum pulse width of the encoded IR_TXD pulse (and the IR_RCV pulse). As per the IrDA specifications, the minimum pulse width of the IR_TXD and IR_RCV pulses should be 3 * (1/1.8432 MHz) or 1.63 µs. The minimum pulse width specified for the HSDL-7000 is 250 ns, which is within IrDA specification. Under normal circumstances, the pulse width should not be less than 1.63 µs. Application Circuits HSDL-7000 Connection to UART HSDL-1000 TXD RCV UART 16550 HSDL-7000 IR_TXD IR_RCV TXD SOUT RCV SIN 16XCLK BAUDOUT Note: At the time of this publication, Light Emitting Diodes (LEDs) that are contained in this product are regulated for eye safety in Europe by the Commission for European Electrotechnical Standardization (CENELEC) EN60825-1. Please refer to Application Briefs I-008, I-009, I-015 for more information. 4-47