MCP2122
Infrared Encoder/Decoder
Features
Package Types
• Pinout compatible with HSDL-7000
• Compliant with IrDA® Standard Physical Layer
Specification (version 1.3)
• UART to IrDA Standard Encoder/Decoder
- Interfaces with IrDA Standard Compliant
Transceiver
• Baud Rates:
- Up to IrDA Standard 115.2 Kbaud Operation
• Transmit/Receive Formats (Bit Width) Supported:
- 1.63 µs
• Low-power Mode (2 µA at 1.8V, +125°C)
PDIP, SOIC
8
7
6
5
MCP2122
1
2
3
4
16XCLK
TX
RX
VSS
VDD
TXIR
RXIR
RESET
Block Diagram
MCP2122
TX
CMOS Technology
• Low-voltage operation
• Extended temperature range
• Low power consumption
Encode
TXIR
Reset
Logic
RESET
Baud Rate
Generator
16XCLK
RX
Decode
RXIR
IrDA Family Selection
Baud Rate
Encoder
/
Decoder
Protocol
Layer
Handler
Clock
Source
Host UART
Baud Rate
Selection
MCP2120 2400 2400 312,500 (1) 312,500 (1)
Yes
No
XTAL
HW/SW
MCP2122 2400 2400 115,200 (1) 115,200 (1)
Yes
No
16XCLK
By 16XCLK
MCP2140 9600
Yes
IrCOMM
XTAL
None - Fixed
MCP2150 9600 9600 115,200 (2) 115,200 (2)
Yes
IrCOMM
XTAL
HW
Host UART easily interfaces to
a PC’s serial port (DTE)
MCP2155 9600 9600 115,200 (2) 115,200 (2)
Yes
IrCOMM
XTAL
HW
Host UART easily interfaces to
a modem’s serial port (DCE)
Device
Host
UART
IR
9600
(3)
(3)
(3)
Comment
Extended Temperature Range
(-40°C to +125°C)
Note 1: The host UART and the IR operate at the same baud rates.
2: The host UART and IR baud rates operate independent of each other.
3: Supports the 9-wire “cooked” service class of the IrCOMM Application Layer Protocol.
2004 Microchip Technology Inc.
Preliminary
DS21894B-page 1
MCP2122
NOTES:
DS21894B-page 2
Preliminary
2004 Microchip Technology Inc.
MCP2122
1.0
DEVICE OVERVIEW
TABLE 1-1:
The MCP2122 is a stand-alone IrDA standard encoder/
decoder device that is pinout-compatible with the
Agilent® HSDL-7000 encoder/decoder.
Features
The MCP2122 has two interfaces: the host UART
interface and the IR interface (see Figure 1-1). The host
UART interfaces to the UART of the Host Controller.
The Host Controller is the device in the embedded
system that transmits and receives the data. The IR
interface connects to an infrared (IR) optical transceiver
circuit that converts electrical pulses into IR light
(encode) and converts IR light into electrical pulses
(decode). This IR optical transceiver circuit could be
either a standard infrared optical transceiver (such as a
Vishay® TFDU 4100) or it could be implemented with
discrete components. For additional information, please
refer to AN243, “Fundamentals of the Infrared Physical
Layer” (DS00243).
MCP2122
Serial Communications:
UART, IR
Baud Rate Selection:
16XCLK
Low-power Mode:
Yes
Packages:
8-pin PDIP
8-pin SOIC
Infrared Technology Features:
• Universal standard for connecting portable
computing devices
• Effortless implementation
• Economical alternative to other connectivity
solutions
• Reliable, high-speed connection
• Safe to use in any environment; can even be used
during air travel
• Eliminates the hassle of cables
• Allows PCs and non-PCs to communicate with
each other
• Enhances mobility by allowing users to easily
connect
When the Host Controller transmits the UART format
data, the MCP2122 receives this UART data and
encodes (modulates) it bit by bit. This encoded data is
then output as electrical pulses to the IR transceiver.
The IR transceiver will then convert these electrical
pulses to IR light pulses.
The IR transceiver also receives IR light pulses (data),
which are outputted as electrical pulses. The MCP2122
decodes (demodulates) these electrical pulses, with
the data then being transmitted by the MCP2122
UART. This modulation/demodulation method is
performed in accordance with the IrDA standard.
1.1
Applications
Some applications where an IR interface (MCP2122)
could be used include:
•
•
•
•
•
•
Table 1-1 shows an overview of some of the device
features. Figure 1-1 shows a typical application block
diagram. Table 1-2 shows the pin definitions of the
MCP2122 during normal operation.
FIGURE 1-1:
MCP2122 FEATURES
OVERVIEW
Data-Logging/Data Exchange
System Setup
System Diagnostic Read Out
Manufacturing Configuration
Host Controller Firmware Updates
System Control
SYSTEM BLOCK DIAGRAM
Host Controller
RESET
2004 Microchip Technology Inc.
MCP2122
RX
SI
Clock
(I/O)
Protocol Handler
TX
SO
UART
PICmicro®
MCU
Host UART
Interface
16XCLK
Encode
Decode
IR
Optical
Interface Transceiver
TFDU 4100
TXIR
RXIR
TXD
RXD
Reset
Logic
Clock
Logic
Preliminary
DS21894B-page 3
MCP2122
TABLE 1-2:
Pin Name
PIN DESCRIPTION
Pin Number
PDIP
SOIC
Pin
Type
Buffer
Type
Description
16XCLK
1
1
I
ST
16x external clock source input
TX
2
2
I
ST
Asynchronous receive from Host Controller UART
RX
3
3
O
—
Asynchronous transmit to Host Controller UART
VSS
4
4
—
P
Ground reference for logic and I/O pins
RESET
5
5
I
ST
Resets the Device
H = Normal Operation
L = Device in Reset
RXIR
6
6
I
ST
Asynchronous receive from infrared transceiver
TXIR
7
7
O
—
Asynchronous transmit to infrared transceiver
8
—
P
Positive supply for logic and I/O pins
VDD
Legend:
8
ST
I
P
O
=
=
=
=
DS21894B-page 4
Schmitt Trigger input with CMOS levels
Input
Power
Output
Preliminary
2004 Microchip Technology Inc.
MCP2122
2.0
DEVICE OPERATION
TABLE 2-1:
DEFAULT OUTPUT PIN
STATES IN DEVICE RESET
The MCP2122 is a low-cost infrared encoder/decoder.
The baud rate is the same for the host UART and IR
interfaces and is determined by the frequency of the
16XCLK signal, with a maximum baud rate of
115.2 Kbaud.
Name
State
RX
TXIR
The MCP2122 is made up of these functional modules:
RESET
L
H
L
• Clock Driver (16XCLK)
• Reset
• IR Encoder/Decoder
- IrDA Standard Encoder
- IrDA Standard Decoder
Output Pin
State
Input Pin
TABLE 2-2:
The 16XCLK circuit allows a clock input to provide the
device clock.
Comments
Device in Reset mode
DEFAULT OUTPUT PIN
STATES AFTER DEVICE
RESET (RESET = L→H)
Output Pin
State
Input Pin
Comments
The Reset circuit supports an external reset signal.
Name State
RX
TXIR
The IR Encoder logic takes a data bit and converts it to
the IrDA standard signal according to the IrDA standard
Physical Layer specification, while the IR Decoder
logic takes the IrDA standard signal and converts it to
8-bit data bytes.
TX
L
—
L→H After 7 - 8 16XCLK
→L pulses, the TXIR pin
will pulse high.
H
—
L
L
H→L
—
H
H
—
RXIR
2.1
Power-up
As the device is powered up, there will be a voltage
range in which the device will not operate properly. The
device should be reset once it has entered the normal
operating range (from an out-of-voltage condition). The
RESET pin may then be forced high.
Other device operating parameters (such as frequency,
temperature, etc.) must also be within their operating
ranges when the device exits reset. Otherwise, the
device may not function as desired.
2.2
Device Reset
The MCP2122 is forced into the known state (RESET)
when the RESET pin is in the low state. Once the
RESET pin is brought to a high state, the device begins
normal operation (if the device operating parameters
are met). Table 2-1 shows the states of the output pins
while the device is in reset (RESET = Low). Table 2-2
shows the state of the output pins once the device exits
reset, RESET = L→H (device in Normal Operation
mode).
2.3
After 4 16XCLK pulses,
RX = L.
Decoupling
It is highly recommended that the MCP2122 have a
decoupling capacitor (CBYP). A 0.01 µF capacitor is
recommended as a starting value, but an evaluation of
the best value for your circuit/layout should be
performed. Place this decoupling capacitor (CBYP) as
close to the MCP2122 as possible (see Figure 2-1).
FIGURE 2-1:
The MCP2122 has a RESET noise filter in the RESET
input signal path. The filter will detect and ignore small
pulses.
DEVICE DECOUPLING
VDD
MCP2122
VDD
CBYP
(bypass
capacitor)
VSS
TXIR
RXIR
RESET
16XCLK
TX
RX
Using the RESET pin to enter a low-power state is
discussed in Section 2.9 “Minimizing Power”.
2004 Microchip Technology Inc.
Preliminary
DS21894B-page 5
MCP2122
2.3.1
FIGURE 2-4:
BROWN-OUTS
Some applications may subject the MCP2122 to a
brown-out condition. Good design practice requires
that when a system is in brown-out, the system should
be in reset to ensure that the system is in a known
state when the system exits the brown-out. This
brown-out circuitry is external to the MCP2122.
2.3.1.1
External Brown-Out Reset Circuits
EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 2
VDD
VDD
R1
Q1
R2
40 kΩ
Figure 2-2 shows a circuit for external brown-out
protection using the TCM809 device.
Figure 2-3 and Figure 2-4 illustrate two examples of
external circuitry that may be implemented. Each
option needs to be evaluated to determine if they
satisfy the requirements of the application.
FIGURE 2-2:
EXTERNAL BROWN-OUT
PROTECTION USING THE
TCM809
VDD
RESET
MCP2122
Note 1: This circuit is less expensive, but
less accurate. Transistor Q1 turns
off when VDD is below a certain level
such that:
VDD •
R1
R1 + R2
= 0.7V
2: Resistors should be adjusted for the
characteristics of the transistor.
VDD
TCM809
RESET
RST
MCP2122
VSS
FIGURE 2-3:
EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 1
VDD
VDD
33 kΩ
10 kΩ
40 kΩ
Q1
RESET
MCP2122
Note 1: Resistors should be adjusted for the
characteristics of the transistor.
2: This circuit will activate reset when
VDD goes below (Vz + 0.7V),
where Vz = Zener voltage.
DS21894B-page 6
Preliminary
2004 Microchip Technology Inc.
MCP2122
2.4
16XCLK (Bit Clock)
The MCP2122 requires an external clock source to
operate. The 16XCLK pin is the device clock input (see
Figure 2-5) and is independent of the host UART
interface or the IR interface. The 16XCLK determines
all timing during device operation. It is the edge of the
16XCLK pin that causes activity to occur.
The 16XCLK signal can also be referred to as a bit
clock (BITCLK). There are 16 BITCLKs for each bit
time. The BITCLKs are used for the generation of the
Start bit, the eight data bits and the Stop bit.
When the embedded system does not want to receive
IR communications, the 16XCLK clock can be disabled
(static). This will reduce the power consumption of the
system.
Figure 2-6 shows the relationship of the 16XCLK signal
to the RXIR input, which then determines the RX output
signal. Figure 2-7 shows the relationship of the
16XCLK signal to the TX input, which then determines
the TXIR output signal. For device timing information,
refer to Section 4.0 “Electrical Characteristics”.
FIGURE 2-5:
When the embedded system could be receiving IR
communication, the MCP2122 is required to have the
16XCLK signal clocking at the expected frequency,
with minimal variation in that frequency. Between data
bytes (Stop bit to Start bit), the 16XCLK frequency can
be changed. This may occur in systems where the Host
Controller is implementing one of the IrDA standard
application layer protocols (such as IrObex).
FIGURE 2-6:
DEVICE CLOCK SOURCE
MCP2122
16XCLK
16XCLK AND RX/RXIR
16 16XCLK
16 16XCLK
16XCLK
(input)
≤ 3 CLK
RXIR
(input)
16 16XCLK
RX
(output)
FIGURE 2-7:
Bit A
Bit B
16XCLK AND TX/TXIR
16 16XCLK
16 16XCLK
16XCLK
(input)
TX
(input)
16 16XCLK
TXIR
(output)
3 CLK (≤ ~ 4 µs)
Bit A
2004 Microchip Technology Inc.
Bit B
Preliminary
DS21894B-page 7
MCP2122
2.4.1
2.5
BAUD RATE
The baud rate for the MCP2122 is determined by the
frequency of the 16XCLK signal. Equation 2-1
demonstrates how to calculate the 16XCLK frequency
based on the desired baud rate. Table 2-3 shows some
common baud rates and the corresponding 16XCLK
frequency.
EQUATION 2-1:
The IR encoder/decoder is made up of two major
components. They are:
• IR Decoder
• IR Encoder
The encoder receives UART data (bit by bit) and
outputs a data bit in the IrDA standard bit format.
Figure 2-8 shows a functional block diagram of the
encoder.
16XCLK FREQUENCY
F 16XCLK = 16 • (Desired Baud Rate)
TABLE 2-3:
Baud
Rate
The decoder receives IrDA standard data (bit by bit)
and outputs data in UART data bit format. Figure 2-8
shows a functional block diagram of the decoder.
The encoder/decoder has two interfaces. They are:
COMMON BAUD RATE/
16XCLK FREQUENCY
16XCLK
Frequency
(F16XCLK)
9600
153,600
19,200
307,200
38,400
614,400
57,600
921,600
115,200
1,843,200
Encoder/Decoder
• Host UART interface
• IR interface
Comment
2.5.1
ENCODING (MODULATION)
Each bit time is comprised of 16 bit clocks. If the value
to be transmitted (as determined by the TX pin) is a
logic-low, the TXIR pin will output a low level for 7-bit
clock cycles, a logic-high level for 3-bit clock (with a
maximum high-time of about 4 µs) cycles, with the
remaining time (6-bit clock cycles or more) being low. If
the value to transmit is a logic-high, the TXIR pin will
output a low level for the entire 16 bit clock cycle.
2.5.2
DECODING (DEMODULATION)
Each bit time is comprised of 16 bit clocks. If the value
to be received is a logic-low, the RXIR pin will be a low
level for the first 3-bit clock cycle (or a minimum of
1.6 µs), with the remaining time (13-bit clock cycles)
being high. If the value to be received is a logic-high,
the RXIR pin will be a high level for the entire 16-bit
clock cycle. The level on the RX pin will be in the
appropriate state for an entire 16-bit clock cycle.
FIGURE 2-8:
MCP2122 RECEIVE DETECT TO ENCODER/DECODER BLOCK DIAGRAM
RX
Glitch
Filter
Decode
RXIR
TX
Encode
Pulse Width
Limiter
(~ 4 µs)
TXIR
The following table shows the state on the RESET pin and how this effects the operation of the TXIR pin.
RESET State
VIH
VIL
DS21894B-page 8
Comment
TXIR output encoded value of TX pin
TXIR is forced low
Preliminary
2004 Microchip Technology Inc.
MCP2122
2.5.3
ENCODING AND SCREEN
CAPTURES
TABLE 2-4:
Table 2-4 shows the TXIR pin high-time at different
common baud rates. The internal TXIR pulse-width
high-time limiter is a feature that minimizes the system
current consumption at lower baud rates. The IrDA
standard specification requires that optical receiver circuitry detect pulses as narrow as 1.41 µs (1.63 µs is
the typical time at 115200 baud). Therefore, the time
that the TXIR pin is high after this valid detection is
additional current that is driven by the emitter LED. The
MCP2122 will force the TXIR pin low once the pulsewidth limiter has timed out. Figure 2-9 shows the
MCP2122 16XCLK, TX and TXIR waveforms at
115200 baud for a single TX low bit. In this case, the
TXIR is high for three 16XCLK pulses. In Figure 2-10,
the MCP2122 is at 9600 baud for a single TX low bit. In
this case, the TXIR is high for 3.55 µs (determined by
pulse-width limiter circuit).
FIGURE 2-9:
TXIR HIGH PULSE WIDTH
TXIR Pulse Width
Baud
Rate
3xT16XCLK
Circuit
Pulse-width
Limiter (2)
Circuit
Actual Pulse
Width
9600
19.53 µs (1)
4.00 µs
4.00 µs (3)
19200
9.77 µs (1)
4.00 µs
4.00 µs (3)
38400
4.88 µs (1)
4.00 µs
4.00 µs (3)
57600
3.26 µs
4.00 µs
3.26 µs
115200
1.63 µs
4.00 µs
1.63 µs
Note 1: The pulse-width limiter on the TXIR pin
saves system current for this baud rate.
2: This TXIR pulse width time is a design
target and is not tested. Actual times may
be greater than, or less than, this value.
3: This time (determined by the pulse-width
limiter circuit) is device dependent.
MCP2122 AT 115200 BAUD WAVEFORM
TXIR
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
16XCLK Pulse
A B Jitter of the TX input relative to the 16XCLK and TXIR
2004 Microchip Technology Inc.
Preliminary
DS21894B-page 9
MCP2122
FIGURE 2-10:
MCP2122 AT 9600 BAUD WAVEFORM
TXIR
1 2
3 4 5
6
7
8 9 10 11 12 13 14 15 16
16XCLK Pulse
A B Jitter of the TX input relative to the 16XCLK and TXIR
DS21894B-page 10
Preliminary
2004 Microchip Technology Inc.
MCP2122
2.6
Host UART Interface
2.7
The UART interface is used to communicate with the
Host Controller. Though a UART is capable of a fullduplex interface, the direct coupling to the IR encoder/
decoder allows only half-duplex operation (since the IR
side is either receiving or transmitting and not both at
the same time). This means that the system can’t
transmit and receive at the same time.
2.6.1
There will be some jitter on the detection of the high-tolow edge of the start bit. This jitter will affect the placement of the encoded start bit. All subsequent bits will be
16 BITCLK times later.
While RXIR is receiving data (low pulse), the TXIR pin
is disabled from transmitting.
RECEIVING
When the controller receives serial data from the
MCP2122, the baud rates are required to match.
There will be some jitter on the detection of the high-tolow edge of the Start bit. This jitter will affect the
placement of the decoded Start bit. All subsequent bits
will be 16 BITCLK times later.
The TXIR pin is disabled when data is being received
(low pulse) on the RXIR pin.
FIGURE 2-11:
The IR interface is used to communicate with the
optical receiver circuitry. The IR interface is either
transmitting data or receiving data (half-duplex).
2.8
Encoding/Decoding Jitter and
Offset
Figure 2-11 shows the jitter on the RXIR and TX pins,
along with the offset on the RX pin and the TXIR pin.
TRANSMITTING
When the controller sends serial data to the MCP2122,
the baud rates are required to match.
2.6.2
IR Interface
Jitter is the possible variation of the desired edge.
Figure 2-9 and Figure 2-10 show the jitter of the TX pin
(range is indicated by red dashed lines).
Offset is the propagation delay of the input signal (RXIR
or TX) to the output signal (RX or TXIR). Figure 2-9 and
Figure 2-10 show the offset of the TXIR pin from the
16XCLK signal that starts the bit time.
2.9
Minimizing Power
The device can be placed in a low-power mode by
forcing the RESET pin low. This disables the internal
state machine. To ensure that the lowest power
consumption is obtained, ensure that the 16XCLK pin
is not active and that the other input pins (TX and RXIR)
are at a logic-high or logic-low level.
2.9.1
RETURNING TO OPERATION
When returning to normal operation, the RESET pin
must be forced high and the 16XCLK signal should be
operating. Time should be given to ensure that the
16XCLK is stabilized at the desired frequency before
data is allowed to be transmitted or received.
EFFECTS OF JITTER AND OFFSET
16 16XCLK
16 16XCLK
BITCLK
3 16XCLK
RXIR
16 16XCLK
RX Jitter
RX Offset
RX
TX Jitter
TX
TX Offset
3 16XCLK
16 16XCLK
TXIR
2004 Microchip Technology Inc.
Preliminary
DS21894B-page 11
MCP2122
3.0
DEVELOPMENT TOOLS
There are currently no development tools for the
MCP2122. A demo board is scheduled to be available
soon.
DS21894B-page 12
Preliminary
2004 Microchip Technology Inc.
MCP2122
4.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
Ambient Temperature under bias ........................................................................................................... –40°C to +125°C
Storage Temperature ............................................................................................................................. –65°C to +150°C
Voltage on VDD with respect to VSS .......................................................................................................... –0.3V to +6.5V
Voltage on RESET with respect to VSS ..................................................................................................... –0.3V to +14V
Voltage on all other pins with respect to VSS ................................................................................. –0.3V to (VDD + 0.3V)
Total Power Dissipation (1) ...................................................................................................................................800 mW
Max. Current out of VSS pin ..................................................................................................................................500 mA
Max. Current into VDD pin .....................................................................................................................................500 mA
Input Clamp Current, IIK (VI < 0 or VI > VDD) ................................................................................................................... ±20 mA
Output Clamp Current, IOK (V0 < 0 or V0 > VDD)............................................................................................................. ±20 mA
Max. Output Current sunk by any Output pin..........................................................................................................25 mA
Max. Output Current sourced by any Output pin.....................................................................................................25 mA
Note 1: Power Dissipation is calculated as follows:
PDIS = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)
†NOTICE:
Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
2004 Microchip Technology Inc.
Preliminary
DS21894B-page 13
MCP2122
FIGURE 4-1:
VOLTAGE-FREQUENCY (16XCLK) GRAPH, -40°C ≤ TA ≤ +125°C
6.0
5.5
5.0
VDD
(Volts)
4.5
4.0
3.5
3.0
2.5
2.0
1.8
0
1.8432
4
Frequency (MHz)
DS21894B-page 14
Preliminary
2004 Microchip Technology Inc.
MCP2122
4.1
DC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature: –40°C ≤ TA ≤ +125°C (Extended)
DC Characteristics
Param.
No.
Sym
D001
VDD
D010
IDD
Characteristic
Supply Voltage
Supply Current
(2)
Min
Typ (1)
Max
Units
1.8
—
5.5
V
—
0.1
1
mA
Conditions
See Figure 4-1
FOSC = 1.8432 MHz, VDD = 5.5V
(TX = H, RXIR = H)
Transmitter (TX = L, RXIR = H)
—
—
300
µA
FOSC = 1.8432 MHz, VDD = 1.8V (4)
—
—
1
mA
FOSC = 1.8432 MHz, VDD = 5.5V
Receiver (RXIR = L, TX = H)
D020
IPD
Device Disabled
Current (3)
—
—
500
µA
FOSC = 1.8432 MHz, VDD = 1.8V (4)
—
—
2
mA
FOSC = 1.8432 MHz, VDD = 5.5V
—
—
2
µA
VDD = 1.8V (4)
—
—
4
µA
VDD = 5.5V
Note 1: Data in the Typical (“Typ”) column is based on characterization results at +25°C. This data is for design
guidance only and is not tested.
2: The supply current is mainly a function of the operating voltage and frequency. Pin loading, pin rate and
temperature have an impact on the current consumption.
a)The test conditions for all IDD measurements are:
16XCLK = external square wave, from rail-to-rail; TX = VSS, RXIR = VSS, RESET = VDD.
3: The device disable current is mainly a function of the operating voltage. Temperature also has an impact
on the current consumption. When the device is disabled (RESET = VSS). The test conditions for all IDD
measurements are:
16XCLK = external square wave, from rail-to-rail; TX = VSS, RXIR = VDD, RESET = VSS; The output pins
are driving a high or low level into infinite impedance.
4: These parameters (shaded) are characterized but are not tested. These values should be used for design
guidance only.
2004 Microchip Technology Inc.
Preliminary
DS21894B-page 15
MCP2122
DC Characteristics (Continued)
DC CHARACTERISTICS
Param
No.
Sym
VIL
Characteristic
Standard Operating Conditions (unless otherwise specified)
Operating temperature
–40°C ≤ TA ≤ +125°C (extended)
Operating voltage VDD range as described in DC spec, Section 4.1 “DC
Characteristics”.
Min
Typ (1)
Max
Units
Conditions
Input Low-Voltage
Input pins
D031
TX, RXIR
Vss
—
0.2 VDD
V
D032
RESET
Vss
—
0.2 VDD
V
16XCLK
Vss
—
0.2 VDD
V
D033
VIH
Input High-Voltage
Input pins
—
D041
TX, RXIR
0.8 VDD
—
VDD
V
D042
RESET
0.8 VDD
—
VDD
V
D043
16XCLK
0.8 VDD
—
VDD
V
TX and 16XCLK
—
—
±1
µA
VSS ≤ VPIN ≤ VDD,
Pin at high-impedance
RESET
—
—
±1
µA
VSS ≤ VPIN ≤ VDD
RXIR
—
—
±1
µA
VDD = 5.5V, VRXIR = VDD
IIL
D060A
D061
D060B
IIH
Input Leakage
Current (2, 3)
Note 1: Data in the Typical (“Typ”) column is based on characterization results at +25°C. This data is for design
guidance only and is not tested.
2: The leakage current on the RESET pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as coming out of the pin.
DS21894B-page 16
Preliminary
2004 Microchip Technology Inc.
MCP2122
DC Characteristics (Continued)
Standard Operating Conditions (unless otherwise specified)
Operating temperature: –40°C ≤ TA ≤ +125°C (Extended)
Operating voltage VDD range as described in DC spec, Section 4.1
“DC Characteristics”.
DC CHARACTERISTICS
Param
No.
Min
Typ (1)
Max
Units
RX
—
—
0.6
V
IOL = 2 mA, VDD = 1.8V
TXIR
—
—
0.6
V
IOL = 2 mA, VDD = 1.8V
RX (2)
VDD – 0.7
—
—
V
IOH = -0.8 mA, VDD = 1.8V
TXIR (2)
VDD – 0.7
—
—
V
IOH = -0.8 mA, VDD = 1.8V
All Output pins
—
—
50
pF
All Input pins
—
7
—
pF
Sym
VOL
D080B
D081
VOH
D090B
D091
Characteristic
Conditions
Output Low-Voltage
Output High-Voltage
Capacitive Loading Specs
on Output Pins
D101A
COUT
D101B
CIN
TA = +25°C, FC = 1.0 MHz
Note 1: Data in the Typical (“Typ”) column is based on characterization results at +25°C. This data is for design
guidance only and is not tested.
2: Negative current is defined as coming out of the pin.
2004 Microchip Technology Inc.
Preliminary
DS21894B-page 17
MCP2122
4.2
Timing Parameter Symbology and Load Conditions
The timing parameter symbols have been created following one of the following formats:
4.2.1
TIMING CONDITIONS
The temperature and voltages specified in Table 4-2 apply to all timing specifications, unless otherwise noted.
Figure 4-2 specifies the load conditions for the timing specifications.
TABLE 4-1:
SYMBOLOGY
1. TppS2ppS
T
F
Frequency
E
Error
Lowercase letters (pp) and their meanings:
pp
io
Input or Output pin
rx
Receive
bitclk
RX/TX BITCLK
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (Hi-impedance)
L
Low
TABLE 4-2:
T
Time
xclk
tx
RST
Oscillator
Transmit
Reset
P
R
V
Z
Period
Rise
Valid
High-impedance
AC TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
Operating temperature: –40°C ≤ TA ≤ +125°C (Extended)
Operating voltage VDD range as described in DC spec,
Section 4.1 “DC Characteristics”.
AC CHARACTERISTICS
FIGURE 4-2:
2. TppS
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
CL
PIN
CL = 50 pF for all output pins
7 pF (typical) for all input pins
VSS
DS21894B-page 18
Preliminary
2004 Microchip Technology Inc.
MCP2122
4.3
Timing Diagrams and Specifications
FIGURE 4-3:
EXTERNAL CLOCK TIMING
Q4
Q1
Q3
Q2
Q4
Q1
16XCLK
1
TABLE 4-3:
Sym
1
TXCLK
3
4
Standard Operating Conditions (unless otherwise specified)
Operating Temperature: –40°C ≤ TA ≤ +125°C (Extended)
Operating Voltage VDD range is described in
Section 4.1 “DC Characteristics”
Characteristic
External 16XCLK Period
(2, 3)
Min
Typ(1)
Max
Units
542.5
—
—
ns
External 16XCLK
DC
—
1.8432
Frequency (2, 3)
—
—
±2
1C
EXCLK Clock Error (4, 5)
50
—
—
3
TXCLKL, Clock in (16XCLK)
TXCLKH Low or High Time
—
—
7.5
4
TXCLKR, Clock in (16XCLK)
TXCLKF Rise or Fall Time (5)
Note 1: Data in the Typical (“Typ”) column is at 5V, +25°C, unless otherwise
design guidance only and are not tested.
1A
4
EXTERNAL CLOCK TIMING REQUIREMENTS
AC Characteristics
Param.
No.
3
FXCLK
Conditions
MHz
%
ns
Note 5
ns
Note 5
stated. These parameters are for
2: All specified values are based on characterization data for that particular oscillator type under standard
operating conditions with the device executing code. Exceeding these specified limits may result in an
unstable oscillator operation and/or higher than expected current consumption.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
3: A duty cycle of no more than 60/40 (High-Time/Low-Time or Low-Time/High-Time) is recommended for
external clock inputs.
4: This is the clock error from the desired clock frequency. The total system clock error includes the error from
the transmitter and the error of receiver (from the desired clock frequency). If the transmitter is 2% fast from
the target frequency, and the receiver is 2% slow from the target frequency, the total error is 4%.
5: These parameters (shaded) are characterized but are not tested. These values should be used for design
guidance only.
2004 Microchip Technology Inc.
Preliminary
DS21894B-page 19
MCP2122
FIGURE 4-4:
I/O WAVEFORM
16XCLK
RX or
TXIR Pin
New Value
Old Value
20, 21
Note: Refer to Figure 4-2 for load conditions.
TABLE 4-4:
I/O TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise specified)
Operating Temperature: –40°C ≤ TA ≤ +125°C (Extended)
Operating Voltage VDD range is described in
Section 4.1 “DC Characteristics”
AC Characteristics
Param.
No.
Sym
Characteristic
20A
ToR
RX pin rise time (2, 3)
20B
20C
TXIR pin rise time
(2, 3)
20D
21A
ToF
21C
RX pin fall time
(2, 3)
TXIR pin fall time
(2, 3)
Min
Typ (1)
Max
Units
—
10
25
ns
VDD ≥ 2.7V (Note 3)
—
10
60
ns
VDD = 1.8V (Note 3)
—
10
25
ns
VDD ≥ 2.7V (Note 3)
—
10
60
ns
VDD = 1.8V (Note 3)
—
10
35
ns
Note 3
—
10
25
ns
Note 3
Conditions
Note 1: Data in the Typical (“Typ”) column is at 5V, +25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
2: See Figure 4-2 for loading conditions.
3: These parameters (shaded) are characterized but are not tested. These values should be used for design
guidance only.
DS21894B-page 20
Preliminary
2004 Microchip Technology Inc.
MCP2122
FIGURE 4-5:
RESET AND DEVICE RESET TIMER TIMING
VDD
RESET
30
Internal
RESET
34A
34A
34B
34B
TXIR Pin
RX Pin
TABLE 4-5:
RESET AND DEVICE RESET TIMER REQUIREMENTS
Standard Operating Conditions (unless otherwise specified)
Operating Temperature: –40°C ≤ TA ≤ +125°C (Extended)
Operating Voltage VDD range is described in
Section 4.1 “DC Characteristics”.
AC Characteristics
Param.
No.
Sym
Characteristic
RESET Pulse Width (low)
Min
Typ (1)
Max
Units
30
TRSTL
2000
—
—
ns
34A
ToD
Default output state of TXIR
pin from RESET Low
—
—
2
µs
34B
ToD
Default output state of RX
pins from RESET Low
—
—
2
µs
Conditions
VDD = 5.0 V
Note 1: Data in the Typical (“Typ”) column is at 5V, +25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
2004 Microchip Technology Inc.
Preliminary
DS21894B-page 21
MCP2122
FIGURE 4-6:
TX AND TXIR WAVEFORMS
Bit
Bit
Bit
Bit
Bit ...
IR100
16XCLK
TX
IR114
IR113
IR113
IR122
IR122
IR122
IR122
IR122
IR122
IR120
IR115
TXIR
IR121
0
TABLE 4-6:
1
0
0
1
0
TX AND TXIR REQUIREMENTS
Standard Operating Conditions (unless otherwise specified)
Operating Temperature: –40°C ≤ TA ≤ +125°C (Extended)
Operating Voltage VDD range is described in
Section 4.1 “DC Characteristics”.
AC Characteristics
Param.
No.
Sym
IR100A
IR100B
IR102A
IR102B
IR113
TTXBIT
TTXIRBIT
ETXBIT
ETXIRBIT
TTXRF
Characteristic
Min
Typ (1)
Max
Transmit Baud Rate
—
16
—
Transmit Baud Rate
16
—
16
Host UART TX Error
—
—
±2
TXIR Error from 16XCLK
—
0
—
TX pin rise time and fall
—
—
25
time
—
—
1
IR114
TTXPDIRJ 16XCLK to TX jitter
7
—
8
IR120 TTXL2TXIRH TX falling edge (↓) to
TXIR rising edge (↑) (1)
IR121A TTXIRPW TXIR pulse width
3
—
3
1.41
3.5
5
IR121B
IR122
TTXIRP
TXIR bit period (1)
—
16
—
IR123
TTXIRRF TXIR pin rise time and fall
—
—
10
time
Note 1: Data in the Typical (“Typ”) column is at 5V, +25°C, unless otherwise
design guidance only and are not tested.
Units
Conditions
TXCLK
TXCLK
%
Note 2, 3
%
Note 2, 4
ns
Note 2
TXCLK Note 2
TXCLK
TXCLK At 115200 baud
µs
At 9600 baud (Note 5)
TXCLK
ns
50 pF load (Note 2)
stated. These parameters are for
2: These parameters (shaded) are characterized but are not tested. These values should be used for design
guidance only.
3: The TX pin operation may be asynchronous to the 16XCLK pin. This is the error from the desired baud rate
for the system.
4: The TXIR pin operation is synchronous to the 16XCLK pin. Any error present on the 16XCLK pin
(Parameter 1C) will be refelected on the TXIR pin.
5: This specification is not tested. This value is from the design target.
DS21894B-page 22
Preliminary
2004 Microchip Technology Inc.
MCP2122
FIGURE 4-7:
16XCLK AND THE TX AND TXIR WAVEFORMS
16 CLK
16 CLK
Data bit x
Data bit x+1
16XCLK
IR114
Bit Value
to TX
0
1
IR113
IR113
IR122
IR115
6 CLK
TXIRI (3 * 16XCLK pulses)
IR121A
TXIR Time Out
IR121B
TXIR pin
IR121C
IR124
IR123
TABLE 4-7:
TX AND TXIR REQUIREMENTS
Standard Operating Conditions (unless otherwise specified)
Operating Temperature: –40°C ≤ TA ≤ +125°C (Extended)
Operating Voltage VDD range is described in
Section 4.1 “DC Characteristics”.
AC Characteristics
Param.
No.
Symbol
Characteristic
Min
Typ (1)
IR113
TTXRF TX pin rise time and fall time
—
TX to 16XCLK jitter
—
IR114
TTXJ
IR120 TTXL2TXIRH TX falling edge (↓) to
7
TXIR rising edge (↑) (1)
TTXIRPW TXIR pulse width
Smaller of
IR121A
3
1.41
IR121B
IR122
TTXIRP TXIR bit period
—
20C
TTXIRR TXIR pin rise time
—
—
20D
21C
TTXIRF TXIR pin fall time
—
Note 1: Data in the Typical (“Typ”) column is at 5V, +25°C,
design guidance only and are not tested.
—
—
—
Max
25
1
8
Units Conditions
ns
Note 2
TXCLK Note 2
TXCLK
Smaller of
—
3
TXCLK At 115200 baud
3.5
5
µs
At 9600 baud (Note 3)
16
—
TXCLK
10
25
ns
VDD ≥ 2.7V (Note 2)
10
60
ns
VDD = 1.8V (Note 2)
10
25
ns
Note 2
unless otherwise stated. These parameters are for
2: These parameters (shaded) are characterized but are not tested. These values should be used for design
guidance only.
3: This specification is not tested. This value is from the design target
2004 Microchip Technology Inc.
Preliminary
DS21894B-page 23
MCP2122
FIGURE 4-8:
RXIR AND RX WAVEFORMS
Bit
Bit
Bit
IR132
IR132
Bit
Bit ...
IR110
16XCLK
IR133
IR132
IR132
IR132
IR132
RXIR
IR131A
IR134
IR130
IR132
IR132
IR132
IR132
IR132
IR132
0
0
1
0
RX
IR103
0
IR103
1
Note: Refer to Figure 4-2 for load conditions.
TABLE 4-8:
RXIR REQUIREMENTS
Standard Operating Conditions (unless otherwise specified)
Operating Temperature: –40°C ≤ TA ≤ +125°C (Extended)
Operating Voltage VDD range is described in
Section 4.1 “DC Characteristics”.
AC Characteristics
Param.
No.
Sym
IR101A ERXIRBIT
IR101B ERXBIT
IR103 TTXRF
Characteristic
Min
Typ (1)
RXIR Error
—
Host UART RX Error
—
RX pin rise time and fall
—
time
Receive (RX pin) Bit Rate
16
IR110 TRXBIT
—
IR130 TRXIRL2RXH RXIR Low AND 16XCLK
edge (↓ or ↑) to RX falling
—
edge (↓)
RXIR pulse width
1.41
IR131A TRXIRPW
(1)
RXIR bit period
—
IR132 TRXIRP
IR133 TRXIRJ
16XCLK to RXIR jitter
—
16XCLK to RX skew
—
IR134 TRXSKW
RXIR Filter
0.7
IR135 TRXPDFIL
Note 1: Data in the Typical (“Typ”) column is at 5V, +25°C,
design guidance only and are not tested.
Max
Units
—
0
—
±2
—
25
%
%
ns
—
4
3
16
—
—
Conditions
Note 2, 3
Note 2, 4
TXCLK
TXCLK At 115,200 baud
TXCLK At 9600 baud
—
3 TXCLK
µs
16
—
TXCLK
—
1
TXCLK Note 2
—
2.5
µs
—
1.4
µs
Note 5
unless otherwise stated. These parameters are for
2: These parameters (shaded) are characterized but are not tested. These values should be used for design
guidance only.
3: The RXIR pin operation is asynchronous to the 16XCLK pin. This is the error from the desired baud rate for
the system.
4: The RX pin operation is synchronous to the 16XCLK pin. Any error present on the 16XCLK pin
(Parameter 1C) will be refelected on the RX pin.
5: The minimum specification ensures that ALL pulses less then this pulse width are rejected, the maximum
specification ensures that ALL pulses greater than this pulse width are never rejected, and pulse widths
between these may or may not be rejected.
DS21894B-page 24
Preliminary
2004 Microchip Technology Inc.
MCP2122
5.0
DC AND AC CHARACTERISTICS GRAPHS AND TABLES
The graphs and tables are not available at this time
2004 Microchip Technology Inc.
Preliminary
DS21894B-page 25
MCP2122
NOTES:
DS21894B-page 26
Preliminary
2004 Microchip Technology Inc.
MCP2122
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
Example:
8-Lead PDIP (300 mil)
XXXXXXXX
XXXXXNNN
YYWW
GMCP2122
E/P256
0423
Or
MCP2122
E/P 3 256
0503
8-Lead SOIC (150 mil)
Example:
GMCP2122
E/SN0423
256
XXXXXXXX
XXXXYYWW
NNN
Or
MCP2122E
SN 3 0503
256
Legend: XX...X
Y
YY
WW
NNN
Note:
*
Customer specific information*
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
Standard device marking consists of Microchip part number, year code, week code, and traceability
code.
2004 Microchip Technology Inc.
Preliminary
DS21894B-page 27
MCP2122
8-Lead Plastic Dual In-line (P) – 300 mil Body (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
p
eB
B
Units
Dimension Limits
n
p
Number of Pins
Pitch
Top to Seating Plane
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
Tip to Seating Plane
Lead Thickness
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
L
c
§
B1
B
eB
α
β
MIN
.140
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
5
INCHES*
NOM
MAX
8
.100
.155
.130
.170
.145
.313
.250
.373
.130
.012
.058
.018
.370
10
10
.325
.260
.385
.135
.015
.070
.022
.430
15
15
MILLIMETERS
NOM
8
2.54
3.56
3.94
2.92
3.30
0.38
7.62
7.94
6.10
6.35
9.14
9.46
3.18
3.30
0.20
0.29
1.14
1.46
0.36
0.46
7.87
9.40
5
10
5
10
MIN
MAX
4.32
3.68
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
DS21894B-page 28
Preliminary
2004 Microchip Technology Inc.
MCP2122
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil Body (SOIC)
E
E1
p
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Overall Length
Chamfer Distance
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
h
L
φ
c
B
α
β
MIN
.053
.052
.004
.228
.146
.189
.010
.019
0
.008
.013
0
0
A1
INCHES*
NOM
8
.050
.061
.056
.007
.237
.154
.193
.015
.025
4
.009
.017
12
12
MAX
.069
.061
.010
.244
.157
.197
.020
.030
8
.010
.020
15
15
MILLIMETERS
NOM
8
1.27
1.35
1.55
1.32
1.42
0.10
0.18
5.79
6.02
3.71
3.91
4.80
4.90
0.25
0.38
0.48
0.62
0
4
0.20
0.23
0.33
0.42
0
12
0
12
MIN
MAX
1.75
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
0.25
0.51
15
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
2004 Microchip Technology Inc.
Preliminary
DS21894B-page 29
MCP2122
NOTES:
DS21894B-page 30
Preliminary
2004 Microchip Technology Inc.
MCP2122
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
–
X
Temperature
Range
Examples:
/XX
X
Package
Lead Finish
a)
b)
c)
Device
MCP2122: Infrared Encoder/Decoder
Temperature Range
E
Package
P
= Plastic DIP (300 mil, Body), 8-lead
SN = Plastic SOIC (150 mil, Body), 8-lead
Lead Finish
G
MCP2122-E/PG:
Extended Temperature,
PDIP package, Pb-free
MCP2122-E/SNG: Extended Temperature,
SOIC package, Pb-free
MCP2122T-E/SNG: Tape and Reel,
Extended Temperature,
SOIC package. Pb-free
= -40°C to +125°C
= Matte Tin (Pure Sn)
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1.
2.
Your local Microchip sales office
The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
Customer Notification System
Register on our web site (www.microchip.com) to receive the most current information on our products.
2004 Microchip Technology Inc.
Preliminary
DS21894B-page 31
MCP2122
NOTES:
DS21894B-page 32
Preliminary
2004 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION, INCLUDING BUT NOT
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and
its use. Use of Microchip’s products as critical components in
life support systems is not authorized except with express
written approval by Microchip. No licenses are conveyed,
implicitly or otherwise, under any Microchip intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
PICMASTER, SEEVAL, SmartSensor and The Embedded
Control Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, MPASM, MPLIB, MPLINK,
MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail,
PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel and Total
Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
2004 Microchip Technology Inc.
Preliminary
DS21894B-page 33
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
India - Bangalore
Tel: 91-80-2229-0061
Fax: 91-80-2229-0062
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
India - New Delhi
Tel: 91-11-5160-8631
Fax: 91-11-5160-8632
Austria - Weis
Tel: 43-7242-2244-399
Fax: 43-7242-2244-393
Denmark - Ballerup
Tel: 45-4450-2828
Fax: 45-4485-2829
China - Chengdu
Tel: 86-28-8676-6200
Fax: 86-28-8676-6599
Japan - Kanagawa
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
France - Massy
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
China - Fuzhou
Tel: 86-591-8750-3506
Fax: 86-591-8750-3521
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Germany - Ismaning
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Atlanta
Alpharetta, GA
Tel: 770-640-0034
Fax: 770-640-0307
Boston
Westford, MA
Tel: 978-692-3848
Fax: 978-692-3821
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
China - Shunde
Tel: 86-757-2839-5507
Fax: 86-757-2839-5571
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
England - Berkshire
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Taiwan - Hsinchu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
China - Qingdao
Tel: 86-532-502-7355
Fax: 86-532-502-7205
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
San Jose
Mountain View, CA
Tel: 650-215-1444
Fax: 650-961-0286
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
10/20/04
DS21894B-page 34
Preliminary
2004 Microchip Technology Inc.