Charge Pump, 7-Channel Smart LED Driver with I2C Interface ADP8860 FEATURES VALS OPTIONAL PHOTOSENSOR VOUT PHOTOSENSOR 0.1µF D1 D3 VIN D2 E3 D3 D4 E4 D5 D4 B4 B3 C3 D6/ CMP_IN2 A3 1µF 1µF E1 VDDIO SDA A1 ADP8860 C1 C2 VDDIO B1 SCL E2 B2 VDDIO nINT VOUT A2 VDDIO nRST 0.1µF D7 CMP_IN C4 C1+ C1– C1 1µF C2+ C2– C2 1µF D2 A4 GND1 D1 GND2 07967-001 Charge pump with automatic gain selection of 1×, 1.5×, and 2× for maximum efficiency Up to two built-in comparator inputs with programmable modes for ambient light sensing Outdoor, office, and dark modes for maximum backlight power savings 7 independent and programmable LED drivers 6 drivers capable of 30 mA (typical) 1 driver capable of 60 mA (typical) Programmable maximum current limit (128 levels) Standby mode for <1 μA current consumption 16 programmable fade in and fade out times 0.1 sec to 5.5 sec Choose from linear, square, or cubic rates Fading override I2C-compatible interface for all programming Dedicated reset pin and built-in power-on reset (POR) Short-circuit, overvoltage, and overtemperature protection Internal soft start to limit inrush currents Input-to-output isolation during faults or shutdown Operation down to VIN = 2.5 V with undervoltage lockout (UVLO) at VIN = 2.0 V Small wafer level chip scale package (WLCSP) or lead frame chip scale package (LFCSP) TYPICAL OPERATING CIRCUIT Figure 1. APPLICATIONS Mobile display backlighting Mobile phone keypad backlighting Dual RGB backlighting LED indication General backlighting of small format displays GENERAL DESCRIPTION The ADP8860 combines a programmable backlight LED charge pump driver with automatic phototransistor control. This combination allows for significant power savings because it changes the current intensity in office and dark ambient light conditions. By performing this function automatically, it eliminates the need for a processor to monitor the phototransistor. The light intensity thresholds are fully programmable via the I2C® interface. A second phototransistor input, with dedicated comparators, improves the ambient light detection levels for various user operating conditions. The ADP8860 allows as many as six LEDs to be independently driven up to 30 mA (typical). A seventh LED can be driven to 60 mA (typical). All LEDs are programmable for minimum/maximum current and fade in/out times via the I2C interface. These LEDs can also be combined into groups to reduce the processor instructions during fade in/out. Driving this entire configuration is a two-capacitor charge pump with gains of 1×, 1.5×, and 2×. This setup is capable of driving a maximum IOUT of 240 mA from a supply of 2.5 V to 5.5 V. The device includes a variety of safety features including short-circuit, overvoltage, and overtemperature protection. These features allow easy implementation of a safe and robust design. Additionally, input inrush currents are limited via an integrated soft start combined with controlled input-to-output isolation. The ADP8860 is available in two package types, either a compact 2 mm × 2.4 mm × 0.6 mm WLCSP (wafer level chip scale package) or a small LFCSP (lead frame chip scale package). Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. ADP8860 TABLE OF CONTENTS Features .............................................................................................. 1 Backlight Turn On/Turn Off/Dim ........................................... 17 Applications ....................................................................................... 1 Automatic Dim and Turn Off Timers ..................................... 18 General Description ......................................................................... 1 Fade Override ............................................................................. 19 Typical Operating Circuit ................................................................ 1 Ambient Light Sensing .............................................................. 19 Revision History ............................................................................... 2 Automatic Backlight Adjustment ............................................. 20 Specifications..................................................................................... 3 Independent Sink Control ........................................................ 20 2 I C Timing Diagram..................................................................... 5 Short-Circuit Protection Mode ................................................ 21 Absolute Maximum Ratings............................................................ 6 Overvoltage Protection .............................................................. 21 Maximum Temperature Ranges ................................................. 6 Thermal Shutdown/Overtemperature Protection ................. 21 Thermal Resistance ...................................................................... 6 Interrupts ..................................................................................... 23 ESD Caution .................................................................................. 6 Applications Information .............................................................. 24 Pin Configurations and Function Descriptions ........................... 7 Layout Guidelines....................................................................... 24 Typical Performance Characteristics ............................................. 8 Example Circuits ........................................................................ 25 Theory of Operation ...................................................................... 12 I2C Programming and Digital Control ........................................ 26 Power Stage.................................................................................. 13 Backlight Register Descriptions ............................................... 30 Operating Modes ........................................................................ 14 Independent Sink Register Descriptions................................. 37 Backlight Operating Levels ....................................................... 16 Comparator Register Descriptions .......................................... 45 Backlight Maximum and Dim Settings ................................... 17 Outline Dimensions ....................................................................... 49 Automated Fade In and Fade Out ............................................ 17 Ordering Guide .......................................................................... 50 REVISION HISTORY 5/09—Revision 0: Initial Version Rev. 0 | Page 2 of 52 ADP8860 SPECIFICATIONS VIN = 3.6 V, SCL = 2.7 V, SDA = 2.7 V, nINT = open, nRST = 2.7 V, CMP_IN = 0 V, VD1:D7 = 0.4 V, C1 = 1 μF, C2 = 1 μF, COUT = 1 μF, typical values are at TA = 25°C and are not guaranteed, minimum and maximum limits are guaranteed from TA = −40°C to +85°C, unless otherwise noted. Table 1. Parameter SUPPLY Input Voltage Operating Range Startup Level Low Level VIN(START) Hysteresis UVLO Noise Filter Quiescent Current Prior to VIN(START) During Standby After Startup and Switching OSCILLATOR Switching Frequency Duty Cycle OUPUT CURRENT CONTROL Maximum Drive Current D1 to D7 TJ = 25°C TJ = −40°C to +85°C D7 Only (60 mA Setting) TJ = 25°C TJ = −40°C to +85°C LED Current Source Matching 1 All Current Sinks D2 to D7 Current Sinks Leakage Current on LED Pins Equivalent Output Resistance Gain = 1× Gain = 1.5× Gain = 2× Regulated Output Voltage AUTOMATIC GAIN SELECTION Minimum Voltage Gain Increases Minimum Current Sink Headroom Voltage Gain Delay Symbol VIN VIN(START) VIN(STOP) VIN(HYS) tUVLO IQ IQ(START) IQ(STBY) IQ(ACTIVE) Test Conditions/Comments ID7(60 mA) IMATCH IMATCH7 IMATCH6 ID1:D7(LKG) ROUT Typ 2.5 VIN increasing VIN decreasing After startup 1.75 VIN = VIN(START) − 100 mV VIN = 3.6 V, Bit nSTBY = 0, SCL = SDA = 0 V VIN = 3.6 V, Bit nSTBY = 1, IOUT = 0 mA, gain = 2× fSW D ID1:D7(MAX) Min 2.05 1.97 80 10 10 0.3 4.5 Max Unit 5.5 2.30 V V V mV μs 1.0 7.2 μA μA mA 0.8 1 50 1.32 MHz % 26.2 24.4 30 34.1 34.1 mA mA 52.5 48.8 60 67 67 mA mA 0.5 % % μA 5.5 Ω Ω Ω V VD1:D7 = 0.4 V Bit SCR = 0 in the ISC7 register VD7 = 0.4 V, Bit SCR = 1 in the ISC7 register VD1:D7 = 0.4 V VD2:D7 = 0.4 V VIN = 5.5 V, VD1:D7 = 2.5 V, Bit nSTBY = 1 2.0 1.5 VOUT(REG) VIN = 3.6 V, IOUT = 100 mA VIN = 3.1 V, IOUT = 100 mA VIN = 2.5 V, IOUT = 100 mA VIN = 3 V, gain = 2×, IOUT = 10 mA 0.5 3.0 3.8 4.9 VHR(UP) VHR(MIN) Decrease VD1:D7 until the gain switches up IDX = IDX(MAX) × 95% tGAIN The delay after gain has changed and before gain is allowed to change again Rev. 0 | Page 3 of 52 4.3 162 200 180 100 276 mV mV μs ADP8860 Parameter AMBIENT LIGHT SENSING COMPARATORS Ambient Light Sensor Current DAC Bit Step Threshold L2 Level Threshold L3 Level FAULT PROTECTION Startup Charging Current Source Output Voltage Threshold Exit Soft Start Short-Circuit Protection Output Overvoltage Protection Activation Level OVP Recovery Hysteresis Thermal Shutdown Threshold Hysteresis Isolation from Input to Output During Fault Time to Validate a Fault I2C INTERFACE VDDIO Voltage Operating Range Logic Low Input 2 Logic High Input 3 I2C TIMING SPECIFICATIONS Delay from Reset Deassertion to I2C access SCL Clock Frequency SCL High Time SCL Low Time Setup Time Data Repeated Start Stop Condition Hold Time Data Start/Repeated Start Bus Free Time (Stop and Start Conditions) Rise Time (SCL and SDA) Fall Time (SCL and SDA) Pulse Width of Suppressed Spike Capacitive Load Per Bus Line Symbol Test Conditions/Comments Min Typ Max Unit IALS CMP_IN = VD6 = 2.8 V, Bit CMP2_SEL = 1 0.70 1.08 1.33 mA IL2BIT IL3BIT IL2BIT = IALS/250 IL3BIT = IALS/2000 ISS VOUT VOUT(START) VOUT(SC) VOVP VIN = 3.6 V, VOUT = 0.8 × VIN TSD TSD(HYS) IOUTLKG 4.3 0.54 2.5 VOUT rising VOUT falling 5.5 V V 5.8 500 V mV 150 20 °C °C μA 1.5 2 VIN = 3.6 V VIN = 3.6 V Guaranteed by design μs 5.5 0.6 V V V 20 μs 400 1.30 tRESET mA 0.92 × VIN 0.55 × VIN VIN = 5.5 V, VOUT = 0 V, Bit nSTBY = 0 tFAULT VDDIO VIL VIH 3.75 μA μA fSCL tHIGH tLOW 0.6 1.3 KHz μs μs tSU, DAT tSU, STA tSU, STO 100 0.6 0.6 ns μs μs tHD, DAT tHD, STA tBUF 0 0.6 1.3 0.9 μs μs μs tR tF tSP CB 20 + 0.1 CB 20 + 0.1 CB 0 300 300 50 400 ns ns ns pF 1 Current source matching is calculated by dividing the difference between the maximum and minimum current from the sum of the maximum and minimum. VIL is a function of the input voltage. See Figure 16 in the Typical Performance Characteristics section for typical values over operating ranges. 3 VIH is a function of the input voltage. See Figure 16 in the Typical Performance Characteristics section for typical values over operating ranges. 2 Rev. 0 | Page 4 of 52 ADP8860 I2C TIMING DIAGRAM SDA tLOW tR tF tSU, DAT tF tHD, STA tSP tBUF tR SCL S tHD, DAT tHIGH tSU, STA Sr P S 07967-002 S = START CONDITION Sr = REPEATED START CONDITION P = STOP CONDITION tSU, STO Figure 2. I2C Interface Timing Diagram Rev. 0 | Page 5 of 52 ADP8860 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter VIN, VOUT D1, D2, D3, D4, D5, D6, and D7 CMP_IN nINT, nRST, SCL, and SDA Output Short-Circuit Duration Operating Ambient Temperature Range Operating Junction Temperature Range Storage Temperature Range Soldering Conditions ESD (Electrostatic Discharge) Human Body Model (HBM) Charged Device Model (CDM) 1 Rating −0.3 V to +6 V −0.3 V to +6 V −0.3 V to +6 V −0.3 V to +6 V Indefinite –40°C to +85°C1 –40°C to +125°C –65°C to +150°C JEDEC J-STD-020 ±2 kV ±2 kV θJA (junction to air) is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. The θJA, θJB (junction to board), and θJC (junction to case) are determined according to JESD51-9 on a 4-layer printed circuit board (PCB) with natural convection cooling. For the LFCSP package, the exposed pad must be soldered to the GND1 and/or GND2 terminal(s) on the board. Table 3. Thermal Resistance1 Package Type WLCSP LFCSP_VQ 1 The maximum operating junction temperature (TJ(MAX)) supersedes the maximum operating ambient temperature (TA(MAX)). See the Maximum Temperature Ranges section for more information. θJA 48 49.5 N/A means not applicable. ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all voltages are referenced to GND. MAXIMUM TEMPERATURE RANGES The maximum operating junction temperature (TJ(MAX)) supersedes the maximum operating ambient temperature (TA(MAX)). Therefore, in situations where the ADP8860 is exposed to poor thermal resistance and a high power dissipation (PD), the maximum ambient temperature may need to be derated. In these cases, the ambient temperature maximum can be calculated with the following equation: TA(MAX) = TJ(MAX) − (θJA × PD(MAX)) Rev. 0 | Page 6 of 52 θJB 9 N/A θJC N/A 5.3 Unit °C/W °C/W ADP8860 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS D4 D5 CMP_IN D6/CMP_IN2 D7 ADP8860 1 2 3 4 5 ADP8860 TOP VIEW (Not to Scale) 2 3 4 C1+ VOUT VIN GND1 C2+ C2– D7 D6/ CMP_IN2 C1– SDA CMP_IN D5 GND2 nINT D1 D4 nRST SCL D2 D3 A 20 19 18 17 16 D3 D2 D1 SCL nRST PIN 1 INDICATOR 1 B 15 GND1 14 VIN 13 VOUT 12 C2+ 11 C1+ C TOP VIEW (BALL SIDE DOWN) Not to Scale 07967-004 NOTES 1. CONNECT THE EXPOSED PADDLE TO GND1 AND/OR GND2. E 07967-003 nINT SDA GND2 C1– C2– 6 7 8 9 10 D Figure 4. WLCSP Pin Configuration Figure 3. LFCSP Pin Configuration Table 4. Pin Function Descriptions Pin No. LFCSP 14 3 2 1 20 19 17 WLCSP A3 D3 E3 E4 D4 C4 B4 Mnemonic VIN D1 D2 D3 D4 D5 D6/CMP_IN2 16 18 B3 C3 D7 CMP_IN 13 11 9 12 10 15 8 6 A2 A1 C1 B1 B2 A4 D1 D2 VOUT C1+ C1− C2+ C2− GND1 GND2 nINT 5 E1 nRST 7 4 C2 E2 SDA SCL Description Input Voltage 2.5 V to 5.5 V. LED Sink 1. LED Sink 2. LED Sink 3. LED Sink 4. LED Sink 5. LED Sink 6/Comparator Input for Second Phototransistor. When using this pin as a second phototransistor input, a capacitor (0.1 μF recommended) must be connected from this pin to ground. LED Sink 7. Comparator Input for Phototransistor. When using this function, a capacitor (0.1 μF recommended) must be connected from this pin to ground. Charge Pump Output. Charge Pump C1+. Charge Pump C1−. Charge Pump C2+. Charge Pump C2−. Ground. Connect the exposed pad to GND1 and/or GND2. Ground. Connect the exposed pad to GND1 and/or GND2. Processor Interrupt (Active Low). Requires an external pull-up resistor. If this pin is not used, it can be left floating. Hardware Reset (Active Low). This bit resets the device to the default conditions. If not used, this pin must be tied above VIH(MIN). I2C Serial Data. Requires an external pull-up resistor. I2C Clock. Requires an external pull-up resistor. Rev. 0 | Page 7 of 52 ADP8860 TYPICAL PERFORMANCE CHARACTERISTICS VIN = 3.6 V, SCL = 2.7 V, SDA = 2.7 V, nRST = 2.7 V, VD1:D7 = 0.4 V, CIN = 1 μF, C1 = 1 μF, C2 = 1 μF, COUT = 1 μF, TA= 25°C, unless otherwise noted. 2.0 35 VIN = 3.6V ID1:D7 = 30mA IOUT = NO LOAD 1.8 30 1.6 25 1.4 IOUT (mA) 1.0 0.8 20 D1 15 D2 0.6 D3 10 D4 –40°C +25°C +85°C +105°C 2.0 2.5 3.0 3.5 4.0 4.5 5.0 D6 D7 5.5 VIN (V) 0 Figure 5. Typical Operating Current, G = 1× 0 0.6 0.8 1.0 1.2 1.4 1.6 1.8 35 34 4.0 33 3.5 32 3.0 31 IOUT (mA) 4.5 2.5 2.0 VD1:D7 = 0.4V 30 D1 29 D2 D3 28 1.5 D4 –40°C +25°C +85°C +105°C 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 27 25 2.0 5 MISMATCH (%) 0.1 –40°C +25°C +85°C +105°C 4 VIN (V) Figure 7. Typical Standby IQ 5 6 4.5 5.0 5.5 2.0 VIN = 3.6V ID1:D7 = 30mA –40°C +25°C +85°C +105°C 4 3 2 0 0.2 07967-102 3 4.0 1 0.001 2 3.5 6 1 1 3.0 Figure 9. Typical Diode Matching vs. VIN SCL = SDA = 0V nRST = 2.7V 0 2.5 VIN (V) Figure 6. Typical Operating Current, G = 2×, IQ(ACTIVE) 0.01 D6 D7 5.5 VIN (V) 10 D5 26 07967-101 1.0 2.0 Figure 8. Typical Diode Current vs. Current Sink Headroom Voltage (VHR) IOUT = NO LOAD IQ (mA) 0.4 VHR (V) 5.0 IQ (µA) 0.2 07967-103 0 1.5 D5 5 07967-104 0.2 07967-100 0.4 07967-105 IQ (mA) 1.2 0.4 0.6 0.8 1.0 1.2 VHR (V) 1.4 1.6 1.8 Figure 10. Typical Diode Matching vs. Current Sink Headroom Voltage (VHR) Rev. 0 | Page 8 of 52 ADP8860 35 1.0 VIN = 3.6V ID1:D7 = 30mA IOUT = 100mA 0.9 30 0.8 0.7 20 ROUT (Ω) 15 0.5 0.4 0.3 10 –40°C +25°C +85°C +105°C 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 –40°C +25°C +85°C +105°C 0.2 0.1 2.0 VHR (V) 0 2.0 07967-106 5 0 0.6 3.0 3.5 4.0 4.5 5.0 5.5 VIN (V) Figure 11. Typical Diode Current vs. Current Sink Headroom Voltage (VHR) 1 2.5 07967-109 IOUT (mA) 25 Figure 14. Typical ROUT (G = 1×) vs. VIN 10 VIN = 3.6V VD1:D7 = 0.40V VOUT = 80% OF VIN 9 0 7 –2 IOUT (mA) –3 6 5 4 3 –40°C +25°C +85°C +105°C 2 –5 1 –10 20 50 80 110 JUNCTION TEMPERATURE (°C) 0 2.0 07967-107 –6 –40 4.0 4.5 5.0 5.5 5.5 1.4 VIH = +25°C 6 VIH = +85°C 1.2 5 VIH = –40°C THRESHOLD (V) 1.0 G = 2× @ VIN = 2.5V 4 3 G = 1.5× @ VIN = 3V 2 0.8 VIL = +25°C VIL = +85°C 0.6 VIL = –40°C 0.4 1 0.2 G = 1× @ VIN = 3.6V –20 0 20 40 60 TEMPERATURE (°C) 80 100 0 2.5 07967-108 ROUT (Ω) 3.5 Figure 15. Typical Soft Start Current, ISS IOUT = 100mA 0 –40 3.0 VIN (V) Figure 12. Typical Change In Diode Current vs. Temperature 7 2.5 07967-110 –4 07967-111 IOUT DEVIATION (%) 8 –1 3.0 3.5 4.0 4.5 5.0 VIN (V) Figure 16. Typical I2C Thresholds, VIH and VIL Figure 13. ROUT vs. Temperature Rev. 0 | Page 9 of 52 ADP8860 1.4 1.3 0.9 450 0.8 400 0.7 350 0.6 300 0.5 250 0.4 200 0.3 150 0.2 100 1.1 1.0 IIN (mA) EFFICIENCY (%) IALS (mA) 1.2 0.9 4.0 4.5 5.0 5.5 VIN (V) 0 2.5 VIN = 3V GAIN = 2× IOUT = 10mA 400 EFFICIENCY (%) 0.7 5.1 5.0 4.9 0.2 4.6 0.1 JUNCTION TEMPERATURE (°C) 250 200 0.4 4.7 110 300 0.5 0.3 80 350 0.6 4.8 50 0 5.5 0.9 0.8 20 5.0 450 5.2 –10 4.5 1.0 5.3 4.5 –40 4.0 Figure 20. Typical Efficiency (Low Vf Diode) 07967-113 VOUT (V) 5.4 3.5 VIN (V) Figure 17. Typical ALS Current, IALS 5.5 3.0 IIN (mA) 3.5 50 IOUT = 210mA, Vf = 3.2V 150 100 IOUT = 140mA, Vf = 3.85V 0 2.5 50 IOUT = 210mA, Vf = 4.25V 3.0 3.5 4.0 4.5 5.0 0 5.5 07967-116 3.0 07967-112 0.7 2.5 IOUT = 140mA, Vf = 3.1V 0.1 07967-115 –40°C +25°C +85°C +105°C 0.8 VIN (V) Figure 21. Typical Efficiency (High Vf Diode) Figure 18. Typical Regulated Output Voltage (VOUT(REG)) 6.0 T VIN (AC-COUPLED) 50mV/DIV 1 5.8 VOUT (AC-COUPLED) 50mV/DIV 2 5.6 IIN (AC-COUPLED) 10mA/DIV 5.4 CIN = 1µF, COUT = 1µF, C1 = 1µF, C2 = 1µF VIN = 3.6V IOUT = 120mA OVP RECOVERY 5.2 –40 –10 20 50 80 110 JUNCTION TEMPERATURE (°C) 500ns/DIV Figure 19. Typical Overvoltage Protection (OVP) Threshold Figure 22. Typical Operating Waveforms, G = 1× Rev. 0 | Page 10 of 52 07967-117 3 07967-114 VOUT (V) OVP THRESHOLD ADP8860 VIN = 3.7V T VIN (AC-COUPLED) 50mV/DIV 1 VOUT (1V/DIV) VOUT (AC-COUPLED) 50mV/DIV 2 2 IIN (10mA/DIV) IIN (AC-COUPLED) 10mA/DIV 500ns/DIV 4 Figure 23. Typical Operating Waveforms, G = 1.5× T 1 VOUT (AC-COUPLED) 50mV/DIV 2 IIN (AC-COUPLED) 10mA/DIV 07967-119 3 500ns/DIV 100µs/DIV Figure 25. Typical Start-Up Waveform VIN (AC-COUPLED) 50mV/DIV CIN = 1µF, COUT = 1µF, C1 = 1µF, C2 = 1µF VIN = 2.5V IOUT = 120mA IOUT (10mA/DIV) Figure 24. Typical Operating Waveforms, G = 2× Rev. 0 | Page 11 of 52 07967-120 CIN = 1µF, COUT = 1µF, C1 = 1µF, C2 = 1µF VIN = 3.0V IOUT = 120mA 07967-118 3 ADP8860 THEORY OF OPERATION The ADP8860 allows up to seven LEDs to be independently driven up to 30 mA (typical). The seventh LED can also be driven to 60 mA (typical). All LEDs can be individually programmed or combined into a group to operate backlight LEDs. A full set of safety features including short-circuit, overvoltage, and overtemperature protection with input-to-output isolation allow for a robust and safe design. The integrated soft start limits inrush currents at startup, restart attempts, and gain transitions. The ADP8860 combines a programmable backlight LED charge pump driver with automatic phototransistor control. This combination allows for significant power savings because it is able to change the current intensity based on the lighting conditions. It performs this function automatically thereby removing the need for a processor to monitor the phototransistor. The light intensity levels are fully programmable via the I2C interface. A second phototransistor input, with dedicated comparators, improves the ambient light detection abilities for various useroperating conditions. VALS OPTIONAL PHOTOSENSOR D3 ID1 D1 E3 D2 ID2 ID3 E4 D3 D4 D4 ID4 C4 ID5 D5 B4 D6 B3 CMP_IN D7 C3 GAIN SELECT LOGIC ID7 ID6 CIN VIN VIN CHARGE PUMP LOGIC VREFS VOUT A2 IREFS UVLO VDDIO COUT EN STNDBY CLK NOISE FILTER nRST E1 SDA A1 LIGHT SENSOR LOGIC 50µs RESET SCL CHARGE PUMP (1×, 1.5×, 2×) STNDBY E2 C1 B1 B2 I2C LOGIC C2 ISS SOFT START A3 C1+ C1 1µF C1– C2+ C2 1µF C2– SWITCH CONTROL ILED CONTROL nINT D2 A4 D1 GND1 GND2 Figure 26. Detailed Block Diagram Rev. 0 | Page 12 of 52 07967-011 VBAT VIN PHOTOSENSOR CONVERSION ADP8860 POWER STAGE Because typical white LEDs require up to 4 V to drive them, some form of boosting is required over the typical variation in battery voltage. The ADP8860 accomplishes this with a high efficiency charge pump capable of producing a maximum IOUT of 240 mA over the entire input voltage range (2.5 V to 5.5 V). Charge pumps use the basic principle that a capacitor stores charge based on the voltage applied to it, as shown in the following equation: Q=C×V (1) By charging the capacitors in different configurations, the charge, and therefore the gain, can be optimized to deliver the voltage required to power the LEDs. Because a fixed charging and discharging combination must be used, only certain multiples of gain are available. The ADP8860 is capable of automatically optimizing the gain (G) from 1×, 1.5×, and 2×. These gains are accomplished with two capacitors (labeled C1 and C2 in Figure 26) and an internal switching network. In G = 1× mode, the switches are configured to pass VIN directly to VOUT. In this mode, several switches are connected in parallel to minimize the resistive drop from input to output. In G = 1.5× and 2× modes, the switches alternatively charge from the battery and discharge into the output. For G = 1.5×, the capacitors are charged from VIN in series and are discharged to VOUT in parallel. For G = 2×, the capacitors are charged from VIN in parallel and are discharged to VOUT in parallel. In certain fault modes, the switches are opened and the output is physically isolated from the input. Automatic Gain Selection Each LED that is driven requires a current source. The voltage on this current source must be greater than a minimum headroom voltage (200 mV typical) to maintain accurate current regulation. The gain is automatically selected based on the minimum voltage (VDx) at all of the current sources. At startup, the device is placed into G = 1× mode and the output charges to VIN. If any VDx level is less than the required headroom (200 mV), the gain is increased to the next step (G = 1.5×). A 100 μs delay is allowed for the output to stabilize prior to the next gain switching decision. If there remains insufficient current sink headroom, then the gain is increased again to 2×. Conversely, to optimize efficiency, it is not desirable for the output voltage to be too high. Therefore, the gain reduces when the headroom voltage is great enough. This point (labeled VDMAX in Figure 27) is internally calculated to ensure that the lower gain still results in ample headroom for all the current sinks. The entire cycle is illustrated in Figure 27. Note that the gain selection criteria apply only to active current sources. If current sources have been deactivated through an I2C command (for example, only five LEDs are used), then the voltages on the deactivated current sources are ignored. Rev. 0 | Page 13 of 52 ADP8860 STBY EXIT STBY STATUP: CHARGE VIN TO VOUT 0 EXIT STARTUP 1 VOU T > VOUT(START) 0 WAIT 100µs (TYP) G=1 MIN (VD1:D7) < VHR(UP) 1 G = 3/2 1 WAIT 100µs (TYP) MIN (VD1:D7) < VHR(UP) 1 0 0 MIN (VD1:D7) > VDMAX 0 1 WAIT 100µs (TYP) MIN (VD1:D7) < VDMAX 07967-012 G=2 NOTES 1. VDMAX IS THE CALCULATED GAIN DOWN TRANSITION POINT. Figure 27. State Diagram for Automatic Gain Selection Soft Start Feature Shutdown Mode At startup (either from UVLO activation or fault/standby recovery), the output is first charged by ISS (3.75 mA typical) until it reaches about 92% of VIN. This soft start feature reduces the inrush current that is otherwise present when the output capacitance is initially charged to VIN. When this point is reached, the controller enters 1× mode. If the output voltage is not sufficient, then the automatic gain selection determines the optimal point as defined in the Automatic Gain Selection section. Shutdown mode disables all circuitry, including the I2C receivers. Shutdown occurs when VIN is below the undervoltage thresholds. When VIN rises above VIN(START) (2.05 V typical), all registers are reset and the part is placed into standby mode. OPERATING MODES There are four different operating modes: active, standby, shutdown, and reset. Reset Mode In reset mode, all registers are set to their default values and the part is placed into standby. There are two ways to reset the part: power-on reset (POR) and the nRST pin. POR is activated anytime that the part exits shutdown mode. After a POR sequence is complete, the part automatically enters standby mode. After startup, the part can be reset by pulling the nRST pin low. As long as the nRST pin is low, the part is held in a standby state but no I2C commands are acknowledged (all registers are kept at their default values). After releasing the nRST pin, all registers remain at their default values, and the part remains in standby; however, the part does accept I2C commands. Active Mode In active mode, all circuits are powered up and in a fully operational state. This mode is entered when nSTBY (in Register MDCR) is set to 1. Standby Mode Standby mode disables all circuitry except for the I2C receivers. Current consumption is reduced to less than 1 μA. This mode is entered when nSTBY is set to 0 or when the nRST pin is held low for more than 100 μs (maximum). When standby is exited, a soft start sequence is performed. The nRST pin has a 50 μs (typical) noise filter to prevent inadvertent activation of the reset function. The nRST pin must be held low for this entire time to activate reset. The operating modes function according to the timing diagram in Figure 28. Rev. 0 | Page 14 of 52 ADP8860 SHUTDOWN VIN CROSSES ~2.05V AND TRIGGERS POWER ON RESET VIN nRST MUST BE HIGH FOR 20µs (MAX) BEFORE SENDING I2C COMMANDS BIT nSTBY IN REGISTER MDCR GOES HIGH ~100µs DELAY BETWEEN POWER UP AND WHEN I2C COMMANDS CAN BE RECEIVED nSTBY nRST IS LOW, WHICH FORCES nSTBY LOW AND RESETS ALL I2C REGISTERS 25µs TO 100µs NOISE FILTER nRST VIN ~3.75mA CHARGES VOUT TO VIN LEVEL SOFT START 1.5× 2× 1× GAIN CHANGES ONLY OCCUR WHEN NECESSARY, BUT HAVE A MIN TIME BEFORE CHANGING 10µs 100µs Figure 28. Typical Timing Diagram Rev. 0 | Page 15 of 52 SOFT START 07967-013 VOUT ADP8860 By default, the backlight operates at daylight level (BLV = 00), where the maximum brightness is set using Register 0x09 (BLMX1). A daylight dim setting can also be set using Register 0x0A (BLDM1). When operating at office level (BLV = 01), the backlight maximum and dim brightness settings are set by Register 0x0B (BLMX2) and Register 0x0C (BLDM2). When operating at the dark level (BLV = 10), the backlight maximum and dim brightness settings are set by Register 0x0D (BLMX3) and Register 0x0E (BLDM3). BACKLIGHT OPERATING LEVELS Backlight brightness control operates in three distinct levels: daylight (L1), office (L2), and dark (L3). The BLV bits in Register 0x04 control the specific level in which the backlight operates. These bits can be changed manually, or if in automatic mode (CMP_AUTOEN is set high in Register 0x01), by the ambient light sensor (see the Ambient Light Sensing section). 30mA DAYLIGHT (L1) OFFICE (L2) DARK (L3) BACKLIGHT CURRENT DAYLIGHT_MAX OFFICE_MAX DARK_MAX DAYLIGHT_DIM OFFICE_DIM 0 BACKLIGHT OPERATING LEVELS Figure 29. Backlight Operating Levels Rev. 0 | Page 16 of 52 07967-014 DARK_DIM ADP8860 BACKLIGHT MAXIMUM AND DIM SETTINGS Table 5. Available Fade In and Fade Out Rates The backlight maximum and dim current settings are determined by a 7-bit code programmed by the user into the registers previously listed in the Backlight Operating Levels section. The 7-bit resolution allows the user to set the backlight to one of 128 different levels between 0 mA and 30 mA. The ADP8860 can implement two distinct algorithms to achieve a linear and a nonlinear relationship between input code and backlight current. The law bits in Register 0x04 are used to change between these algorithms. Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 By default, the ADP8860 uses a linear algorithm (law = 00), where the backlight current increases linearly for a corresponding increase of input code. Backlight current (in millamperes) is determined by the following equation: Backlight Current (mA) = Code × (Full-Scale Current/127) (2) where: Code is the input code programmed by the user. Full-Scale Current is the maximum sink current allowed per LED (typically 30 mA). The ADP8860 can also implement a nonlinear (square approximation) relationship between input code and backlight current level. In this case (law = 01), the backlight current (in milliamperes) is determined by the following equation: ⎛ Full − Scale Current Backlight Current (mA) = ⎜ Code × ⎜ 127 ⎝ The fade profile is based on the transfer law selected (linear, square, Cubic 10, or Cubic 11) and the delta between the actual current and the target current. Smaller changes in current reduce the fade time. For linear and square law fades, the fade time is given by Fade Time = Fade Rate × (Code/127) (4) 2 ⎞ ⎟ (3) ⎟ ⎠ Figure 30 shows the backlight current level vs. input code for both the linear and square law algorithms. 30 where the Fade Rate is shown in Table 5. The Cubic 10 and Cubic 11 laws also use the square backlight currents in Equation 3; however, the time between each step is varied to produce a steeper slope at higher currents and a shallower slope at lighter currents (see Figure 31). 30 25 25 LINEAR 20 CURRENT (mA) 15 LINEAR 10 SQUARE 15 SQUARE 10 CUBIC 11 5 5 CUBIC 10 0 32 64 SINK CODE 96 128 07967-015 0 20 0 0 0.25 0.50 0.75 1.00 UNIT FADE TIME Figure 30. Backlight Current vs. Input Code 07967-016 BACKLIGHT CURRENT (mA) Fade Rate (in sec per Full-Scale Current) 0.1 (disabled) 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.5 4.0 4.5 5.0 5.5 Figure 31. Comparison of the Dimming Transfers Laws AUTOMATED FADE IN AND FADE OUT The LED drivers are easily configured for automated fade in and fade out. Sixteen fade in and fade out rates can be selected via the I2C interface. Fade in and fade out rates range from 0.1 sec to 5.5 sec (per full-scale current, either 30 mA or 60 mA). BACKLIGHT TURN ON/TURN OFF/DIM With the device in active mode (nSTBY = 1), the backlight can be turned on using the BL_EN bit in Register 0x01. Before turning on the backlight, the user chooses which level (daylight (L1), office (L2), or dark (L3)) in which to operate, and ensures that maximum and dim settings are programmed for that level. Rev. 0 | Page 17 of 52 ADP8860 The backlight turns on when BL_EN = 1. The backlight turns off when BL_EN = 0. BACKLIGHT CURRENT BACKLIGHT CURRENT DIM TIMER RUNNING DIM TIMER RUNNING MAX MAX DIM BL_EN = 0 Figure 34. Dim Timer While the backlight is on (BL_EN = 1), the user can change to the dim setting by programming DIM_EN = 1 in Register 0x01. If DIM_EN = 0, the backlight reverts to its maximum setting. BACKLIGHT CURRENT MAX BL_EN = 0 07967-018 DIM_EN = 0 If the user clears the DIM_EN bit, the backlight reverts to its maximum setting and the dim timer begins counting again. When the dim timer expires, the internal state machine again sets DIM_EN = 1, and the backlight enters its dim setting. The backlight can be turned off at any point during the dim timer countdown by clearing BL_EN. The user can also program the backlight to turn off automatically by using the OFFT timer in Register 0x06. The off timer has 127 settings ranging from 1 sec to 127 sec. Program the off timer (OFFT) before turning on the backlight. If BL_EN = 1, the backlight turns on to its maximum setting and the off timer starts counting. When the off timer expires, the internal state machine clears the BL_EN bit, and the backlight turns off. DIM DIM_EN = 1 BL_EN = 0 SET BY USER SET BY INTERNAL STATEMACHINE Figure 32. Backlight Turn On/Off BL_EN = 1 DIM_EN = 0 DIM_EN = 1 07967-019 BL_EN = 1 07967-017 BL_EN = 1 DIM_EN = 1 BACKLIGHT CURRENT Figure 33. Backlight Turn On/Dim/Turn Off The maximum and dim settings can be set between 0 mA and 30 mA; therefore, it is possible to program a dim setting that is greater than a maximum setting. For normal expected operation, ensure that the dim setting is programmed to be less than the maximum setting. OFF TIMER RUNNING MAX The user can program the backlight to dim automatically by using the DIMT timer in Register 0x07. The dim timer has 127 settings ranging from 1 sec to 127 sec. Program the dim timer (DIMT) before turning on the backlight. If BL_EN = 1, the backlight turns on to its maximum setting and the dim timer starts counting. When the dim timer expires, the internal state machine sets DIM_EN = 1, and the backlight enters its dim setting. BL_EN = 1 BL_EN = 0 SET BY USER SET BY INTERNAL STATE MACHINE 07967-020 AUTOMATIC DIM AND TURN OFF TIMERS Figure 35. Off Timer The backlight can be turned off at any point during the off timer countdown by clearing BL_EN. The dim timer and off timer can be used together for sequential maximum-to-dim-to-off functionality. With both the dim and off timers programmed, if BL_EN is asserted, the backlight turns on to its maximum setting, and when the dim timer expires, the backlight changes to its dim setting. When the off timer expires, the backlight turns off. Rev. 0 | Page 18 of 52 ADP8860 These comparators have two programmable trip points (L2 and L3) that select among three of the backlight operation modes (daylight, office, and dark) based on the ambient lighting conditions. DIM TIMER RUNNING MAX The L3 comparator controls the dark-to-office mode transition. The L2 comparator controls the office-to-daylight transition (see Figure 38). The currents for the different lighting modes are defined in the BLMXx and BLDMx registers (see the Backlight Operating Levels section). OFF TIMER RUNNING BL_EN = 1 DIM_EN = 1 BL_EN = 0 SET BY USER SET BY INTERNAL STATE MACHINE L2_OUT = 1 L3_OUT = 1 07967-021 DIM Figure 36. Dim and Off Timers Used Together 0A A fade override feature (FOVR in Register CFGR (0x04)) enables the host to override the preprogrammed fade in or fade out settings. If FOVR is set and the backlight is enabled in the middle of a fade out process, the backlight instantly (within approximately 100 ms) returns to its maximum setting. Alternatively, if the backlight is fading in, reasserting BL_EN overrides the programmed fade in time and the backlight instantly goes to its final fade value. This is useful for situations where a key is pressed during a fade sequence. However, if FOVR is cleared and the backlight is enabled in the middle of a fade process, the backlight gradually brightens from where it was interrupted (it does not go down to 0 and then come back on). FADE-IN OVER-RIDDEN L2_OUT = 0 L3_OUT = 0 0 LUX FADE OVERRIDE BACKLIGHT CURRENT L2_OUT = 1 L3_OUT = 0 DARK OFFICE L3 DAYLIGHT L2 07967-023 BACKLIGHT CURRENT BRIGHTNESS Figure 38. Light Sensor Modes Based on the Detected Ambient Light Level Each light sensor comparator uses an external capacitor together with an internal reference current source to form an analog-todigital converter (ADC) that samples the output of the external photosensor. The ADC result is fed into two programmable trip comparators. The ADC has an input range of 0 μA to 1080 μA (typical). L2_EN FADE-OUT OVER-RIDDEN L2_TRIP L2_HYS L2_OUT MAX FILTER SETTINGS ADC L3_TRIP BL_EN = 1 BL_EN = 1 (RE-ASSERTED) BL_EN = 0 BL_EN = 1 BL_EN = 0 07967-022 L3_HYS L3_EN Figure 39. Ambient Light Sensing and Trip Comparators Figure 37. Fade Override Function (FOVR is High) AMBIENT LIGHT SENSING The ADP8860 integrates two ambient light sensing comparators. One of the ambient light sensing comparator pins (CMP_IN) is always available. The second pin (D6/CMP_IN2) can be activated rather than connecting an LED to D6. Activating the CMP_IN2 function of the pin is accomplished through Bit CMP2_SEL in Register CFGR. Therefore, when Bit CMP2_SEL is set to 0, Pin D6/CMP_IN2 is programmed as a current sink. When Bit CMP2_SEL is set to 1, Pin D6/CMP_IN2 becomes the input for a second phototransistor. L3_OUT 07967-024 PHOTO SENSOR OUTPUT The L2_CMPR detects when the photosensor output has dropped below the programmable L2_TRP point (Register 0x1D). If this event occurs, then the L2_OUT status signal is set. L2_CMPR contains programmable hysteresis, meaning that the photosensor output must rise above L2_TRP + L2_HYS before L2_OUT clears. L2_CMPR is enabled via the L2_EN bit. The L2_TRP and L2_HYS values of L2_CMPR can be set between 0 μA and 1080 μA (typical) in steps of 4.3 μA (typical). The L3_CMPR detects when the photosensor output has dropped below the programmable L3_TRP point (Register 0x1F). If this event occurs, the L3_OUT status signal is set. L3_CMPR Rev. 0 | Page 19 of 52 ADP8860 contains programmable hysteresis, meaning that the photosensor output must rise above L3_TRP + L3_HYS before L3_OUT clears. L3_CMPR is enabled via the L3_EN bit. The L3_TRP and L3_HYS values of L3_CMPR can be set between 0 μA and 137.7 μA (typical) in steps of 0.54 μA (typical). L2_TRP L2_HYS L3_TRP 1 10 ADC RANGE (µA) 100 1000 07967-025 L3_HYS Figure 40. Comparator Ranges Note that the full-scale value of the L2_TRP and L2_HYS registers is 250 (decimal). Therefore, if the value of L2_TRP + L2_HYS exceeds 250, the comparator output is unable to deassert. For example, if L2_TRP is set at 204 (80% of the fullscale value, or approximately 0.80 × 1080 μA = 864 μA), then L2_HYS must be set at less than 46 (250 − 204 = 46). If it is not, then the L2_HYS + L2_TRP exceeds 250 and the L2_CMPR comparator is never allowed to go low. When both phototransistors are enabled and programmed in automatic mode (through Bit L3_EN and Bit L2_EN in Register 0x1B and Register 0x1C), the user application needs to determine which of the comparator outputs to use, selecting Bit SEL_AB in Register 0x04 for automatic light sensing transitions. For example, the user’s software may select the comparator of the phototransistor exposed to higher light intensity to control the transition between the programmed backlight intensity levels. The L2_CMPR and L3_CMPR comparators can be enabled independently of each other, or can operate simultaneously. A single conversion from each ADC takes 80 ms (typical). When CMP_AUTOEN is set for automatic backlight adjustment (see the Automatic Backlight Adjustment section), the ADC and comparators run continuously. If the backlight is disabled and at least one independent sink is enabled, it is possible to use the light sensor comparators in a single shot mode. A single shot read of the photocomparators is performed by setting the FORCE_RD bit. After the single shot measurement is completed, the internal state machine clears the FORCE_RD bit. The interrupt flags (CMP_INT and CMP_INT2) can be used to notify the system when either L2 or L3 changes state. Refer to the Interrupts section for more information. AUTOMATIC BACKLIGHT ADJUSTMENT The ambient light sensor comparators can automatically transition the backlight between one of its three operating levels. To enable this mode, set the CMP_AUTOEN bit in Register 0x01. When enabled, the internal state machine takes control of the BLV bits and changes them based on the L2_OUT and L3_OUT status bits. When L2_OUT is set high, it indicates that the ambient light conditions have dropped below the L2_TRP point and the backlight should move to its office (L2) level. When L3_OUT is set high, it indicates that ambient light conditions have dropped below the L3_TRP point and the backlight should move to its dark (L3) level. Table 6 shows the relationship between backlight operation and the ambient light sensor comparator outputs. The L3_OUT status bit has greater priority; therefore, the backlight operates at L3 (dark) even if L2_OUT is set. Filter times of between 80 ms and 10 sec can be programmed for the comparators (Register 0x1B and Register 0x1C) before they change state. Table 6. Comparator Output Truth Table CMP_AUTOEN 0 L3_OUT X1 L2_OUT X1 1 0 0 1 0 1 1 1 X1 1 Backlight Operation BLV can be manually set by the user BLV = 00, backlight operates at L1 (daylight) BLV = 01, backlight operates at L2 (office) BLV = 10, backlight operates at L3 (dark) X is the don’t care bit. INDEPENDENT SINK CONTROL Each of the seven LEDs can be configured (in Register 0x05) to operate as either part of the backlight or to operate as an independent sink current (ISC). Each ISC can be enabled independently and has its own current level. All ISCs share the same fade in rates, fade out rates, and fade law. The ISCs have additional timers to facilitate blinking functions. A shared on timer (SCON) used in conjunction with the off timers of each ISC (SC1OFF, SC2OFF, SC3OFF, SC4OFF, SC5OFF, SC6OFF, and SC7OFF) allow the LED current sinks to be configured in various blinking modes. The on timer can be set to four different settings: 0.2 sec, 0.6 sec, 0.8 sec, and 1.2 sec. The off timers have four different settings: disabled, 0.6 sec, 1.2 sec, and 1.8 sec. Blink mode is activated by setting the off timers to any setting other than disabled. Rev. 0 | Page 20 of 52 ADP8860 Program all fade, on, and off timers before enabling any of the LED current sinks. If ISCx is on during a blink cycle and SCx_EN is cleared, it turns off (or fades to off if fade out is enabled). If ISCx is off during a blink cycle and SCx_EN is cleared, it stays off. SCx CURRENT ON TIME FADE-IN ON TIME FADE-OUT FADE-IN FADE-OUT MAX voltage, the ADP8860 detects when the output voltage rises to VOUT(REG). It then increases the effective ROUT of the gain stage to reduce the voltage that is delivered. This effectively regulates VOUT to VOUT(REG); however, there is a limit to the effect that this system can have on regulating VOUT. It is designed only for normal operation and it is not intended to protect against faults or sudden load changes. When the output voltage is regulated to VOUT(REG) no interrupt is set and the operation is transparent to the LEDs and the overall application. Abnormal Overvoltage OFF TIME SCx_EN SET BY USER 07967-026 OFF TIME Figure 41. Independent Sink Blink Mode with Fading SHORT-CIRCUIT PROTECTION MODE The ADP8860 can protect against short circuits on the output (VOUT). Short-circuit protection (SCP) is activated at the point when VOUT < 55% of VIN. Note that this SCP sensing is disabled during both start-up and restart attempts (fault recovery). SCP sensing reenables 4 ms (typical) after activation. During a shortcircuit fault, the device enters a low current consumption state and an interrupt flag is set. The device can be restarted at any time after receiving a short-circuit fault by simply rewriting nSTBY = 1. It then repeats another complete soft start sequence. Note that the value of the output capacitance (COUT) should be small enough to allow VOUT to reach approximately 55% (typical) of VIN within the 4 ms (typical) time. If COUT is too large, the device inadvertently enters short-circuit protection. OVERVOLTAGE PROTECTION Overvoltage protection (OVP) is implemented on the output. There are two types of overvoltage events: normal (no fault) and abnormal (from a fault or sudden load change). Normal Overvoltage In a normal (no fault) overvoltage, the output voltage approaches VOUT(REG) (4.9 V typical) during normal operation. This is not caused by a fault or load change, but it is simply a consequence of the input voltage times the gain reaching the same level as the clamped output voltage (VOUT(REG)). To prevent this type of over- Because of the open-loop behavior of the charge pump as well as how the gain transitions are computed, a sudden load change or fault can abnormally force VOUT beyond 6 V. This causes an abnormal overvoltage situation. If the event happens slowly enough, the system first tries to regulate the output to 4.9 V as in a normal overvoltage scenario. However, if this is not sufficient, or if the event happens too quickly, then the ADP8860 enters overvoltage protection (OVP) mode when VOUT exceeds the OVP threshold (typically 5.8 V). In the OVP mode, only the charge pump is disabled to prevent VOUT from rising too high. The current sources and all other device functionality remain intact. When the output voltage falls by about 500 mV (to 5.3 V typical), the charge pump resumes operation. If the fault or load step recurs, the process may repeat. An interrupt flag is set at each OVP instance. THERMAL SHUTDOWN/OVERTEMPERATURE PROTECTION If the die temperature of the ADP8860 rises above a safe limit (150°C typical), the controllers enter thermal shutdown (TSD) protection mode. In this mode, most of the internal functions shut down, the part enters standby, and the TSD_INT interrupt is set. When the die temperature decreases below ~130°C, the part can be restarted. To restart the part, simply remove it from standby. No interrupt is generated when the die temperature falls below 130°C. However, if the software clears the pending TSD_INT interrupt and the temperature remains above 130°C, another interrupt is generated. The complete state machine for these faults (SCP, OVP, and TSD) is shown in Figure 42. Rev. 0 | Page 21 of 52 ADP8860 STBY 0 EXIT STBY 1 TSD FAULT DIE TEMP > TSD EXIT STBY 0 1 STARTUP: CHARGE VIN TO VOUT DIE TEMP < TSD – TSD(HYS) SCP FAULT 0 VOUT > VOUT(START) 1 0 EXIT STARTUP VOUT < VOUT(SC) 0 1 VOUT < VOVP – VOVP(HYS) 0 0 G=1 WAIT 100µs (TYP) MIN (VD1:D7) < VHR(UP) 1 VOUT > VOVP 1 OVP FAULT 1 1 0 VOUT < VOVP – VOVP (HYS) 0 G = 3/2 WAIT 100µs (TYP) MIN (VD1:D7) < VHR(UP) 0 0 MIN (VD1:D7) > VDMAX VOUT > VOUT(REG) 1 1 1 0 OVP FAULT TRY TO REGULATE VOUT TO VOUT(REG) 1 VOUT > VOVP 0 1 VOUT < VOVP – VOVP (HYS) 0 0 1 WAIT 100µs (TYP) MIN (VD1:D7) > VDMAX VOUT > VOUT(REG) 1 0 OVP FAULT G=2 TRY TO REGULATE VOUT TO VOUT(REG) NOTES 1. VDMAX IS THE CALCULATED GAIN DOWN TRANSITION POINT. 07967-027 VOUT > VOVP Figure 42. Fault State Machine Rev. 0 | Page 22 of 52 ADP8860 • INTERRUPTS There are five interrupt sources available on the ADP8860. • • Main light sensor comparator: CMP_INT sets every time the main light sensor comparator detects a threshold (L2 or L3) transition (rising or falling conditions). Sensor Comparator 2: CMP2_INT interrupt works the same way as CMP_INT, except the sensing input derives from the second light sensor. The programmable thresholds are the same as the main light sensor comparator. • • Overvoltage protection: OVP_INT is generated when the output voltage exceeds 5.8 V (typical). Thermal shutdown circuit: An interrupt (TSD_INT) is generated when entering overtemperature protection. Short-circuit detection: SHORT_INT is generated when the device enters short-circuit protection mode. The interrupt (if any) that appears on the nINT pin is determined by the bits mapped in Register INTR_EN. To clear an interrupt, write a 1 to the interrupt in the MDCR2 register or reset the part. Reading the interrupt, or writing a 0, has no effect. Rev. 0 | Page 23 of 52 ADP8860 APPLICATIONS INFORMATION The ADP8860 allows the charge pump to operate efficiently with a minimum of external components. Specifically, the user must select an input capacitor (CIN), output capacitor (COUT), and two charge pump fly capacitors (C1 and C2). CIN should be 1 μF or greater. The value must be high enough to produce a stable input voltage signal at the minimum input voltage and maximum output load. A 1 μF capacitor for COUT is recommended. Larger values are permissible, but care must be exercised to ensure that VOUT charges above 55% (typical) of VIN within 4 ms (typical). See the Short-Circuit Protection Mode section for more details. For best practice, it is recommended that the two charge pump fly capacitors be 1 μF; larger values are not recommended and smaller values may reduce the ability of the charge pump to deliver maximum current. For optimal efficiency, the charge pump fly capacitors should have low equivalent series resistance (ESR). Low ESR X5R or X7R capacitors are recommended for all four components. Use voltage ratings of 10 V or greater for these capacitors. If one or both ambient light sensor comparator inputs (CMP_IN and D6/CMP_IN2) are used, a small capacitor (0.1 μF is recommended) must be connected from the input to ground. Any color of LED can be used if the Vf (forward voltage) is less than 4.1 V. However, using lower Vf LEDs reduces the input power consumption by allowing the charge pump to operate at lower gain states. The equivalent circuit model for a charge pump is shown in Figure 43. VOUT is also equal to the largest Vf of the LEDs that are used plus the voltage drop across the regulating current source. This gives VOUT = Vf(MAX) + VDx Combining Equation 5 and Equation 6 gives VIN = (Vf(MAX) + VDx + IOUT × ROUT(G))/G Determining the Transition Point of the Charge Pump Consider the following design example where: Vf(MAX) = 3.7 V IOUT = 140 mA (7 LEDs at 20 mA each) ROUT (G = 1.5×) = 3 Ω (obtained from Figure 13) At the point of a gain transition, VDx = VHR(UP), Table 1 gives the typical value of VHR(UP) as 0.2 V. Therefore, the input voltage level when the gain transitions from 1.5× to 2× is VIN = (3.7 V + 0.2 V + 140 mA × 3 Ω)/1.5 = 2.88 V LAYOUT GUIDELINES • • • IOUT COUT VDX 07967-140 G × VIN • Figure 43. Charge Pump Equivalent Circuit Model • The input voltage is multiplied by the gain (G) and delivered to the output through an effective resistance (ROUT). The output current flows through ROUT and produces an IR drop to yield VOUT = G ×VIN − IOUT × ROUT(G) (5) The ROUT term is a combination of the RDSON resistance for the switches used in the charge pump and a small resistance that accounts for the effective dynamic charge pump resistance. The ROUT level changes based upon the gain (the configuration of the switches). Typical ROUT values are given in Table 1 and Figure 13 and Figure 14. (7) This equation is useful for calculating approximate bounds for the charge pump design. VOUT ROUT (6) • • Rev. 0 | Page 24 of 52 For optimal noise immunity, place the CIN and COUT capacitors as close as possible to their respective pins. These capacitors should share a short ground trace. If the LEDs are a significant distance from the VOUT pin, another capacitor on VOUT, placed closer to the LEDs, is advisable. For optimal efficiency, place the charge pump fly capacitors as close to the part as possible. The ADP8860 does not distinguish between power ground and analog ground. Therefore, both ground pins can be connected directly together. It is recommended that these ground pins be connected at the ground for the input and output capacitors. If using the LFCSP package, the exposed pad must be soldered at the board to the GND1 and/or GND2 pin(s). Unused diode pins (Pin D1 to Pin D7) can be connected to ground, VOUT, or remain floating. However, the unused diode current sinks must be disabled by setting them as independent sinks in Register 0x05 and then disabling them in Register 0x10. If they are not disabled, the charge pump efficiency may suffer. If the CMP_IN phototransistor input is not used, it can be connected to ground or remain floating. If the interrupt pin (nINT) is not used, connect it to ground or leave it floating. Never connect it to a voltage supply, except through a ≥1 kΩ series resistor. ADP8860 • bypass capacitor on this pin. If the nRST pin is not used, it must be pulled well above the VIH(MIN) level (see Table 1). Do not allow the nRST pin to float. The ADP8860 has an integrated noise filter on the nRST pin. Under normal conditions, it is not necessary to filter the reset line. However, if exposed to an unusually noisy signal, then it is beneficial to add a small RC filter or EXAMPLE CIRCUITS VALS OPTIONAL PHOTOSENSOR VOUT PHOTOSENSOR 0.1µF D1 D2 D3 VIN D3 E3 D4 E4 D5 D4 D6 C4 0.1µF D7 CMP_IN B4 B3 C3 A3 1µF nRST 1µF E1 VDDIO A1 ADP8860 SDA C1 C2 VDDIO B1 SCL E2 B2 VDDIO nINT VOUT A2 VDDIO C1+ C1– C1 1µF C2+ C2– C2 1µF A4 D1 GND1 07967-028 D2 GND2 Figure 44. Generic Application Schematic KEYPAD LIGHT UP TO 10 LEDs (6mA EACH) 60mA MAX TOTAL CURRENT DISPLAY BACKLIGHT DL1 DL2 DL3 DL4 DL8 DL17 R5 R6 R15 2.8V ACCESSORY LIGHTS OR SUB-DISPLAY BL PH2 PH1 OPTIONAL MAIN PHOTOSENSOR PHOTOSENSOR DL5 DL6 D3 E3 E4 D4 C4 D1 D2 D3 D4 D5 B4 B3 D6/ D7 CMP_IN2 C3 0.1µF 0.1µF CMP_IN A3 VIN VIN 1µF VDDIO R1 nRST DL7 R2 R3 R4 VOUT A2 A4 GND1 D1 GND2 1µF ADP8860 C1+ A1 E1 nRST C1 1µF C1– C1 C2 SDA C2+ B1 E2 SCL C2– B2 nINT D2 nINT Figure 45. Application Schematic with Keypad Light Control Rev. 0 | Page 25 of 52 C2 1µF 07967-029 I2C CONTROL SIGNALS ADP8860 I2C PROGRAMMING AND DIGITAL CONTROL The ADP8860 provides full software programmability to facilitate its adoption in various product architectures. The default I2C address is 0101010x (x = 0 during write, x = 1 during read). Therefore, the default write address is 0x54 and the read address is 0x55. Note the following general behavior of registers: • • • All registers are read/write unless otherwise specified. Unused bits are read as zero. The following tables provide register and bit descriptions. The reset value for all bits in the bit map tables is all 0s, except in Table 9 (see Table 9 for its unique reset value). Wherever the acronym N/A appears in the tables, it means not applicable. All registers are set to their default values during reset or after a UVLO event. 0 = WRITE 1 = READ ST SP 0 1 CHIP ADDRESS 0 R/W 0 0 REG ADDRESS 0 DATA 2 Figure 46. I C Command Sequence Table 7. Register Set Definitions Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F Register Name MFDVID MDCR MDCR2 INTR_EN CFGR BLSEN BLOFF BLDIM BLFR BLMX1 BLDM1 BLMX2 BLDM2 BLMX3 BLDM3 ISCFR ISCC ISCT1 ISCT2 ISCF ISC7 ISC6 ISC5 ISC4 ISC3 ISC2 ISC1 CCFG CCFG2 L2_TRP L2_HYS L3_TRP Description Manufacturer and device ID Device mode and status Device mode and Status Register 2 Interrupts enable Configuration register Sink enable backlight or independent Backlight off timeout Backlight dim timeout Backlight fade in and out rates Backlight (Brightness Level 1—daylight) maximum current Backlight (Brightness Level 1—daylight) dim current Backlight (Brightness Level 2—office) maximum current Backlight (Brightness Level 2—office) dim current Backlight (Brightness Level 3—dark) maximum current Backlight (Brightness Level 3—dark) dim current Independent sink current fade control register Independent sink current control register Independent Sink Current Timer Register LED[7:5] Independent Sink Current Timer Register LED[4:1] Independent sink current fade register Independent Sink Current LED7 Independent Sink Current LED6 Independent Sink Current LED5 Independent Sink Current LED4 Independent Sink Current LED3 Independent Sink Current LED2 Independent Sink Current LED1 Comparator configuration Second comparator configuration L2 comparator reference L2 hysteresis L3 comparator reference Rev. 0 | Page 26 of 52 07967-030 1 ACK 0 ACK 1 ACK 0 ADP8860 Address 0x20 0x21 0x22 0x23 0x24 Register Name L3_HYS PH1LEVL PH1LEVH PH2LEVL PH2LEVH Description L3 hysteresis First phototransistor ambient light level—low byte register First phototransistor ambient light level—high byte register Second phototransistor ambient light level—low byte register Second phototransistor ambient light level—high byte register Table 8. Register Map Addr 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 Reg. Name MFDVID MDCR MDCR2 INTR_EN CFGR BLSEN BLOFF BLDIM BLFR BLMX1 BLDM1 BLMX2 BLDM2 BLMX3 BLDM3 ISCFR ISCC ISCT1 ISCT2 ISCF ISC7 ISC6 ISC5 ISC4 ISC3 ISC2 ISC1 CCFG CCFG2 L2_TRP L2_HYS L3_TRP L3_HYS PH1LEVL PH1LEVH PH2LEVL PH2LEVH Bit 7 Reserved Reserved Reserved Reserved Reserved Bit 6 Bit 5 Manufacture ID INT_CFG NSTBY Reserved Reserved SEL_AB CMP2_SEL D7EN D6EN Bit 4 Bit 3 Bit 2 DIM_EN SHORT_INT SHORT_IEN Reserved TSD_INT TSD_IEN BLV D5EN D4EN OFFT DIMT Bit 1 Device ID SIS_EN CMP_AUTOEN OVP_INT CMP2_INT OVP_IEN CMP2_IEN Law D3EN D2EN BL_FO Bit 0 BLEN CMP_INT CMP_IEN FOVR D1EN BL_FI Reserved Reserved Reserved Reserved Reserved Reserved BL1_MC BL1_DC BL2_MC BL2_DC BL3_MC BL3_DC Reserved SC7_EN SCON SC4OFF SCR Reserved Reserved Reserved Reserved Reserved Reserved FILT FILT2 Reserved SC6_EN SC5_EN SC7OFF SC3OFF SCFO SC4_EN SC3_EN SC6OFF SC2OFF SCD7 SCD6 SCD5 SCD4 SCD3 SCD2 SCD1 FORCE_RD L3_OUT FORCE_RD2 L3_OUT2 L2_TRP L2_HYS L3_TRP L3_HYS PH1LEV_LOW Reserved SC_LAW SC2_EN SC1_EN SC5OFF SC1OFF SCFI L2_OUT L2_OUT2 PH1LEV_HIGH PH2LEV_LOW Reserved PH2LEV_HIGH Rev. 0 | Page 27 of 52 L3_EN L3_EN2 L2_EN L2_EN2 ADP8860 Manufacturer and Device ID (MFDVID)—Register 0x00 This is a read-only register. Table 9. MFDVID Manufacturer and Device ID Bit Map Bit 7 Bit 6 0 Bit 5 Manufacture ID 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 Device ID 1 Bit 0 1 1 Mode Control Register (MDCR)—Register 0x01 Table 10. MDCR Mode Control Bit Map Bit 7 Reserved Bit 6 INT_CFG Bit 5 nSTBY Bit 4 DIM_EN Bit 3 Reserved Bit 2 SIS_EN Bit 1 CMP_AUTOEN Bit 0 BL_EN Table 11. Bit Descriptions for the MDCR Register Bit Name N/A INT_CFG Bit No. 7 6 nSTBY 5 DIM_EN 4 N/A SIS_EN 3 2 CMP_AUTOEN 1 BL_EN 0 Description Reserved. Interrupt configuration. 1 = processor interrupt deasserts for 50 μs and reasserts with pending events. 0 = processor interrupt remains asserted if the host tries to clear the interrupt while there is a pending event. 1 = device is in active mode. 0 = device is in standby mode, only the I2C interface is enabled. DIM_EN is set by the hardware after a DIM timeout. The user may also force the backlight into DIM mode by asserting this bit. DIM mode can only be entered if BL_EN is also enabled. 1 = backlight is operating at the DIM current level (BL_EN must also be asserted). 0 = backlight is not in DIM mode. Reserved. Synchronous independent sinks enable. 1 = enables all LED current sinks designated as independent sinks. All of the ISC enable bits must be cleared; if any of the SC_EN bits in Register 0x10 are set, this bit has no effect. 0 = disables all sinks designated as independent sinks. All of the ISC enable bits must be cleared; if any of the SC_EN bits are set in Register 0x10, this bit has no effect. 1 = backlight automatically responds to the comparator outputs (L2_OUT and L3_OUT). L2_EN and/or L3_EN must be set for this to function. BLV values in Register 0x04 are overridden. 0 = backlight does not autorespond to comparator level changes. The user can manually select backlight operating levels using Bit BLV in Register 0x04. 1 = backlight is enabled (nSTBY must also be asserted). 0 = backlight is disabled. Rev. 0 | Page 28 of 52 ADP8860 Mode Control Register 2 (MDCR2)—Register 0x02 Table 12. MDCR2 Bit Map Bit 7 Bit 6 Reserved Bit 5 Bit 4 SHORT_INT Bit 3 TSD_INT Bit 2 OVP_INT Bit 1 CMP2_INT Bit 0 CMP_INT Table 13. Bit Descriptions for the MDCR2 Register Bit Name N/A SHORT_INT Bit No. 7:5 4 TSD_INT 3 OVP_INT 2 CMP2_INT 1 CMP_INT 0 1 Description 1 Reserved. Short-circuit error. 1 = a short-circuit or overload condition on VOUT was detected. 0 = no short-circuit or overload condition has been detected. Thermal shutdown. 1 = the device temperature has exceeded 150°C (typical). 0 = no overtemperature condition has been detected. Overvoltage interrupt. 1 = VOUT has exceeded VOVP. 0 = VOUT has not exceeded VOVP. 1 = indicates that the second ALS comparator (CMP_IN2) has changed state. 0 = the second sensor comparator has not triggered. 1 = indicates that the main ALS comparator (CMP_IN) has changed state. 0 = the main sensor comparator has not triggered. Interrupt bits are cleared by writing a 1 to the flag; writing a 0 or reading the flag has no effect. Interrupt Enable (INTR_EN)—Register 0x03 Table 14. INTR_EN Bit Map Bit 7 Bit 6 Reserved Bit 5 Bit 4 SHORT_IEN Bit 3 TSD_IEN Bit 2 OVP_IEN Bit 1 CMP2_IEN Bit 0 CMP_IEN Table 15. Bit Descriptions for the INTR_EN Register Bit Name N/A SHORT_IEN Bit No. 7:5 4 TSD_IEN 3 OVP_IEN 2 CMP2_IEN 1 Description Reserved. Short-circuit interrupt is enabled. When the SHORT_INT status bit is set after an error condition, an interrupt is raised to the host if the SHORT_IEN flag is enabled. 1 = the short-circuit interrupt is enabled. 0 = the short-circuit interrupt is disabled (the SHORT_INT flag continues to assert). Thermal shutdown interrupt is enabled. When the TSD_INT status bit is set after an error condition, an interrupt is raised to the host if the TSD_IEN flag is enabled. 1 = the thermal shutdown interrupt is enabled. 0 = the thermal shutdown interrupt is disabled (the TSD_INT flag continues to assert). Overvoltage interrupt enabled. When the OVP_INT status bit is set after an error condition, an interrupt is raised to the host if the OVP_IEN flag is enabled. 1 = the overvoltage interrupt is enabled. 0 = the overvoltage interrupt is disabled (the OVP_INT flag continues to assert). When the CMP2_INT status bit is set after an enabled comparator trips, an interrupt is raised if the CMP2_IEN flag is enabled. 1 = the second phototransistor comparator interrupt is enabled. 0 = the second phototransistor comparator interrupt is disabled (the CMP2_INT flag continues to assert). Rev. 0 | Page 29 of 52 ADP8860 Bit Name CMP_IEN Bit No. 0 Description When the CMP_INT status bit is set after an enabled comparator trips, an interrupt is raised if the CMP_IEN flag is enabled. 1 = the main comparator interrupt is enabled. 0 = the main comparator interrupt is disabled (the CMP_INT flag continues to assert). BACKLIGHT REGISTER DESCRIPTIONS Configuration Register (CFGR)—Register 0x04 Table 16. CFGR Bit Map Bit 7 Reserved Bit 6 SEL_AB Bit 5 CMP2_SEL Bit 4 Bit 3 BLV Bit 2 Bit 1 Law Bit 0 FOVR Table 17. Bit Descriptions for the CFGR Register Bit Name N/A SEL_AB Bit No. 7 6 CMP2_SEL 5 BLV 4:3 Law 2:1 FOVR 0 Description Reserved. 1 = selects the second phototransistor (CMP_IN2) to control the backlight. 0 = selects the main phototransistor (CMP_IN) to control the backlight. 1 = the second phototransistor is enabled; the current sink on D6 is disabled. 0 = the second phototransistor is disabled. Brightness level. This field indicates the brightness level at which the device is operating. The software may force the backlight to operate at one of the three brightness levels. Setting CMP_AUTOEN high (Register 0x01) sets these values automatically and overwrites any previously written values. 00 = Level 1 (daylight). 01 = Level 2 (office). 10 = Level 3 (dark). 11 = off (backlight set to 0 mA). Backlight transfer law. 00 = linear law DAC, linear time steps. 01 = square law DAC, linear time steps. 10 = square law DAC, nonlinear time steps (Cubic 10). 11 = square law DAC, nonlinear time steps (Cubic 11). Backlight fade override. 1 = the backlight fade override is enabled. 0 = the backlight fade override is disabled. Backlight Sink Enable (BLSEN)—Register 0x05 Table 18. BLSEN Bit Map Bit 7 Reserved Bit 6 D7EN Bit 5 D6EN Bit 4 D5EN Bit 3 D4EN Bit 2 D3EN Table 19. Bit Descriptions for the BLSEN Register Bit Name N/A D7EN Bit No. 7 6 D6EN 5 Description Reserved. Diode 7 backlight sink enable. 1 = selects LED7 as an independent sink. 0 = connects LED7 sink to backlight enable (BL_EN). Diode 6 backlight sink enable. 1 = selects LED6 as an independent sink. 0 = connects LED6 sink to backlight enable (BL_EN). Rev. 0 | Page 30 of 52 Bit 1 D2EN Bit 0 D1EN ADP8860 Bit Name D5EN Bit No. 4 D4EN 3 D3EN 2 D2EN 1 D1EN 0 Description Diode 5 backlight sink enable. 1 = selects LED5 as an independent sink. 0 = connects LED5 sink to backlight enable (BL_EN). Diode 4 backlight sink enable. 1 = selects LED4 as independent sink. 0 = connects LED4 sink to backlight enable (BL_EN). Diode 3 backlight sink enable. 1 = selects LED3 as independent sink. 0 = connects LED3 sink to backlight enable (BL_EN). Diode 2 backlight sink enable. 1 = selects LED2 as independent sink. 0 = connects LED2 sink to backlight enable (BL_EN). Diode 1 backlight sink enable. 1 = selects LED1 as independent sink. 0 = connects LED1 sink to backlight enable (BL_EN). Backlight Off Timeout (BLOFF)—Register 0x06 Table 20. BLOFF Bit Map Bit 7 Reserved Bit 6 Bit 5 Bit 4 Bit 3 OFFT Bit 2 Bit 1 Bit 0 Table 21. Bit Descriptions for the BLOFF Register Bit Name N/A OFFT Bit No. 7 6:0 Description Reserved. Backlight off timeout. After the off timeout (OFFT) period, the backlight turns off. If the dim timeout (DIMT) is enabled, the off timeout starts after the dim timeout. 0000 = timeout disabled 0000001 = 1 sec 0000010 = 2 sec 0000011 = 3 sec … 1111111 = 127 sec Backlight Dim Timeout (BLDIM)—Register 0x07 Table 22. BLDIM Bit Map Bit 7 Reserved Bit 6 Bit 5 Bit 4 Bit 3 DIMT Bit 2 Bit 1 Bit 0 Table 23. Bit Descriptions for the BLDIM Register Bit Name N/A DIMT Bit No. 7 6:0 Description Reserved. Backlight dim timeout. After the dim timeout (DIMT) period, the backlight is set to the dim current value. The dim timeout starts after backlight reaches the maximum current. 0000 = timeout disabled 0000001 = 1 sec 0000010 = 2 sec 0000011 = 3 sec … 1111111 = 127 sec Rev. 0 | Page 31 of 52 ADP8860 Backlight Fade (BLFR)—Register 0x08 Table 24. BLFR Backlight Fade Bit Map Bit 7 Bit 6 Bit 5 BL_FO Bit 4 Bit 3 Bit 2 Bit 1 BL_FI Bit 0 Table 25. Bit Descriptions for the BLFR Register Bit Name BL_FO Bit No. 7:4 BL_FI 3:0 1 Description Backlight fade out rate. If the fade out is disabled (BL_FO = 0000), the backlight changes instantly (within 100 ms). If the fade out rate is set, the backlight fades from its current value to the dim or the off value. The times listed for BL_FO are for a full-scale fade out (30 mA to 0 mA). Fades between closer current values reduce the fade time. See the Automated Fade In and Fade Out section for more information. 0000 = 0.1 sec (fade out disabled) 1 0001 = 0.3 sec 0010 = 0.6 sec 0011 = 0.9 sec 0100 = 1.2 sec 0101 = 1.5 sec 0110 = 1.8 sec 0111 = 2.1 sec 1000 = 2.4 sec 1001 = 2.7 sec 1010 = 3.0 sec 1011 = 3.5 sec 1100 = 4.0 sec 1101 = 4.5 sec 1110 = 5.0 sec 1111 = 5.5 sec Backlight fade in rate. If the fade in is disabled (BL_FI = 0000), the backlight changes instantly (within 100 ms). If the fade in rate is set, the backlight fades from its current value to its maximum when the backlight is turned on. The times listed for BL_FI are for a full-scale fade in (0 mA to 30 mA). Fades between closer current values reduce the fade time. See the Automated Fade In and Fade Out section for more information. 0000 = 0.1 sec (fade in disabled)1 0001 = 0.3 sec 0010 = 0.6 sec 0011 = 0.9 sec … 1111 = 5.5 sec When fade in and fade out are disabled, the backlight does not instantaneously fade, but instead, fades rapidly within about 100 ms. Rev. 0 | Page 32 of 52 ADP8860 Backlight Level 1 (Daylight) Maximum Current Register (BLMX1)—Register 0x09 Table 26. BLMX1 Bit Map Bit 7 Reserved Bit 6 Bit 5 Bit 4 Bit 3 BL1_MC Bit 2 Bit 1 Bit 0 Table 27. Bit Descriptions for the BLMX1 Register Bit Name N/A BL1_MC Bit No. 7 6:0 Description Reserved. Backlight maximum Level 1 (daylight) current. The backlight maximum current can be set according to the linear or square law function, as follows (see Table 28 for a complete list of values): DAC 0000000 0000001 0000010 0000011 … 1111111 Linear Law (mA) 0 0.236 0.472 0.708 … 30 Square Law (mA) 0 0.002 0.007 0.017 … 30 Table 28. Linear and Square Law Currents Per DAC Code DAC Code 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E Linear Law (mA) 0 0.236 0.472 0.709 0.945 1.181 1.417 1.654 1.890 2.126 2.362 2.598 2.835 3.071 3.307 3.543 3.780 4.016 4.252 4.488 4.724 4.961 5.197 5.433 5.669 5.906 6.142 6.378 6.614 6.850 7.087 Square Law 1 (mA) 0.000 0.002 0.007 0.017 0.030 0.047 0.067 0.091 0.119 0.151 0.186 0.225 0.268 0.314 0.365 0.419 0.476 0.538 0.603 0.671 0.744 0.820 0.900 0.984 1.071 1.163 1.257 1.356 1.458 1.564 1.674 DAC Code 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D Rev. 0 | Page 33 of 52 Linear Law (mA) 7.323 7.559 7.795 8.031 8.268 8.504 8.740 8.976 9.213 9.449 9.685 9.921 10.157 10.394 10.630 10.866 11.102 11.339 11.575 11.811 12.047 12.283 12.520 12.756 12.992 13.228 13.465 13.701 13.937 14.173 14.409 Square Law 1 (mA) 1.787 1.905 2.026 2.150 2.279 2.411 2.546 2.686 2.829 2.976 3.127 3.281 3.439 3.601 3.767 3.936 4.109 4.285 4.466 4.650 4.838 5.029 5.225 5.424 5.627 5.833 6.043 6.257 6.475 6.696 6.921 ADP8860 DAC Code 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E Linear Law (mA) 14.646 14.882 15.118 15.354 15.591 15.827 16.063 16.299 16.535 16.772 17.008 17.244 17.480 17.717 17.953 18.189 18.425 18.661 18.898 19.134 19.370 19.606 19.842 20.079 20.315 20.551 20.787 21.024 21.260 21.496 21.732 21.968 22.205 Square Law 1 (mA) 7.150 7.382 7.619 7.859 8.102 8.350 8.601 8.855 9.114 9.376 9.642 9.912 10.185 10.463 10.743 11.028 11.316 11.608 11.904 12.203 12.507 12.814 13.124 13.439 13.757 14.078 14.404 14.733 15.066 15.403 15.743 16.087 16.435 DAC Code 0x5F 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F 1 Linear Law (mA) 22.441 22.677 22.913 23.150 23.386 23.622 23.858 24.094 24.331 24.567 24.803 25.039 25.276 25.512 25.748 25.984 26.220 26.457 26.693 26.929 27.165 27.402 27.638 27.874 28.110 28.346 28.583 28.819 29.055 29.291 29.528 29.764 30.000 Square Law 1 (mA) 16.787 17.142 17.501 17.863 18.230 18.600 18.974 19.351 19.733 20.118 20.507 20.899 21.295 21.695 22.099 22.506 22.917 23.332 23.750 24.173 24.599 25.028 25.462 25.899 26.340 26.784 27.232 27.684 28.140 28.599 29.063 29.529 30.000 Cubic 10 and Cubic 11 laws use the square law DAC setting but vary the time step per DAC code (see Figure 31). Rev. 0 | Page 34 of 52 ADP8860 Backlight Level 1 (Daylight) Dim Current Register (BLDM1)—Register 0x0A Table 29. BLDM1 Bit Map Bit 7 Reserved Bit 6 Bit 5 Bit 4 Bit 3 BL1_DC Bit 2 Bit 1 Bit 0 Table 30. Bit Descriptions for the BLDM1 Register Bit Name N/A BL1_DC Bit No. 7 6:0 Description Reserved. Backlight Level 1 (daylight) dim current. The backlight is set to the dim current value after a dim timeout or if the DIM_EN flag is set by the user (see Table 28 for a complete list of values). DAC 0000000 0000001 0000010 0000011 … 1111111 Linear Law (mA) 0 0.236 0.472 0.709 … 30 Square Law (mA) 0 0.002 0.007 0.017 … 30 Backlight Level 2 (Office) Maximum Current Register (BLMX2)—Register 0x0B Table 31. BLMX2 Bit Map Bit 7 Reserved Bit 6 Bit 5 Bit 4 Bit 3 BL2_MC Bit 2 Bit 1 Table 32. Bit Descriptions for the BLMX2 Register Bit Name N/A BL2_MC Bit No. 7 6:0 Description Reserved. Backlight Level 2 (office) maximum current (see Table 28 for a complete list of values). DAC 0000000 0000001 0000010 0000011 … 1111111 Linear Law (mA) 0 0.236 0.472 0.709 … 30 Square Law (mA) 0 0.002 0.007 0.017 … 30 Rev. 0 | Page 35 of 52 Bit 0 ADP8860 Backlight Level 2 (Office) Dim Current Register (BLDM2)—Register 0x0C Table 33. BLDM2 Bit Map Bit 7 Reserved Bit 6 Bit 5 Bit 4 Bit 3 BL2_DC Bit 2 Bit 1 Bit 0 Table 34. Bit Descriptions for the BLDM2 Register Bit Name N/A BL2_DC Bit No. 7 6:0 Description Reserved. Backlight Level 2 (office) dim current. See Table 28 for a complete list of values. The backlight is set to the dim current value after a dim timeout or if the DIM_EN flag is set by the user. DAC 0000000 0000001 0000010 0000011 … 1111111 Linear Law (mA) 0 0.236 0.472 0.709 … 30 Square Law (mA) 0 0.002 0.007 0.017 … 30 Backlight Level 3 (Dark) Maximum Current Register (BLMX3)—Register 0x0D Table 35. BLMX3 Bit Map Bit 7 Reserved Bit 6 Bit 5 Bit 4 Bit 3 BL3_MC Bit 2 Bit 1 Table 36. Bit Descriptions for the BLMX3 Register Bit Name N/A BL3_MC Bit No. 7 6:0 Description Reserved. Backlight Level 3 (dark) maximum current. See Table 28 for a complete list of values. DAC 0000000 0000001 0000010 0000011 … 1111111 Linear Law (mA) 0 0.236 0.472 0.709 … 30 Square Law (mA) 0 0.002 0.007 0.017 … 30 Rev. 0 | Page 36 of 52 Bit 0 ADP8860 Backlight Level 3 (Dark) Dim Current Register (BLDM3)—Register 0x0E Table 37. BLDM3 Bit Map Bit 7 Reserved Bit 6 Bit 5 Bit 4 Bit 3 BL3_DC Bit 2 Bit 1 Bit 0 Table 38. Bit Descriptions for the BLDM3 Register Bit Name N/A BL3_DC Bit No. 7 6:0 Description Reserved. Backlight Level 3 (dark) dim current. See Table 28 for a complete list of values. The backlight is set to the dim current value after a dim timeout or if the DIM_EN flag is set by the user. DAC 0000000 0000001 0000010 0000011 … 1111111 Linear Law (mA) 0 0.236 0.472 0.709 … 30 Square Law (mA) 0 0.002 0.007 0.017 … 30 INDEPENDENT SINK REGISTER DESCRIPTIONS Independent Sink Current Fade Control Register (ISCFR)—Register 0x0F Table 39. ISCFR Bit Map Bit 7 Bit 6 Bit 5 Bit 4 Reserved Bit 3 Bit 2 Bit 1 Bit 0 SC_LAW Table 40. Bit Descriptions for the ISCFR Bit Name N/A SC_LAW Bit No. 7:2 1:0 Description Reserved. Independent sink current fade transfer law. 00 = linear law DAC, linear time steps. 01 = square law DAC, linear time steps. 10 = square law DAC, nonlinear time steps (Cubic 10). 11 = square law DAC, nonlinear time steps (Cubic 11). Independent Sink Current Control (ISCC)—Register 0x10 Table 41. ISCC Bit Map Bit 7 Reserved Bit 6 SC7_EN Bit 5 SC6_EN Bit 4 SC5_EN Bit 3 SC4_EN Table 42. Bit Descriptions for the ISCC Register Bit Name N/A SC7_EN Bit No. 7 6 SC6_EN 5 SC5_EN 4 Description Reserved. This enable acts upon the LED7. 1 = SC7 is turned on. 0 = SC7 is turned off. This enable acts upon the LED6. 1 = SC6 is turned on. 0 = SC6 is turned off. This enable acts upon the LED5. 1 = SC5 is turned on. 0 = SC5 is turned off. Rev. 0 | Page 37 of 52 Bit 2 SC3_EN Bit 1 SC2_EN Bit 0 SC1_EN ADP8860 Bit Name SC4_EN Bit No. 3 Description This enable acts upon the LED4. 1 = SC4 is turned on. 0 = SC4 is turned off. SC3_EN 2 SC2_EN 1 SC1_EN 0 This enable acts upon the LED3. 1 = SC3 is turned on. 0 = SC3 is turned off. This enable acts upon the LED2. 1 = SC2 is turned on. 0 = SC2 is turned off. This enable acts upon the LED1. 1 = SC1 is turned on. 0 = SC1 is turned off. Independent Sink Current Time (ISCT1)—Register 0x11 Table 43. ISCT1 Bit Map Bit 7 Bit 6 SCON Bit 5 Bit 4 SC7OFF Bit 3 Bit 2 SC6OFF Bit 1 Bit 0 SC5OFF Table 44. Bit Descriptions for the ISCT1 Register Bit Name SCON Bit No. 7:6 Description 1, 2 SC on time. If the SCxOFF time is not disabled, then when the independent current sink is enabled (Register 0x10) it remains on for the on time selected (per the following list) and then turns off. 00 = 0.2 sec. 01 = 0.6 sec. 10 = 0.8 sec. 11 = 1.2 sec. SC7OFF 5:4 SC6OFF 3:2 SC5OFF 1:0 1 2 SC7 off time. When the SC off time is disabled, the ISC remains on while enabled. When the SC off time is set to any other value, the ISC turns off for the off time (per the following listed times) and then turns on according to the SCON setting. 00 = off time disabled. 01 = 0.6 sec. 10 = 1.2 sec. 11 = 1.8 sec. SC6 off time. When the SC off time is disabled, the ISC remains on while enabled. When the SC off time is set to any other value, the ISC turns off for the off time (per the following listed times) and then turns on according to the SCON setting. 00 = off time disabled. 01 = 0.6 sec. 10 = 1.2 sec. 11 = 1.8 sec. SC5 off time. When the SC off time is disabled, the ISC remains on while enabled. When the SC off time is set to any other value, the ISC turns off for the off time (per the following listed times) and then turns on according to the SCON setting. 00 = off time disabled. 01 = 0.6 sec. 10 = 1.2 sec. 11 = 1.8 sec. An independent sink remains on continuously when SCx_EN = 1 and SCx_OFF is 00 (disabled). To enable multiple independent sinks, set the appropriate SCx_EN bits. To create equivalent blinking and fading sequences, enable all independent sinks in one write cycle to cause a preprogrammed sequence to start simultaneously. Rev. 0 | Page 38 of 52 ADP8860 Independent Sink Current Time (ISCT2)—Register 0x12 Table 45. ISCT2 Bit Map Bit 7 Bit 6 SC4OFF Bit 5 Bit 4 SC3OFF Bit 3 Bit 2 SC2OFF Bit 1 Bit 0 SC1OFF Table 46. Bit Descriptions for the ISCT2 Register Designation SC4OFF Bit 7:6 SC3OFF 5:4 SC2OFF 3:2 SC1OFF 1:0 1 2 Description 1, 2 SC4 off time. When the SC off time is disabled, the ISC remains on while enabled. When the SC off time is set to any other value, then the ISC turns off for the off time (per the following listed times) and then turns on according to the SCON setting. 00 = off time disabled. 01 = 0. 6 sec. 10 = 1.2 sec. 11 = 1.8 sec. SC3 off time. When the SC off time is disabled, the ISC remains on while enabled. When the SC off time is set to any other value, then the ISC turns off for the off time (per the following listed times) and then turns on according to the SCON setting. 00 = off time disabled. 01 = 0. 6 sec. 10 = 1.2 sec. 11 = 1.8 sec. SC2 off time. When the SC off time is disabled, the ISC remains on while enabled. When the SC off time is set to any other value, then the ISC turns off for the off time (per the following listed times) and then turns on according to the SCON setting. 00 = off time disabled. 01 = 0. 6 sec. 10 = 1.2 sec. 11 = 1.8 sec. SC1 off time. When the SC off time is disabled, the ISC remains on while enabled. When the SC off time is set to any other value, then the ISC turns off for the off time (per the following listed times) and then turns on according to the SCON setting. 00 = off time disabled. 01 = 0. 6 sec. 10 = 1.2 sec. 11 = 1.8 sec. An independent sink remains on continuously when SCx_EN = 1 and SCx_OFF is 00 (disabled). To enable multiple independent sinks, set the appropriate SCx_EN bits. To create equivalent blinking and fading sequences, enable all independent sinks in one write cycle. This causes a preprogrammed sequence to start simultaneously. Rev. 0 | Page 39 of 52 ADP8860 Independent Sink Current Fade (ISCF)—Register 0x13 Table 47. ISCF Bit Map Bit 7 Bit 6 Bit 5 SCFO Bit 4 Bit 3 Bit 2 Bit 1 SCFI Bit 0 Table 48. Bit Descriptions for the ISCF Register Bit Name SCFO Bit No. 7:4 SCFI 3:0 Description Sink current fade out rate. The following times listed are for a full-scale fade out (30 mA to 0 mA). Fades between closer current values reduce the fade time. See the Automated Fade In and Fade Out section for more information. 0000 = disabled. 0001 = 0.30 sec. 0010 = 0.60 sec. 0011 = 0.90 sec. 0100 = 1.2 sec. 0101 = 1.5 sec. 0110 = 1.8 sec. 0111 = 2.1 sec. 1000 = 2.4 sec. 1001 = 2.7 sec. 1010 = 3.0 sec. 1011 = 3.5 sec. 1100 = 4.0 sec. 1101 = 4.5 sec. 1110 = 5.0 sec. 1111 = 5.5 sec. Sink current fade in rate. The following times listed are for a full-scale fade in (0 mA to 30 mA). Fades between closer current values reduce the fade time. See the Automated Fade In and Fade Out section for more information. 0000 = disabled. 0001 = 0.30 sec. 0010 = 0.60 sec. 0011 = 0.90 sec. 0100 = 1.2 sec. 0101 = 1.5 sec. 0110 = 1.8 sec. 0111 = 2.1 sec. 1000 = 2.4 sec. 1001 = 2.7 sec. 1010 = 3.0 sec. 1011 = 3.5 sec. 1100 = 4.0 sec. 1101 = 4.5 sec. 1110 = 5.0 sec. 1111 = 5.5 sec. Rev. 0 | Page 40 of 52 ADP8860 Sink Current Register LED7 (ISC7)—Register 0x14 Table 49. ISC7 Bit Map Bit 7 SCR Bit 6 Bit 5 Bit 4 Bit 3 SCD7 Bit 2 Bit 1 Bit 0 Table 50. Bit Descriptions for the ISC7 Register Bit Name SCR Bit No. 7 SCD7 6:0 Description 1 = Sink Current 1. 0 = Sink Current 0. For the lowest input current consumption and optimal efficiency, set SCR to 0 when D7 is set to ISC in Register 0x05 and SC7_EN = 0. For Sink Current 0, use the following DAC code schedule (see Table 28 for a complete list of values): DAC Linear Law (mA) Square Law (mA) 0000000 0 0 0000001 0.236 0.002 0000010 0.472 0.007 0000011 0.709 0.017 … … … 1111111 30 30 For Sink Current 1, use the following DAC code schedule (see Table 51 for a complete list of values): DAC 0000000 Linear Law (mA) 0 Square Law (mA) 0 0000001 0.472 0.004 0000010 0.945 0.014 0000011 01.417 0.034 … … … 1111111 60 60 Table 51. Linear and Square Law Currents for LED7 (SCR = 1) DAC Code 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 Linear Law (mA) 0.000 0.472 0.945 1.42 1.89 2.36 2.83 3.31 3.78 4.25 4.72 5.20 5.67 6.14 6.61 7.09 7.56 8.03 8.50 8.98 Square Law1 (mA) 0 0.004 0.014 0.034 0.06 0.094 0.134 0.182 0.238 0.302 0.372 0.45 0.536 0.628 0.73 0.838 0.952 1.076 1.206 1.342 DAC Code 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 Rev. 0 | Page 41 of 52 Linear Law (mA) 9.45 9.92 10.39 10.87 11.34 11.81 12.28 12.76 13.23 13.70 14.17 14.65 15.12 15.59 16.06 16.54 17.01 17.48 17.95 18.43 Square Law1 (mA) 1.488 1.64 1.8 1.968 2.142 2.326 2.514 2.712 2.916 3.128 3.348 3.574 3.81 4.052 4.3 4.558 4.822 5.092 5.372 5.658 ADP8860 DAC Code 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 Linear Law (mA) 18.90 19.37 19.84 20.31 20.79 21.26 21.73 22.20 22.68 23.15 23.62 24.09 24.57 25.04 25.51 25.98 26.46 26.93 27.40 27.87 28.35 28.82 29.29 29.76 30.24 30.71 31.18 31.65 32.13 32.60 33.07 33.54 34.02 34.49 34.96 35.43 35.91 36.38 36.85 37.32 37.80 38.27 38.74 39.21 Square Law 1 (mA) 5.952 6.254 6.562 6.878 7.202 7.534 7.872 8.218 8.57 8.932 9.3 9.676 10.058 10.45 10.848 11.254 11.666 12.086 12.514 12.95 13.392 13.842 14.3 14.764 15.238 15.718 16.204 16.7 17.202 17.71 18.228 18.752 19.284 19.824 20.37 20.926 21.486 22.056 22.632 23.216 23.808 24.406 25.014 25.628 DAC Code 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F 1 Linear Law (mA) 39.69 40.16 40.63 41.10 41.57 42.05 42.52 42.99 43.46 43.94 44.41 44.88 45.35 45.83 46.30 46.77 47.24 47.72 48.19 48.66 49.13 49.61 50.08 50.55 51.02 51.50 51.97 52.44 52.91 53.39 53.86 54.33 54.80 55.28 55.75 56.22 56.69 57.17 57.64 58.11 58.58 59.06 59.53 60 Square Law 1 (mA) 26.248 26.878 27.514 28.156 28.808 29.466 30.132 30.806 31.486 32.174 32.87 33.574 34.284 35.002 35.726 36.46 37.2 37.948 38.702 39.466 40.236 41.014 41.798 42.59 43.39 44.198 45.012 45.834 46.664 47.5 48.346 49.198 50.056 50.924 51.798 52.68 53.568 54.464 55.368 56.28 57.198 58.126 59.058 60 Cubic 10 and Cubic 11 laws use the square law DAC setting but vary the time step per DAC code (see Figure 31). Rev. 0 | Page 42 of 52 ADP8860 Sink Current Register LED6 (ISC6)—Register 0x15 Table 52. ISC6 Bit Map Bit 7 Reserved Bit 6 Bit 5 Bit 4 Bit 3 SCD6 Bit 2 Bit 1 Bit 0 Table 53. Bit Descriptions for the ISC6 Register Bit Name N/A SCD6 Bit No. 7 6:0 Description Reserved. Sink current. Use the following DAC code schedule (see Table 28 for a complete list of values): DAC 0000000 0000001 0000010 0000011 … 1111111 Linear Law (mA) 0 0.236 0.472 0.709 … 30 Square Law (mA) 0 0.002 0.007 0.017 … 30 Sink Current Register LED5 (ISC5)—Register 0x16 Table 54. ISC5 Bit Map Bit 7 Reserved Bit 6 Bit 5 Bit 4 Bit 3 SCD5 Bit 2 Bit 1 Bit 0 Table 55. Bit Descriptions for the ISC5 Register Bit Name N/A SCD5 Bit No. 7 6:0 Description Reserved. Sink current. Use the following DAC code schedule (see Table 28 for a complete list of values): DAC 0000000 0000001 0000010 0000011 … 1111111 Linear Law (mA) 0 0.236 0.472 0.709 … 30 Square Law (mA) 0 0.002 0.007 0.017 … 30 Sink Current Register LED4 (ISC4)—Register 0x17 Table 56. ISC4 Bit Map Bit 7 Reserved Bit 6 Bit 5 Bit 4 Bit 3 SCD4 Bit 2 Bit 1 Table 57. Bit Descriptions for the ISC4 Register Bit Name N/A SCD4 Bit No. 7 6:0 Description Reserved. Sink current. Use the following DAC code schedule (see Table 28 for a complete list of values): DAC 0000000 0000001 0000010 0000011 … 1111111 Linear Law (mA) 0 0.236 0.472 0.709 … 30 Square Law (mA) 0 0.002 0.007 0.017 … 30 Rev. 0 | Page 43 of 52 Bit 0 ADP8860 Sink Current Register LED3 (ISC3)—Register 0x18 Table 58. ISC3 Bit Map Bit 7 Reserved Bit 6 Bit 5 Bit 4 Bit 3 SCD3 Bit 2 Bit 1 Bit 0 Table 59. Bit Descriptions for the ISC3 Register Bit Name N/A SCD3 Bit No. 7 6:0 Description Reserved. Sink current. Use the following DAC code schedule (see Table 28 for a complete list of values): DAC 0000000 0000001 0000010 0000011 … 1111111 Linear Law (mA) 0 0.236 0.472 0.709 … 30 Square Law (mA) 0 0.002 0.007 0.017 … 30 Sink Current Register LED2 (ISC2)—Register 0x19 Table 60. ISC2 Bit Map Bit 7 Reserved Bit 6 Bit 5 Bit 4 Bit 3 SCD2 Bit 2 Bit 1 Bit 0 Table 61. Bit Descriptions for the ISC2 Register Bit Name N/A SCD2 Bit No. 7 6:0 Description Reserved. Sink current. Use the following DAC code schedule (see Table 28 for a complete list of values): DAC 0000000 0000001 0000010 0000011 … 1111111 Linear Law (mA) 0 0.236 0.472 0.709 … 30 Square Law (mA) 0 0.002 0.007 0.017 … 30 Sink Current Register LED1 (ISC1)—Register 0x1A Table 62. ISC1 Bit Map Bit 7 Reserved Bit 6 Bit 5 Bit 4 Bit 3 SCD1 Bit 2 Bit 1 Table 63. Bit Descriptions for the ISC1 Register Bit Name N/A SCD1 Bit No. 7 6:0 Description Reserved Sink current. Use the following DAC code schedule (see Table 28 for a complete list of values): DAC 0000000 0000001 0000010 0000011 … 1111111 Linear Law (mA) 0 0.236 0.472 0.709 … 30 Square Law (mA) 0 0.002 0.007 0.017 … 30 Rev. 0 | Page 44 of 52 Bit 0 ADP8860 COMPARATOR REGISTER DESCRIPTIONS Comparator Configuration (CCFG)—Register 0x1B Table 64. CCFG Bit Map Bit 7 Bit 6 FILT Bit 5 Bit 4 FORCE_RD Bit 3 L3_OUT Bit 2 L2_OUT Bit 1 L3_EN Bit 0 L2_EN Table 65. Bit Descriptions for the CCFG Register Bit Name FILT Bit No. 7:5 Description Filter setting for the CMP_IN light sensor. 000 = 80 ms. 001 = 160 ms. 010 = 320 ms. 011 = 640 ms. 100 = 1280 ms. 101 = 2560 ms. 110 = 5120 ms. 111= 10,240 ms. FORCE_RD 4 L3_OUT L2_OUT L3_EN 3 2 1 L2_EN 0 Force a read of the CMP_IN light sensor while independent sinks are running, but the backlight is not. Reset by chip after the conversion is complete and L2_OUT and L3_OUT are valid. Ignored if the backlight is enabled. This bit is the output of the L3 comparator. This bit is the output of the L2 comparator. 1 = the L3 comparator is enabled for the CMP_IN comparator. 0 = the L3 comparator is disabled for the CMP_IN comparator. Note that the L3 comparator has priority over L2. 1 = the L2 comparator is enabled for the CMP_IN comparator. 0 = the L2 comparator is disabled for the CMP_IN comparator. Second Comparator Configuration (CCFG2)—Register 0x1C Table 66. CCFG2 Bit Map Bit 7 Bit 6 FILT2 Bit 5 Bit 4 FORCE_RD2 Bit 3 L3_OUT2 Bit 2 L2_OUT2 Bit 1 L3_EN2 Bit 0 L2_EN2 Table 67. Bit Descriptions for the CCFG2 Register Bit Name FILT2 Bit No. 7:5 Description Filter setting for the CMP_IN2 light sensor. 000 = 80 ms. 001 = 160 ms. 010 = 320 ms. 011 = 640 ms. 100 = 1280 ms. 101 = 2560 ms. 110 = 5120 ms. 111= 10,240 ms. FORCE_RD2 4 L3_OUT2 L2_OUT2 L3_EN2 3 2 1 Force a read of the CMP_IN2 light sensor while independent sinks are running, but the backlight is not. Reset by chip after the conversion is complete and L2_OUT and L3_OUT are valid. Ignored if the backlight is enabled. This bit is the output of the L3 comparator for the second light sensor. This bit is the output of the L2 comparator for the second light sensor. 1 = the L3 comparator is enabled for the CMP_IN2 comparator. 0 = the L3 comparator is disabled for the CMP_IN2 comparator. Rev. 0 | Page 45 of 52 ADP8860 Bit Name L2_EN2 Bit No. 0 Description Note that the L3 comparator has priority over L2. 1 = the L2 comparator is enabled for the CMP_IN2 comparator. 0 = the L2 comparator is disabled for the CMP_IN2 comparator. Comparator Level 2 Threshold (L2_TRP)—Register 0x1D Table 68. L2_TRP Bit Map Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 L2_TRP Bit 2 Bit 1 Bit 0 Table 69. Bit Descriptions for the L2_TRP Register Bit Name L2_TRP Bit No. 7:0 Description Comparator Level 2 threshold. If the comparator input is below L2_TRP, then the comparator trips and the backlight enters Level 2 (office) mode. The following lists the code settings for photosensor current: 00000000 = 0 μA. 00000001 = 4.3 μA. 00000010 = 8.6 μA. 00000011 = 12.9 μA. … 11111010 = 1080 μA. … 11111111 = 1106 μA. Although codes above 1111010 (250) are possible, they should not be used. Furthermore, the maximum value of L2_TRP + L2_HYS must not exceed 1111010 (250). Comparator Level 2 Hysteresis (L2_HYS)—Register 0x1E Table 70. L2_HYS Bit Map Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 L2_HYS Bit 2 Bit 1 Bit 0 Table 71. Bit Descriptions for the L2_HYS Register Bit Name L2_HYS Bit No. 7:0 Description Comparator Level 2 hysteresis. If the comparator input is above L2_TRP + L2_HYS, the comparator trips and the backlight enters Level 1 (daylight) mode. The following lists the code settings for photosensor current hysteresis: 0000000 = 0 μA. 00000001 = 4.3 μA. 00000010 = 8.6 μA. 00000011 = 12.9 μA. … 11111010 = 1080 μA. … 11111111 = 1106 μA. Although codes above 1111010 (250) are possible, they should not be used. Furthermore, the maximum value of L2_TRP + L2_HYS must not exceed 1111010 (250). Rev. 0 | Page 46 of 52 ADP8860 Comparator Level 3 Threshold (L3_TRP)—Register 0x1F Table 72. L3_TRP Bit Map Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 L3_TRP Bit 2 Bit 1 Bit 0 Table 73. Bit Descriptions for the L3_TRP Register Bit Name L3_TRP Bit No. 7:0 Description Comparator Level 3 threshold. If the comparator input is below L3_TRP, the comparator trips and the backlight enters Level 3 (dark) mode. The following lists the code settings for photosensor current: 0000000 = 0 μA. 0000001 = 0.54 μA. 0000010 = 1.08 μA. 0000011 = 1.62 μA. … 1111111 = 137.7 μA. Comparator Level 3 Hysteresis (L3_HYS)—Register 0x20 Table 74. L3_HYS Comparator Level 3 Hysteresis Bit Map Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 L3_HYS Bit 2 Bit 1 Bit 0 Table 75. Bit Descriptions for the L3_HYS Register Bit Name L3_HYS Bit No. 7:0 Description Comparator Level 3 hysteresis. If the comparator input is above L3_TRP + L3_HYS, the comparator trips and the backlight enters Level 2 (office) mode. The following lists the code settings for photosensor current hysteresis: 0000000 = 0 μA. 0000001 = 0.54 μA. 0000010 = 1.08 μA. 0000011 = 1.62 μA. … 1111111 = 137.7 μA. First Phototransistor Register: Low Byte (PH1LEVL)—Register 0x21 Table 76. PH1LEVL Bit Map Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 PH1LEV_LOW Bit 2 Bit 1 Bit 0 Table 77. Bit Descriptions for the PH1LEVL Register Bit Name PH1LEV_LOW Bit No. 7:0 Description 13-bit conversion value for the first light sensor—low byte (Bit 7 to Bit 0). The value is updated every 80 ms (when the light sensor is enabled). This is a read-only register. Rev. 0 | Page 47 of 52 ADP8860 First Phototransistor Register: High Byte (PH1LEVH)—Register 0x22 Table 78. PH1LEVH Bit Map Bit 7 Bit 6 Reserved Bit 5 Bit 4 Bit 3 Bit 2 PH1LEV_HIGH Bit 1 Bit 0 Table 79. Bit Descriptions for the PH1LEVH Register Bit Name N/A PH1LEV_HIGH Bit No. 7:5 4:0 Description Reserved. 13-bit conversion value for the first light sensor—high byte (Bit 12 to Bit 8). The value is updated every 80 ms (when the light sensor is enabled). This is a read-only register. Second Phototransistor Register: Low Byte (PH2LEVL)—Register 0x23 Table 80. PH2LEVL Bit Map Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 PH2LEV_LOW Bit 2 Bit 1 Bit 0 Table 81. Bit Descriptions for the PH2LEVL Register Bit Name PH2LEV_LOW Bit No. 7:0 Description 13-bit conversion value for the second light sensor—low byte (Bit 7 to Bit 0) The value is updated every 80 ms (when the light sensor is enabled). This is a read-only register. Second Phototransistor Register: High Byte (PH2LEVH)—Register 0x24 Table 82. PH2LEVH Bit Map Bit 7 Bit 6 Reserved Bit 5 Bit 4 Bit 3 Bit 2 PH2LEV_HIGH Bit 1 Bit 0 Table 83. Bit Descriptions for the PH2LEVH Register Bit Name N/A Bit No. 7:5 Description Reserved. PH2LEV_HIGH 4:0 13-bit conversion value for the second light sensor—high byte (Bit 12 to Bit 8). The value is updated every 80 ms (when the light sensor is enabled). This is a read-only register. Rev. 0 | Page 48 of 52 ADP8860 OUTLINE DIMENSIONS 0.645 0.600 0.555 1.995 1.955 1.915 3 4 SEATING PLANE 2 1 A BALL A1 IDENTIFIER B 2.395 2.355 2.315 1.60 REF 0.287 0.267 0.247 C D E 0.40 REF BOTTOM VIEW 0.05 MAX COPLANARITY 0.415 0.400 0.385 (BALL SIDE UP) 0.230 0.200 0.170 021009-A TOP VIEW (BALL SIDE DOWN) Figure 47. 20-Ball Wafer Level Chip Scale Package [WLCSP] (CB-20-6) Dimensions shown in millimeters 0.60 MAX 4.00 BSC SQ 0.60 MAX 15 PIN 1 INDICATOR 20 16 1 PIN 1 INDICATOR 3.75 BSC SQ 0.50 BSC 2.65 2.50 SQ 2.35 EXPOSED PAD (BOTTOM VIEW) 5 1.00 0.85 0.80 SEATING PLANE 12° MAX 0.80 MAX 0.65 TYP 0.30 0.23 0.18 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 11 10 6 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1 Figure 48. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-20-4) Dimensions shown in millimeters Rev. 0 | Page 49 of 52 090408-B TOP VIEW 0.50 0.40 0.30 ADP8860 ORDERING GUIDE Model ADP8860ACBZ-R7 1 ADP8860ACPZ-R71 Package Description 20-Ball WLCSP, Tape and Reel 20-Lead LFCSP_VQ, Tape and Reel Z = RoHS Compliant Part. 07967-033 Figure 49. Tape and Reel Orientation for WLCSP Units 07967-034 1 Temperature Range −40°C to +85°C −40°C to +85°C Figure 50. Tape and Reel Orientation for LFCSP Units Rev. 0 | Page 50 of 52 Package Option CB-20-6 CP-20-4 ADP8860 NOTES Rev. 0 | Page 51 of 52 ADP8860 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07967-0-5/09(0) Rev. 0 | Page 52 of 52