PRELIMINARY TECHNICAL DATA 8-Bit, 165 MSPS TxDAC® D/A Converter a Preliminary Technical Data FEATURES High-Performance Member of Pin-Compatible TxDAC Product Family Excellent Spurious-Free Dynamic Range and Noise Performance Two’s Complement or Straight Binary Data Format Differential Current Outputs: 2 mA to 20 mA Power Dissipation: 135 mW @ 3.3 V Power-Down Mode: 15 mW @ 3.3 V On-Chip 1.20 V Reference CMOS-Compatible Digital Interface Package: 32-Lead Leadframe Chip Scale Package (LFCSP) Edge-Triggered Latches APPLICATIONS Wideband Communication Transmit Channel: Direct IF Base Stations Wireless Local Loop Digital Radio Link Direct Digital Synthesis (DDS) Instrumentation PRODUCT DESCRIPTION The AD9748 is a 8-bit resolution, wideband, third generation member of the TxDAC series of high-performance, low power CMOS digital-to-analog converters (DACs). The TxDAC family, consisting of pin-compatible 8-, 10-, 12-, and 14-bit DACs, is specifically optimized for the transmit signal path of communication systems. All of the devices share the same interface options, small outline package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost. The AD9748 offers exceptional ac and dc performance while supporting update rates up to 165 MSPS. The AD9748’s low power dissipation makes it well suited for portable and low power applications. Its power dissipation can be further reduced to a mere 60 mW with a slight degradation in performance by lowering the full-scale current output. Also, a power-down mode reduces the standby power dissipation to approximately 15 mW. A segmented current source architecture is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance. Edgetriggered input latches and a 1.2 V temperature compensated TxDAC is a registered trademark of Analog Devices, Inc. *Protected by U.S. Patent Numbers 5568145, 5689257, and 5703519. AD9748* FUNCTIONAL BLOCK DIAGRAM 3.3V AVDD 150pF 0.1F RSET 3.3V ACOM +1.20V REF REFIO FS ADJ DVDD DCOM CURRENT SOURCE ARRAY SEGMENTED SWITCHES CLK+ CLK- AD9748 LSB SWITCHES LATCHES 3.3V IOUTA IOUTB MODE1 MODE2 CLKVDD CLKCOM DIGITAL DATA INPUTS (DB7-DB0) SLEEP band gap reference have been integrated to provide a complete monolithic DAC solution. The digital inputs support 3 V CMOS logic families. PRODUCT HIGHLIGHTS 1. New 32-lead LFCSP package. 2. The AD9748 is the 8-bit member of the pin-compatible TxDAC family that offers excellent INL and DNL performance. 3. Differential or single-ended clock input (LVPECL or CMOS). 4. Data input supports two’s complement or straight binary data coding. 5. High-speed, single-ended CMOS clock input supports 165 MSPS conversion rate. 6. Low power: Complete CMOS DAC function operates on 135 mW from a 3.0 V to 3.6 V single supply. The DAC full-scale current can be reduced for lower power operation, and a sleep mode is provided for low power idle periods. 7. On-chip voltage reference: The AD9748 includes a 1.2 V temperature-compensated band gap voltage reference. REV. PrA Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 PRELIMINARY TECHNICAL DATA AD9748-SPECIFICATIONS DC SPECIFICATIONS (TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.) Parameter Min RESOLUTION 8 DC ACCURACY1 Integral Linearity Error (INL) Differential Nonlinearity (DNL) TBD TBD ANALOG OUTPUT Offset Error Gain Error (Without Internal Reference) Gain Error (With Internal Reference) Full-Scale Output Current2 Output Compliance Range Output Resistance Output Capacitance –0.02 –0.5 –0.5 2.0 –1.0 Typ Max Bits ±0.25 ±0.25 TBD TBD LSB LSB +0.02 +0.5 +0.5 20.0 +1.25 % of FSR % of FSR % of FSR mA V kΩ pF 1.26 V nA 1.25 1 0.5 V MΩ MHz 0 ±50 ±100 ±50 ppm of FSR/°C ppm of FSR/°C ppm of FSR/°C ppm/°C ±0.1 ±0.1 100 5 REFERENCE OUTPUT Reference Voltage Reference Output Current 3 1.14 REFERENCE INPUT Input Compliance Range Reference Input Resistance (Ext. Ref) Small Signal Bandwidth 1.20 100 0.1 TEMPERATURE COEFFICIENTS Offset Drift Gain Drift (Without Internal Reference) Gain Drift (With Internal Reference) Reference Voltage Drift POWER SUPPLY Supply Voltages AVDD DVDD Analog Supply Current (IAVDD) Digital Supply Current (IDVDD)4 Supply Current Sleep Mode (IAVDD) Power Dissipation4 Power Dissipation5 Power Supply Rejection Ratio—AVDD6 Power Supply Rejection Ratio—DVDD6 3.0 3.0 OPERATING RANGE Unit 3.3 3.3 33 8 5 135 145 3.6 3.6 36 TBD 6 145 –1 –0.04 +1 +0.04 V V mA mA mA mW mW % of FSR/V % of FSR/V –40 +85 °C NOTES 1 Measured at IOUTA, driving a virtual ground. 2 Nominal full-scale current, IOUTFS, is 32 times the IREF current. 3 An external buffer amplifier with input bias current <100 nA should be used to drive any external load. 4 Measured at fCLOCK = 25 MSPS and fOUT = 1.0 MHz. 5 Measured as unbuffered voltage output with IOUTFS = 20 mA and 50 Ω RLOAD at IOUTA and IOUTB, fCLOCK = 100 MSPS and fOUT = 40 MHz. 6 ±5% Power supply variation. Specifications subject to change without notice. REV. PrA –2– PRELIMINARY TECHNICAL DATA AD9748 DYNAMIC SPECIFICATIONS (TMIN to TMAX , AVDD = 3.3 V, DVDD = 3.3 V, IOUTFS = 20 mA, Differential Transformer Coupled Output, 50 ⍀ Doubly Terminated, unless otherwise noted.) Parameter Min DYNAMIC PERFORMANCE Maximum Output Update Rate (fCLOCK) Output Settling Time (tST) (to 0.1%)1 Output Propagation Delay (tPD) Glitch Impulse Output Rise Time (10% to 90%)1 Output Fall Time (10% to 90%)1 Output Noise (IOUTFS = 20 mA)2 Output Noise (IOUTFS = 2 mA)2 Noise Spectral Density3 Typ Max 165 AC LINEARITY Spurious-Free Dynamic Range to Nyquist fCLOCK = 25 MSPS; fOUT = 1.00 MHz 0 dBFS Output fCLOCK = 65 MSPS; fOUT = 1.00 MHz fCLOCK = 65 MSPS; fOUT = 2.51 MHz fCLOCK = 65 MSPS; fOUT = 10 MHz fCLOCK = 65 MSPS; fOUT = 15 MHz fCLOCK = 65 MSPS; fOUT = 25 MHz fCLOCK = 165 MSPS; fOUT = 21 MHz fCLOCK = 165 MSPS; fOUT = 41 MHz Total Harmonic Distortion fCLOCK = 25 MSPS; fOUT = 1.00 MHz fCLOCK = 50 MSPS; fOUT = 2.00 MHz fCLOCK = 65 MSPS; fOUT = 2.00 MHz fCLOCK = 125 MSPS; fOUT = 2.00 MHz Signal-to-Noise Ratio fCLOCK = 65 MSPS; fOUT = 5 MHz; IOUTFS = 20 mA fCLOCK = 65 MSPS; fOUT = 5 MHz; IOUTFS = 5 mA fCLOCK = 125 MSPS; fOUT = 5 MHz; IOUTFS = 20 mA fCLOCK = 125 MSPS; fOUT = 5 MHz; IOUTFS = 5 mA fCLOCK = 165 MSPS; fOUT = 5 MHz; IOUTFS = 20 mA fCLOCK = 165 MSPS; fOUT = 5 MHz; IOUTFS = 5 mA TBD Unit 11 1 5 2.5 2.5 50 30 TBD MSPS ns ns pV-s ns ns pA/√Hz pA/√Hz dBm/Hz TBD TBD TBD TBD TBD TBD TBD TBD dBc dBc dBc dBc dBc dBc dBc dBc TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD dBc dBc dBc dBc dB dB dB dB dB dB NOTES 1 Measured single-ended into 50 ý load. 2 Output noise is measured with a full-scale output set to 20 mA with no conversion activity. It is a measure of the thermal noise only. 3 Noise spectral density is the average noise power normalized to a 1 Hz bandwidth, with the DAC converting and producing an output tone. Specifications subject to change without notice. REV. PrA –3– PRELIMINARY TECHNICAL DATA AD9748 DIGITAL SPECIFICATIONS (TMIN to TMAX , AVDD = 3.3 V, DVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.) Parameter DIGITAL INPUTS Logic “1” Voltage Logic “0” Voltage Logic “1” Current Logic “0” Current Input Capacitance Input Setup Time (tS) Input Hold Time (tH) Latch Pulsewidth (tLPW) Min Typ 2.1 3 0 Max Unit V V µA µA pF ns ns ns 0.9 +10 +10 –10 –10 5 2.0 1.5 1.5 Figure 1. Timing Diagram ABSOLUTE MAXIMUM RATINGS* Parameter AVDD DVDD ACOM AVDD CLOCK, SLEEP Digital Inputs IOUTA, IOUTB REFIO, REFLO, FSADJ Junction Temperature Storage Temperature Lead Temperature (10 sec) ORDERING GUIDE Temperature Range Package Description Package Options* With Respect to Min Max Unit Model ACOM DCOM DCOM DVDD DCOM DCOM ACOM ACOM –0.3 –0.3 –0.3 –3.9 –0.3 –0.3 –1.0 –0.3 +3.9 +3.9 +0.3 +3.9 DVDD + 0.3 DVDD + 0.3 AVDD + 0.3 AVDD + 0.3 150 +150 300 V V V V V V V V °C °C °C AD9748XCP –40°C to +85°C 32-Lead LFCSP –65 CP-32 *CP = Leadframe Chip Scale Package THERMAL CHARACTERISTICS Thermal Resistance 32-Lead LFCSP JA= TBD°C/W *Stresses above those listed under Absolute Maximum Ratings may cause perma nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9748 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. PrA PRELIMINARY TECHNICAL DATA AD9748 32 DB2 31 DB3 30 DB4 29 DB5 28 DB6 27 DB7 (MSB) 26 DCOM 25 SLEEP PIN CONFIGURATION PIN 1 INDICATOR AD9748 TOP VIEW 24 FSADJ 23 REFIO 22 ACOM 21 IOUTA 20 IOUTB 19 ACOM 18 AVDD 17 AVDD NC 9 DCOM 10 CLKVDD 11 CLK+ 12 CLK- 13 CLKCOM 14 MODE2 15 MODE1 16 DB1 1 (LSB) DB0 2 DVDD 3 NC 4 NC 5 NC 6 NC 7 NC 8 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 27 28-32, 1 2 25 DB7 DB6–DB1 DB0 SLEEP 23 REFIO 24 4-9 19, 22 20 21 17, 18 15 16 FS ADJ NC ACOM IOUTB IOUTA AVDD MODE2 MODE1 10, 26 3 12 13 11 14 DCOM DVDD CLK+ CLKCLKVDD CLKCOM Most Significant Data Bit (MSB) Data Bits 6-1 Least Significant Data Bit (LSB) Power-Down Control Input. Active high. Contains active pull-down circuit; it may be left unterminated if not used. Reference Input/Output. Serves as reference input when internal reference disabled (i.e., tie REFLO to AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., tie REFLO to AGND). Requires 0.1 µF capacitor to AGND when internal reference activated. Full-Scale Current Output Adjust No Internal Connection Analog Common Complementary DAC Current Output. Full-scale current when all data bits are 0s. DAC Current Output. Full-scale current when all data bits are 1s. Analog Supply Voltage (3.3 V) Selects Input Data Format. Connect to CLKGND for straight binary, CLKVDD for two’s complement. Clock Mode Selection. Connect to CLKGND for single ended clock receiver (drive clk+ and float clk-). Connect to CLKVDD for differential receiver. Float for PECL receiver (terminations on-chip). Digital Common Digital Supply Voltage (3.3 V) Differential Clock Input. Differential Clock Input. Clock Supply Voltage (3.3 V) Clock Common REV. PrA –5– PRELIMINARY TECHNICAL DATA AD9748 DEFINITIONS OF SPECIFICATIONS Linearity Error (Also Called Integral Nonlinearity or INL) range (FSR) per °C. For reference drift, the drift is reported in ppm per °C. Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Power Supply Rejection The maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages. Differential Nonlinearity (or DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Settling Time The time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. Monotonicity A D/A converter is monotonic if the output either increases or remains constant as the digital input increases. Glitch Impulse Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is specified as the net area of the glitch in pV-s. Offset Error The deviation of the output current from the ideal of zero is called the offset error. For IOUTA, 0 mA output is expected when the inputs are all 0s. For IOUTB, 0 mA output is expected when all inputs are set to 1s. Spurious-Free Dynamic Range The difference, in dB, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. Gain Error Total Harmonic Distortion The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to 0s. THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. It is expressed as a percentage or in decibels (dB). Output Compliance Range Multitone Power Ratio The range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown resulting in nonlinear performance. The spurious free dynamic range containing multiple carrier tones of equal amplitude. It is measures as the difference between the rms amplitude of a carrier tone to the peak spurious signal in the region of a removed tone. Temperature Drift Temperature drift is specified as the maximum change from the ambient (25°C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of full-scale 3.3V REFLO AVDD 150pF +1.20V REF 0.1F REFIO PMOS CURRENT SOURCE ARRAY FS ADJ RSET 2k⍀ 3.3V DVDD DCOM 50⍀ RETIMED CLOCK OUTPUT* LECROY 9210 PULSE GENERATOR MINI-CIRCUITS T1-1T IOUTA SEGMENTED SWITCHES FOR DB13–DB5 CLOCK DVDD DCOM ACOM AD9744 LSB SWITCHES 100⍀ IOUTB MODE LATCHES 50⍀ SLEEP 50⍀ CLOCK OUTPUT RHODE & SCHWARZ FSEA30 SPECTRUM ANALYZER 20pF 20pF DIGITAL DATA TEKTRONIX AWG-2021 w/OPTION 4 * AWG2021 CLOCK RETIMED SUCH THAT DIGITAL DATA TRANSITIONS ON FALLING EDGE OF 50% DUTY CYCLE CLOCK. Figure 2. Basic AC Characterization Test Set-Up –6– REV. PrA PRELIMINARY TECHNICAL DATA AD9748 OUTLINE DIMENSIONS Dimensions shown in inches and (mm) 32-Lead Leadframe Chip Scale Package (LFCSP) (CP-28) REV. PrA –7–