19-1389; Rev 1; 12/99 Low-Cost 4x4, 8x4, 8x8 Video Crosspoint Switches Features ♦ Eight (MAX4456) or Four (MAX4359/MAX4360) Internal Buffers 250V/µs Slew Rate Three-State Output Capability Power-Saving Disable Feature 65MHz -3dB Bandwidth ♦ Routes Any Input Channel to Any Output Channel ♦ Serial or Parallel Digital Interface ♦ Expandable for Larger Switch Matrices ♦ 80dB All-Channel Off-Isolation at 5MHz ♦ 70dB Single-Channel Crosstalk ♦ Straight-Through Pinouts Simplify Layout ♦ Low-Cost Pin-Compatible Alternative to MAX456 (MAX4456) The MAX4456 has a digitally controlled 8x8 switch matrix and is a low-cost pin-for-pin compatible alternative to the popular MAX456. The MAX4359/MAX4360 are similar to the MAX4456, with the 8x8 switch matrix replaced by a 4x4 (MAX4359) or an 8x4 (MAX4360) switch matrix. Three-state output capability and internal, programmable active loads make it feasible to parallel multiple devices to form larger switch arrays. The inputs and outputs are on opposite sides, and a quiet power supply or digital input line separates each channel, which reduces crosstalk to -70dB at 5MHz. For applications demanding better DC specifications, see the MAX456 8x8 video crosspoint switch. ________________________ Applications High-Speed Signal Routing Video-On-Demand Systems Video Test Equipment Video Conferencing Security Systems Ordering Information PART MAX4359EAX MAX4359EWG MAX4360EAX MAX4456CPL MAX4456CQH MAX4456EPL MAX4456EQH TEMP. RANGE PIN-PACKAGE -40°C to +85°C -40°C to +85°C -40°C to +85°C 0°C to +70°C 0°C to +70°C -40°C to +85°C -40°C to +85°C 36 SSOP 24 SO 36 SSOP 40 Plastic DIP 44 PLCC 40 Plastic DIP 44 PLCC Pin Configurations appear at end of data sheet. _________________________________________________ Typical Application Circuits 8 INPUT CHANNELS MAX497 AV = +2 75Ω 4 INPUT CHANNELS (8 INPUT CHANNELS) (MAX4360) Z0 = 75Ω MAX497 AV = +2 WR LATCH WR LATCH 75Ω MAX4456 OUTPUT SELECT INPUT SELECT OR SERIAL I/O MAX4359 (MAX4360) A2 A1 A0 OUTPUT SELECT 8x8 T-SWITCH MATRIX D3 D2 D1/SER OUT D0/SER IN AV = +2 INPUT SELECT OR SERIAL I/O 75Ω Z0 = 75Ω 75Ω A1 A0 4x4 (8x4) T-SWITCH MATRIX D3 D2 D1/SER OUT D0/SER IN MAX497 ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. MAX4359/MAX4360/MAX4456 General Description The MAX4359/MAX4360/MAX4456 low-cost video crosspoint switches are designed to reduce component count, board space, design time, and system cost. Each contains a matrix of T-switches that connect any of their four (MAX4359) or eight (MAX4360/MAX4456) video inputs to any of their buffered outputs, in any combination. Each matrix output is buffered by an internal, high-speed (250V/µs), unity-gain amplifier that is capable of driving 400Ω and 20pF at 2.6Vp-p. For applications requiring increased drive capability, buffer the MAX4359/ MAX4360/MAX4456 outputs with the MAX497 quad, gain-of-two video line driver. MAX4359/MAX4360/MAX4456 Low-Cost 4x4, 8x4, 8x8 Video Crosspoint Switches ABSOLUTE MAXIMUM RATINGS Total Supply Voltage (V+ to V-) ...........................................+12V Positive Supply Voltage (V+) Referred to AGND .......-0.3V to +12V Negative Supply Voltage (V-) Referred to AGND ......-12V to +0.3V DGND to AGND ..................................................................±0.3V Buffer Short Circuit to Ground when Not Exceeding Package Power Dissipation .............Indefinite Analog Input Voltage ............................(V+ + 0.3V) to (V- - 0.3V) Digital Input Voltage .............................(V+ + 0.3V) to (V- - 0.3V) Input Current, Power On or Off Digital Inputs.................................................................±20mA Analog Inputs ...............................................................±50mA Continuous Power Dissipation (TA = +70°C) 36-Pin SSOP (derate 11.8mW/°C above +70°C) ...........941mW 24-Pin SO (derate 11.8mW/°C above +70°C)................941mW 40-Pin Plastic DIP (derate 11.3mW/°C above +70°C)....889mW 44-Pin PLCC (derate 13.3mW/°C above +70°C) .......1066mW Operating Temperature Ranges MAX4456C _ _ ....................................................0°C to +70°C MAX4_ _ _E_ _ .................................................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (V+ = +5V, V- = -5V, VLOAD = +5V (internal load resistors on), VIN_ = VAGND = VDGND = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER CONDITIONS MIN TYP MAX UNITS Operating Supply Voltage Inferred from PSRR test ±4.5 ±5.5 V Input Voltage Range Inferred from swing test -1.3 1.3 V Voltage Gain Buffer Offset Voltage Internal load resistors on, no external load, VIN = 0 to 1V TA = +25°C 0.99 1.0 1.01 TA = TMIN to TMAX 0.98 1.0 1.02 ±1 ±15 TA = +25°C TA = TMIN to TMAX ±20 Offset Voltage Drift 20 MAX4359/MAX4360 Supply Current, All Buffers On (no external load) MAX4456 TA = +25°C 50 ±4.5V to ±5.5V 50 Internal load resistors off, all buffers off TA = +25°C 250 TA = TMIN to TMAX 200 VLOAD = 5V Buffer Output Voltage Swing Internal load resistors on, no external load 400 nA ±100 nA 600 0.8 2.4 Serial mode, VSER/PAR = 5V IOL = 0.4mA IOH = -0.4mA _______________________________________________________________________________________ V V 0.4 4 µA Ω 10 Input Logic High Threshold Ω V ±1 Input Logic Low Threshold 2 dB ±1.3 Output Impedance at DC mA ±100 765 Digital Input Current SER OUT Output Logic Low/High 5 64 ±0.1 Internal Amplifier Load Resistor mA 65 1.6 Analog Input Current Output Leakage Current 39 TA = TMIN to TMAX Supply Current, All Buffers Off Power-Supply Rejection Ratio 32 37 TA = +25°C mV µV/°C 20 TA = TMIN to TMAX V/V V Low-Cost 4x4, 8x4, 8x8 Video Crosspoint Switches (V+ = +5V, V- = -5V, VLOAD = +5V (internal load resistors on), VAGND = VDGND = 0, TA = +25°C, unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX UNITS DYNAMIC SPECIFICATIONS X Output-Buffer Slew Rate Internal load resistors on, 10pF load 250 V/µs Single-Channel Crosstalk 5MHz, VIN = 2Vp-p (Note 1) 70 dB All-Hostile Crosstalk 5MHz, VIN = 2Vp-p (Notes 1, 2) 57 dB All-Channel Off-Isolation 5MHz, VIN = 2Vp-p (Note 1) 80 dB -3dB Bandwidth 10pF load, VIN = 2Vp-p (Note 1) 35 MHz Small-Signal -3dB Bandwidth 10pF load, VIN = 100mVp-p (Note 1) 65 MHz 0.1dB Bandwidth 10pF load, VIN = 100mVp-p (Note 1) 4 MHz Differential Phase Error (Note 3) 1.0 degrees Differential Gain Error (Note 3) 0.5 % Input Noise DC to 40MHz 0.3 mVRMS Input Capacitance All buffer inputs grounded 6 pF Buffer Input Capacitance Additional capacitance for each output buffer connected to channel input 2 pF Output Capacitance Output buffer off 7 pF SWITCHING CHARACTERISTICS (Figure 4, V+ = +5V, V- = -5V, VLOAD = +5V (internal load resistors on), VIN_ = VAGND = VDGND = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 4) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Chip-Enable to Write Setup tCE 0 ns Write Pulse Width High tWH 80 ns Write Pulse Width Low tWL 80 ns Data Setup tDS Data Hold Parallel mode 240 Serial mode 160 ns tDH 0 ns Latch Pulse Width tL 80 ns Latch Delay tD 80 ns Switch Break-Before-Make Delay tON - tOFF LATCH Edge to Switch Off tOFF LATCH Edge to Switch On tON LATCH on 15 ns 35 ns 50 ns Note 1: See Dynamic Test Circuits section. Note 2: 3dB typical crosstalk improvement when RS = 0. Note 3: Input test signal: 3.58MHz sine wave of amplitude 40IRE superimposed on a linear ramp (0 to 100IRE). IRE is a unit of video-signal amplitude developed by the International Radio Engineers. 140IRE = 1.0V. Note 4: Guaranteed by design. _______________________________________________________________________________________ 3 MAX4359/MAX4360/MAX4456 AC ELECTRICAL CHARACTERISTICS MAX4359/MAX4360/MAX4456 Low-Cost 4x4, 8x4, 8x8 Video Crosspoint Switches Pin Description PIN MAX4359 MAX4360 MAX4456 NAME FUNCTION SO SSOP SSOP DIP PLCC 1 1 1 1 2 D1/ SER OUT Parallel Data Bit D1 when SER/PAR = GND. Serial output for cascading multiple parts when SER/PAR = VCC. 2 2 2 2 3 D0/SER IN Parallel Data Bit D0 when SER/PAR = GND. Serial input when SER/PAR = VCC. 3, 5 3, 5 3, 5 3, 4, 6 4, 5, 7 A_ Output Buffer Address Lines 4, 6, 8, 10 4, 6, 8, 10 4, 6, 8, 10, 12, 14, 16, 18 IN_ Video Input Lines 7 7 7 8 9 LOAD Asynchronous Control Line. When LOAD = VCC, all the 400Ω internal active loads are on. When LOAD = GND, external 400Ω loads must be used. The buffers must have a resistive load to maintain stability. 9 9 9 10, 12 11, 14 DGND Digital Ground. DGND pins must have the same potential and be bypassed to AGND. DGND should be within ±0.3V of AGND. When this control line is high, the 2nd-rank registers are loaded with the rising edge of LATCH. If this control line is low, the 2nd-rank registers are transparent when LATCH is low, passing data directly from the 1st-rank registers to the decoders. 11 11 11 14 16 EDGE/ LEVEL — 12–16, 18, 22–26 22–26 — 1, 12, 23, 34 N.C. 12 17 17 18 20 SER/PAR 13 19, 30 19, 30 20, 34 22, 38 V- Negative Supply. All V- pins must be connected to each other and bypassed to GND separately (Figure 2). 14 20 20 21 24 WR In serial mode, WR (write) shifts data into the input register. In parallel mode, WR loads data into the 1st-rank registers. Data is latched on the rising edge. 15 4 5, 7, 9, 11, 6, 8, 10, 13, 13, 15, 17, 15, 17, 19, 19 21 21 21 22 25 LATCH No connection. Not internally connected. Connect to VCC for serial mode; connect to GND for parallel mode. If EDGE/LEVEL = VCC, data is loaded from the 1strank registers to the 2nd-rank registers on the rising edge of LATCH. If EDGE/LEVEL = GND, data is loaded while LATCH = GND. In addition, data is loaded during the execution of parallel-mode functions 1011 through 1110, or if LATCH = VCC during the execution of the parallel-mode “software-latch” command (1111). _______________________________________________________________________________________ Low-Cost 4x4, 8x4, 8x8 Video Crosspoint Switches PIN MAX4359 MAX4360 MAX4456 NAME FUNCTION SO SSOP SSOP DIP PLCC — — — 23 26 CE Active-Low Chip Enable. WR is enabled when CE = GND and CE = VCC. WR is disabled when CE = VCC and CE = GND. 16 27 27 24 27 CE Active-High Chip Enable. WR is enabled when CE = GND and CE = VCC. WR is disabled when CE = VCC and CE = GND. 17, 19, 21, 23 28, 31, 33, 35 28, 31, 33, 35 25, 27, 29, 31, 33, 35, 37, 39 28, 30, 32, 35, 37, 39, 41, 43 OUT_ Buffer Outputs. Buffer inputs are internally grounded with a 1000 or 1001 command from the D3–D0 lines. 18 29 15, 29 28, 30, 32 31, 33, 36 AGND Analog Ground. AGND must be at 0.0V, since the gainsetting resistors of the buffers are connected to these pins. 20 32 32 36 40 D3 Parallel Data Bit when SER/PAR = GND. When D3 = GND, D0–D2 specify the input channel to be connected to specified buffer. When D3 = VCC, D0–D2 specify control codes. D3 is not used in serial mode (SER/PAR = VCC). 22 34 34 38 42 D2 Parallel Data Bit D2 when SER/PAR = GND. Not used when SER/PAR = VCC. 24 36 13, 36 16, 26, 40 18, 29, 44 V+ Positive Supply. All V+ pins must be connected to each other and bypassed to AGND separately (Figure 2). _______________________________________________________________________________________ 5 MAX4359/MAX4360/MAX4456 Pin Description (continued) MAX4359/MAX4360/MAX4456 Low-Cost 4x4, 8x4, 8x8 Video Crosspoint Switches Detailed Description Output Buffers The MAX4456 video crosspoint switch consists of 64 T-switches in an 8x8 grid (Figure 1). The eight matrix outputs are followed by eight wideband buffers optimized for driving 400Ω and 20pF loads. The MAX4359’s core is a 4x4 switch matrix with each of its outputs followed by a wideband buffer. The MAX4360 has an 8x4 matrix and four output buffers. Each buffer has an internal active load on the output that can be readily shut off through the LOAD input (off when LOAD = 0V). The shut-off is useful when two or more crosspoints are connected in parallel to create more input channels. With more input channels, only one set of IN0 IN1 IN2 IN4 IN3 IN5 IN6 buffers can be active and only one set of loads can be driven. When active, the buffer must have either 1) an internal load, 2) the internal load of another buffer in another MAX4359/MAX4360/MAX4456, or 3) an external load. Each output can be disabled under logic control. When a buffer is disabled, its output enters a high-impedance state. In multichip parallel applications, the disable function prevents inactive outputs from loading lines driven by other devices. Disabling the inactive buffers reduces power consumption. The outputs connect easily to MAX497 quad, gain-oftwo buffers when back-terminated 75Ω coaxial cable must be driven. IN7 OUTPUT BUFFERS A = +1 OUT0 400Ω MAX4456 8x8 SWITCH MATRIX LOAD A = +1 SER/PAR 2nd-RANK REGISTERS LATCH EDGE/LEVEL 1st-RANK REGISTERS WR CE CE V+ A0 A1 A2 D0/SER IN D2 OUT7 400Ω V- AGND DGND D3 D1/SER OUT Figure 1. MAX4456 Functional Diagram 6 _______________________________________________________________________________________ Low-Cost 4x4, 8x4, 8x8 Video Crosspoint Switches Digital Interface The desired switch state can be loaded in a parallelinterface mode or serial-interface mode (Table 3 and Figures 4, 5, 6). All action associated with the WR line occurs on its rising edge. The same is true for the LATCH line if EDGE/LEVEL is high. Otherwise, the second-rank registers update while LATCH is low (when EDGE/LEVEL is low). WR is logically ANDed with CE and CE (when present) to allow active-high or activelow chip enable. 6-Bit Parallel-Interface Mode (MAX4359/MAX4360) In the MAX4359/MAX4360’s parallel-interface mode (SER/PAR = GND), the six data bits specify an output channel (A1, A0) and the input channel to which it connects (D3–D0). This data is loaded on the rising edge of WR. The input channels are selected by codes 0000 through 0111 (D3–D0) for the MAX4360, and codes 0000 through 0011 (D3–D0) for the MAX4359. Note that the MAX4359 does not use codes 0100 through 0111. The eight codes 1000 through 1111 control other functions, as listed in Table 1. 7-Bit Parallel-Interface Mode (MAX4456) In the MAX4456’s parallel-interface mode (SER/PAR = GND), the seven data bits specify an output channel (A2, A1, A0) and the input channel to which it connects (D3–D0). This data is loaded on the rising edge of WR. The input channels are selected by codes 0000 through 0111 (D3–D0) for the MAX4456. The remaining eight codes 1000 through 1111 control other functions, as listed in Table 1. 16-Bit Serial-Interface Mode (MAX4359/MAX4360) In serial mode (SER/PAR = VCC), all first-rank registers are loaded with data, making it unnecessary to specify an output address (A1, A0). The input data format is D3–D0, starting with OUT0 and ending with OUT3 for 16 total bits. For the MAX4360, only codes 0000 through 1010 are valid. For the MAX4359, only the codes 0000 through 0011 and codes 1000 through 1010 are valid. Code 1010 disables a buffer, while code 1001 enables it. After data is shifted into the 16bit first-rank register, it is transferred to the second rank by LATCH (Table 2), which updates the switches. Table 1. Parallel-Interface Mode Functions A2, A1, A0 Selects Output Buffer D3–D0 FUNCTION 0000 to 0111 Connect the buffer selected by A2–A0 (MAX4456) or A1–A0 (MAX4359/MAX4360) to the input channel selected by D3–D0. 1000 Connect the buffer selected by A2–A0 (MAX4456) or A1–A0 (MAX4359/MAX4360) to DGND. Note, if the buffer output is on, its output is its offset voltage. 1011 Shut off the buffer selected by A2–A0 (MAX4456) or A1–A0 (MAX4359/MAX4360) and retain 2nd-rank registers contents. 1100 Turn on the buffer selected by A2–A0 (MAX4456) or A1–A0 (MAX4359/MAX4360, and restore the previously connected channel. 1101 Turn off all buffers, and leave 2nd-rank registers unchanged. 1110 Turn on all buffers, and restore the connected channels. 1111 Send a pulse to the 2nd-rank registers to load them with the contents of the 1st-rank registers. When latch is held high, this “software-LATCH” command performs the same function as pulsing LATCH low. 1001 and 1010 Do not use these codes in the parallel-interface mode. These codes are for the serialinterface mode only. 0100 and 0111 For the MAX4359, unused codes. _______________________________________________________________________________________ 7 MAX4359/MAX4360/MAX4456 Power-On RESET The MAX4359/MAX4360/MAX4456 have an internal power-on reset (POR) circuit that remains low for 5µs after power is applied. POR also remains low if the total supply voltage is less than 4V. The POR disables all buffer outputs at power-up, but the switch matrix is not preset to any initial condition. The desired switch state should be programmed before the buffer outputs are enabled. MAX4359/MAX4360/MAX4456 Low-Cost 4x4, 8x4, 8x8 Video Crosspoint Switches 32-Bit Serial-Interface Mode (MAX4456) Table 2. Serial-Interface Mode Functions D3–D0 FUNCTION 0000 to 0111 Connect the selected buffer to the input channel selected by D3–D0. Note that 0100 through 0111 are not valid for the MAX4359. 1000 Connect the input of the selected buffer to GND. Note: If the buffer output remains on, its input is its offset voltage. 1001 Turn on the selected buffer and connect its input to GND. Use this code to turn on buffers after power is applied. The default power-up state is all buffers disabled. 1010 Shut off the selected buffer at the specified channel, and erase data stored in the 2nd rank of registers. The 2nd rank now holds the command word 1010. 1011 to 1111 Do not use these codes in the serial-interface mode. They inhibit the latching of the 2nd-rank registers, which prevents proper data loading. In serial mode (SER/PAR = VCC), all first-rank registers are loaded with data, making it unnecessary to specify an output address (A2, A1, A0). The input data format is D3–D0, starting with OUT0 and ending with OUT7 for 32 total bits. Only codes 0000 through 1010 are valid. Code 1010 disables a buffer, while code 1001 enables it. After data is shifted into the 32-bit first-rank register, it is transferred to the second rank by LATCH (Table 2), which updates the switches. Table 3. Input/Output Line Configurations SERIAL / PARALLEL D3 D2 D1 D0 (A2), A1, A0 H X X Serial Output Serial Input X L H Parallel Input Parallel Input Parallel Input Output Buffer Address Parallel Mode, D0–D2 = Control Code L L Parallel Input Parallel Input Parallel Input Output Buffer Address Parallel Mode, D0–D2 = Input Address COMMENT Serial Mode X = Don’t care, H = 5V, L = 0V ( ) are for MAX4456 only. 8 _______________________________________________________________________________________ Low-Cost 4x4, 8x4, 8x8 Video Crosspoint Switches MAX4359/MAX4360/MAX4456 MAX497 5 IN0 8 INPUT VIDEO CHANNELS 1 2 3 4 5 6 7 8 14 18 19 20 21 22 23 24 25 7 9 11 13 15 17 19 22 21 2 1 38 36 6 4 3 OUT0 39 2 IN0 OUT0 16 37 35 33 31 29 27 25 24 14 8 40 26 4 IN1 6 IN2 8 IN3 AV = 2 OUT1 14 OUT2 12 OUT3 10 IN1 IN2 IN3 IN4 IN5 IN6 IN7 OUT1 OUT2 OUT3 OUT4 MAX4456 OUT5 OUT6 OUT7 CE EDGE/LEVEL LOAD LATCH V+ WR V+ D0/SER IN D1/SER OUT D2 D3 A0 A1 A2 AGND DGND VVCE SER/PAR V+ 28, 30, 32 10, 12 20 34 23 18 16 DB–25 VCC 9,15 75Ω Z0 = 75Ω 75Ω VEE GND 1, 3, 5, 7 11,13 -5V +5V -5V +5V NOTE: ALL BYPASS CAPACITORS ARE 0.1µF CERAMIC. Figure 2. MAX4456 (plastic DIP) Typical Application Circuit Typical Application Figure 2 shows a typical application of the MAX4456 (PDIP) with MAX497 quad, gain-of-two buffers at the outputs to drive 75Ω loads. This application shows the MAX4456 digital-switch control interface set up in the 7bit parallel mode. The MAX4456 uses seven data lines and two control lines (WR and LATCH). Two additional lines may be needed to control CE and LOAD when using multiple MAX4456s. The input/output information is presented to the chip at A2, A1, A0, and D3–D0 by a parallel printer port. The data is stored in the 1st-rank registers on the rising edge of WR. When the LATCH line goes high, the switch configuration is loaded into the 2nd-rank registers, and all eight outputs enter the new configuration at the same time. Each 7-bit word updates only one output buffer at a time. If several buffers are to be updated, the data is individually loaded into the 1st-rank registers. Then, a single LATCH pulse is used to reconfigure all channels simultaneously. The short BASIC program in Figure 3 loads programming data into the MAX4456 from any IBM PC or compatible. It uses the computer’s “LPT1” output to interface to the circuit, then automatically finds the address for LPT1 and displays a table of valid input values to be used. The program does not keep track of previous commands, but it does display the last data sent to LPT1, which is written and latched with each transmission. A similar application is possible with the MAX4359/MAX4360. Chip Information MAX4359 TRANSISTOR COUNT: 2372 MAX4360 TRANSISTOR COUNT: 2372 MAX4456 TRANSISTOR COUNT: 3820 _______________________________________________________________________________________ 9 MAX4359/MAX4360/MAX4456 Low-Cost 4x4, 8x4, 8x8 Video Crosspoint Switches Figure 3. BASIC Program for Loading Data into the MAX4456 from a PC Using Figure 2’s Circuit Timing Diagrams A0–A2 VALID DATA N-1 VALID DATA N D0–D3 tDS tDH tWL tWH WR tD LATCH tL Figure 4. Write Timing for Serial- and Parallel-Interface Modes 10 ______________________________________________________________________________________ Low-Cost 4x4, 8x4, 8x8 Video Crosspoint Switches NOTE: SEE FIGURE 4 FOR WR AND LATCH TIMING. DATA (N) DATA (N + 1) DATA (N + 2) WR LATCH 1st-RANK REGISTER DATA DATA (N) 2nd-RANK REGISTER DATA (EDGE/LEVEL = GND) DATA (N) 2nd-RANK REGISTER DATA (EDGE/LEVEL = VCC) DATA (N + 1) DATA (N + 2) DATA (N + 1) DATA (N) DATA (N + 1) Figure 5. Parallel-Interface Mode Format (SER/PAR = GND) NOTES: SEE TABLE 2 FOR INPUT DATA. SEE FIGURE 4 FOR WR AND LATCH TIMING. INPUT DATA FOR OUT1 TO OUT6 INPUT DATA FOR OUT0 0D3 0D2 0D1 0D0 1D3 1D2 INPUT DATA FOR OUT7 7D3 7D2 7D1 7D0 WR LATCH 2nd-RANK REGISTER DATA (EDGE/LEVEL = GND) 2nd-RANK REGISTER DATA (EDGE/LEVEL = VCC) DATA VALID DATA VALID Figure 6. Serial-Mode Interface Format (SER/PAR = VCC) ______________________________________________________________________________________ 11 MAX4359/MAX4360/MAX4456 Timing Diagrams (continued) Low-Cost 4x4, 8x4, 8x8 Video Crosspoint Switches MAX4359/MAX4360/MAX4456 Dynamic Test Circuits IN0 OUT0 VOUT IN1 OUT1 VOUT IN2 OUT2 VOUT IN3 MAX4456 OUT3 IN3 MAX4456 OUT3 VOUT IN4 OUT4 IN4 OUT4 VOUT IN5 OUT5 IN5 OUT5 VOUT IN6 OUT6 IN6 OUT6 VOUT IN7 OUT7 IN7 OUT7 VOUT LOAD +5V IN0 OUT0 IN1 OUT1 IN2 OUT2 LOAD VOUT +5V VIN = 2Vp-p AT 5MHz RS = 75Ω VIN = 2Vp-p, SWEEP FREQUENCY RS = 75Ω -3dB BANDWIDTH (NOTES 1–4) 7 x 75Ω ALL-CHANNEL OFF-ISOLATION (NOTES 1, 5–8) IN0 OUT0 VOUT IN0 OUT0 IN1 OUT1 VOUT IN1 OUT1 IN2 OUT2 VOUT IN2 OUT2 IN3 MAX4456 OUT3 VOUT IN3 MAX4456 OUT3 IN4 OUT4 VOUT IN4 IN5 OUT5 VOUT IN5 OUT5 IN6 OUT6 VOUT IN6 OUT6 IN7 IN7 OUT7 LOAD 75Ω +5V VIN = 2Vp-p AT 5MHz RS = 75Ω SINGLE-CHANNEL CROSSTALK (NOTES 1, 5, 9–11) VOUT OUT4 OUT7 LOAD +5V VIN = 2Vp-p AT 5MHz RS = 75Ω ALL-HOSTILE CROSSTALK (NOTES 1, 5, 9, 11, 12) Connect LOAD to +5V (internal 400Ω loads on at all outputs). Program any one input to connect to any one output. See Table 1 or 2 for programming codes. Turn on the buffer at the selected output (Table 1 or 2). Drive the selected input with VIN, and measure VOUT at the -3dB frequency at the selected output. Program each numbered input to connect to the same numbered output (IN0 to OUT0, IN1 to OUT1, etc., for the MAX4456; also IN4 to OUT0, IN5 to OUT1, etc., for the MAX4360.) See Table 1 or 2 for programming codes. Note 6: Turn off all output buffers (Table 1 or 2). Note 7: Drive all inputs with VIN, and measure VOUT at any output. Note 8: Isolation (in dB) = 20log10 (VOUT/VIN). Note 9: Turn on all output buffers (Table 1 or 2). Note 10: Drive any one input with VIN, and measure VOUT at any undriven output. Note 11: Crosstalk (in dB) = 20log10 (VOUT/VIN). Note 12: Drive all but one input with VIN, and measure VOUT at the undriven output. Note 1: Note 2: Note 3: Note 4: Note 5: 12 ______________________________________________________________________________________ Low-Cost 4x4, 8x4, 8x8 Video Crosspoint Switches TOP VIEW 24 V+ D1/SER OUT 1 23 OUT0 D0/SER IN 2 A1 3 IN0 4 MAX4359 D1/SER OUT 1 36 V+ D0/SER IN 2 D1/SER OUT 1 35 OUT0 36 V+ D0/SER IN 2 35 OUT0 22 D2 A1 3 21 OUT1 IN0 4 33 OUT1 IN0 4 33 OUT1 32 D3 A0 5 32 D3 31 OUT2 IN1 6 34 D2 A1 3 34 D2 20 D3 A0 5 IN1 6 19 OUT2 IN1 6 LOAD 7 18 AGND LOAD 7 IN2 8 17 OUT3 IN2 8 29 AGND IN2 8 29 AGND DGND 9 28 OUT3 DGND 9 28 OUT3 D0/SER IN 2 39 OUT0 A2 3 A1 4 38 D2 MAX4456 37 OUT1 IN0 5 36 D3 A0 6 35 OUT2 IN1 7 34 V- LOAD 8 33 OUT3 IN2 9 32 AGND DGND 10 31 OUT4 IN3 11 30 AGND 24 N.C. V+ 13 24 N.C. N.C. 14 23 N.C. IN5 14 23 N.C. N.C. 15 22 N.C. AGND 15 22 N.C. N.C. 16 21 LATCH SER/PAR 17 IN6 16 20 WR N.C. 18 21 LATCH SER/PAR 17 19 V- 20 WR IN7 18 19 V- SSOP SSOP 6 5 4 3 2 1 44 43 42 D3 40 V+ 25 N.C. N.C. 13 OUT1 D1/SER OUT 1 26 N.C. IN4 12 D2 SO EDGE/LEVEL 11 25 N.C. OUT0 13 V- 26 N.C. N.C. 12 V+ SER/PAR 12 27 CE EDGE/LEVEL 11 N.C. 14 WR EDGE/LEVEL 11 D1/SER OUT 15 LATCH 41 40 A0 7 39 OUT2 IN1 8 38 V- LOAD 9 37 OUT3 IN2 10 36 AGND 35 OUT4 DGND 12 29 OUT5 IN4 13 28 AGND DGND 11 EDGE/LEVEL 14 27 OUT6 N.C. 12 34 N.C. IN3 13 33 AGND DGND 14 32 OUT5 IN4 15 31 AGND IN5 15 26 V+ MAX4456 V+ 16 25 OUT7 IN6 17 24 CE EDGE/LEVEL 16 30 OUT6 SER/PAR 18 23 CE IN5 17 29 V+ DIP OUT7 CE CE LATCH WR N.C. V- 18 19 20 21 22 23 24 25 26 27 28 IN7 21 WR SER/PAR V- 20 V+ 22 LATCH IN6 IN7 19 31 OUT2 30 V- IN3 10 D0/SER IN IN3 10 27 CE IN3 10 MAX4360 LOAD 7 A2 16 CE 30 V- A1 DGND 9 MAX4359 IN0 A0 5 PLCC ______________________________________________________________________________________ 13 MAX4359/MAX4360/MAX4456 Pin Configurations Low-Cost 4x4, 8x4, 8x8 Video Crosspoint Switches SSOP.EPS MAX4359/MAX4360/MAX4456 Package Information 14 ______________________________________________________________________________________ Low-Cost 4x4, 8x4, 8x8 Video Crosspoint Switches SOICW.EPS ______________________________________________________________________________________ 15 MAX4359/MAX4360/MAX4456 Package Information (continued) Low-Cost 4x4, 8x4, 8x8 Video Crosspoint Switches PDIPW.EPS PLCC.EPS MAX4359/MAX4360/MAX4456 Package Information (continued) Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ___________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.