MOTOROLA Order this document by MC33690/D SEMICONDUCTOR TECHNICAL MC33690 Standalone Tag Reader Circuit STARC STANDALONE TAG READER CIRCUIT The Standalone Tag Reader Circuit (STARC) is an integrated circuit dedicated to the automotive immobilizer applications. It combines on the same chip all the circuitry to interface with a transponder : antenna drivers and demodulator. A low dropout voltage regulator and a physical interface fully compatible with the ISO 9141 norm are also available. The Standalone Tag Reader Circuit is fabricated with the SMARTMOSTM3.5 technology. This process is a double layer metal, 1.4µm, 45V technology, combining CMOS and bipolar devices. • • • Contactless 125kHz tag reader module : - Self synchronous sample & hold demodulator - Amplitude or phase modulation detection - High sensitivity - Fast “read after write“ demodulator settling time - Low resistance and high current antenna drivers : 2Ω @ 150mA (typ.) - Bidirectionnal data transmission - Multi tag, multi scheme operation. Low dropout voltage regulator : - Wide input supply voltage range : from 5.5V up to 40V - Output current capability up to 150mA DC with an external power transistor - 5V output voltage with a ± 5% accuracy - Low voltage reset function - Low current consumption in standby mode : 300µA (typ.). ISO 9141 transmitter and receiver module : - Input voltage thresholds ratiometric to the supply voltage - Current limitation - Ouput slew rate control - No external protection device required. DW SUFFIX Plastic Package CASE 751D SO - 20 Pin Connections VSUP 1 20 Tx SOURCE 2 19 Rx GATE 3 18 K TD1 4 17 AM VSS 5 16 XTAL1 VDD 6 15 XTAL2 TD2 7 14 LVR MODE1 8 13 DOUT MODE2 9 12 CEXT RD 10 11 AGND ORDERING INFORMATION Device MC33690DW This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice. REV 4.8 © Motorola, Inc., 2002. Operating Junction Package Temperature Range T J = -40°C to 125°C SOIC 20 MC33690 BLOCK DIAGRAM Figure 1 : Standalone Tag Reader Circuit Optional : external N channel MOS required for sourced current > 50mA. A recommended reference is MMFT 3055VL from Motorola. VBAT VSUP C1 GATE SOURCE VDD Voltage Regulator LVR VDD 10µF VSS 8MHz RA TD1 XTAL1 LA XTAL2 R1 RD R2 CA MODE1 Tag Reader DOUT TD2 CEXT MODE2 AM CEXT VBAT 10nF AGND 510Ω Tx ISO 9141 Interface K Rx © Motorola, Inc., 2002. MOTOROLA SEMICONDUCTORS PRODUCTS 2 revision 4.8, 5 February 2002 MC33690 MAXIMUM RATINGS Rating Symbol Value Unit Supply voltage V SUP V SS -0.3 to +40 V Supply voltage without using the voltage regulator (V SUP = V DD ) V DD V SS -0.3 to +7 V V SS-0.3 to +40 V 0 mA V SS -0.3 V V SS -0.3 to V DD +0.3 V ±10 V V SS -3 to 40 V ±300 mA V SS ±0.3 V ±2000 V ESD voltage capability (MM, see note 1) ±200 V Solder heat resistance test (10s) 260 °C Voltage on SOURCE Current into/from GATE Voltage on GATE Voltage on pins : MODE1/2, CEXT, DOUT, LVR, XTAL1/2, Rx, Tx Voltage on RD Voltage on K and AM Current on TD1 & TD2 (Drivers on & off) Voltage on AGND ESD voltage capability (HBM, see note 1) Junction temperature TJ 170 °C Storage temperature Ts -65 to +150 °C Characteristic Symbol Value Unit Junction to ambiant thermal resistance (SOIC20) Rth 80 °C/W Note 1 : Human Body model, AEC-Q100-002 Rev. C. Machine Model, AEC-Q100-003 Rev. E. THERMAL CHARACTERISTIC © Motorola, Inc., 2002. MOTOROLA SEMICONDUCTORS PRODUCTS 3 revision 4.8, 5 February 2002 MC33690 PIN FUNCTION DESCRIPTION Pin Function 1 VSUP 2 SOURCE 3 GATE 4 TD1 Antenna driver 1 output 5 VSS Power and digital ground 6 VDD Voltage regulator output 7 TD2 Antenna driver 2 output 8 MODE1 Mode selection input 1 9 MODE2 Mode selection input 2 10 RD 11 AGND Demodulator ground 12 CEXT Comparator reference input 13 DOUT Demodulator output (5V) 14 LVR 15 XTAL2 Oscillator output 16 XTAL1 Oscillator input 17 AM 18 K 19 Rx ISO 9141 receiver monitor output 20 Tx ISO 9141 transmitter input © Motorola, Inc., 2002. Description Power supply External N channel transistor source External N channel transistor gate Demodulator input Low Voltage Reset input/output Amplitude modulation input ISO 9141 transmitter output and receiver input MOTOROLA SEMICONDUCTORS PRODUCTS 4 revision 4.8, 5 February 2002 MC33690 DESCRIPTION TAG READER MODULE The Tag Reader module is dedicated for automotive or industrial applications where information has to be transmitted contactless. The tag reader module is a write/read (challenge/ response) controller for applications which demand high security level. The tag reader module is connected to a serial tuned LC circuit which generates a magnetic field power supplying the tag. The use of a synchronous sample & hold technique allows communication with all avalaible tags using admittance switching producing absorption of the RF field. Load amplitude or phase shift modulation can be detected at high bit rates up to 8kHz. 125kHz is the typical operational carrier frequency of the tag reader module with a 8MHz clock. Figure 2 : Tag Reader block diagram AM Data RA TD1 1/32 counter LA 4MHz 125kHz Clock 8MHz 1/2 8MHz Shutdown 125kHz CA Self synchronous sample & hold Setup & Preload LVR TD2 Interface - R1 11.25° , 22.5° , 33.75° , 45° , 56.25° , 67.5° , 78.75° , 90° + 0°, -11.25°, -22.5°, -33.75°, -45°, -56.25°, -67.5°, -78.75° + VDD 500ns Buffer RD S/H Comparator + Buffer 100KΩ + D - Q Data out C VDD R2 500µA AGND CEXT © Motorola, Inc., 2002. CEXT 10nF MOTOROLA SEMICONDUCTORS PRODUCTS 5 revision 4.8, 5 February 2002 MC33690 Read function When answering to the base station, a transponder generates an absorption modulation of the magnetic field. It results in an amplitude/ phase modulation of the current across the antenna. This information is picked up at the antenna tap point between the coil and the capacitor. An external resistive ladder down scales this voltage to a level compatible with the demodulator input voltage range (see parameter VINRD page 16). The demodulator (see figure 2) consists of : - an input stage (emitter follower), - a sample & hold circuit, - a voltage follower, - a low offset voltage comparator. The sampling time is automatically set to take into account a phase shift due to the tolerances of the antenna components (L and C) and of the oscillator. The allowed phase shift measured at the input RD ranges from -45° to +45°. Assuming that the phase reference is the falling edge of the driving signal TD1, this leads to a sampling time phase ranging from -78.75° to 90° with discrete steps of 11.25°. After reset condition, the sampling time phase is +11.25°. The antenna phase shift evaluation is only done : - after each wake-up command (see pages 10 to 12), - or after reset (see page 7). This is necessary to obtain the best demodulator performances. In order to ensure a fast demodulator settling time after wake up, reset or a write sequence, the external capacitor CEXT is preloaded at its working voltage. This preset occurs 256µs after switching the antenna drivers on and its duration is 128µs. After wake up or reset, the preset has the same duration but begins 518µs after clock settling. After power on reset, VSUP must meet the minimum specified value, enabling the nominal operation of VDD, before the start of the preset. Otherwise the preset must be done by the user through a standby/wake-up sequence. Write function Whatever the selected configuration (see page 9), the write function is achieved by switching on/off the output drivers TD1/2. Once the drivers have been set in high impedance, the load current flows alternatively Figure 3 : Current flow when the buffers are switched off VDD RA TD1 ILOAD LA R1 VDD CA TD2 © Motorola, Inc., 2002. MOTOROLA SEMICONDUCTORS PRODUCTS 6 revision 4.8, 5 February 2002 MC33690 VOLTAGE REGULATOR internal LDMOS. The threshold voltage of this transistor must be lower than the one of the internal LDMOS (1.95V typ.) in order to prevent the current from flowing into the LDMOS. Its breakdown voltage must be higher than the maximum supply voltage. The low dropout voltage regulator provides a regulated 5V supply for the internal circuitry. It can also supply external peripherals or sensors. The input supply voltage ranges from 5.5V to over 40V. This voltage regulator uses a series combination of high voltage LDMOS and low voltage PMOS transistors to provide regulation. An external low ESR capacitor is required for the regulator stability. A low voltage reset function monitors the VDD output. An internal 10µA pull-up current source allows, when an external capacitor is connected between LVR and GND, to generate delays at power up (5ms typ. with CReset=22nF) . The LVR pin is also the input generating the internal reset signal. Applying a logic low level on this pin resets the circuit : - all the internal flip flops are reset, - the drivers TD1/2 are switched on. The maximum average current is limited by the power dissipation capability of the SO 20 package. This limitation can be overcome by connecting an external N channel MOS in parallel with the Figure 4 : Voltage regulator block diagram VBAT VSUP GATE C1 Charge pump 1MHz oscillator N channel LDMOS SOURCE Voltage reference - and biasing VDD + generator P channel MOS VDD 10µA LVR VDD VDD C2 C3 10µ F 100n F reset CReset Comparator + © Motorola, Inc., 2002. MOTOROLA SEMICONDUCTORS PRODUCTS 7 revision 4.8, 5 February 2002 MC33690 ISO 9141 PHYSICAL INTERFACE When a negative voltage is applied on the K or AM lines, the input current is internally limited by a 2kΩ resistor (typ.) in series with a diode. any capacitive load and protects against short circuit to the battery voltage. An overtemperature protection shuts the driver down when the junction temperature exceeds 150°C (typ). Once shut down by the overtemperature protection, the driver can be switched on again : - if the junction temperature has decreased below the threshold, - and by applying an off/on command, coming either from the demodulator in configurations A and B or directly applied on the input Tx in configuration C (see pin K status in table 1 page 9). A current limitation allows the transmitter to drive The electromagnetic emission is reduced thanks to the voltage slew rate control (5V/µs typ.). This interface module is fully compatible with the ISO 9141 norm describing the diagnosis line. It includes one transmitter (pin K) and 2 receivers (pins K and AM). The input stages consist of high voltage CMOS triggers. The thresholds are ratiometric to VSUP. A ground referenced current source (2.5µA typ.) pulls down the input when unconnected. Figure 5 : ISO 9141interface VDD L line 2kΩ AM data AM VSUP GND From configuration controller 2.5µA GND VSUP VDD 2kΩ Rx 2.5µA GND GND From configuration controller VBAT Over temperature detector K line Tag Reader module output K VDD Command Tx Current limitation © Motorola, Inc., 2002. MOTOROLA SEMICONDUCTORS PRODUCTS 8 revision 4.8, 5 February 2002 MC33690 COMMUNICATION MODES DESCRIPTION The STARC offers 3 different communication modes. Therefore it can be used as a standalone circuit connected to an Electronic Control Unit (ECU) through a bus line or it can be directly connected to a microcontroller in case of a single board architecture. Table 1. Communication modes description Configuration pins Configuration Type Bus type 1 wire (VBAT) Name A Mode1 0 Mode2 Pin status & function description 0 K output/input : - demodulator output, - amplitude modulation input - shutdown/wake-up AM must be connected to VSUP DOUT forces a low level 1 K output : - demodulator output AM input : - amplitude modulation input, - shutdown/wake-up DOUT forces a low level x DOUT output : - demodulator output AM input : - amplitude modulation input MODE2 input : - shutdown/wake-up 1 K output/input (standalone ISO 9141 interface) : - driven by Tx and monitored by Rx 0 K input (standalone ISO 9141 interface) : - monitored by Rx -Tx disabled Standalone 2 wires (VBAT) Direct connection to a MCU © Motorola, Inc., 2002. 2 wires (VDD) B C 0 1 MOTOROLA SEMICONDUCTORS PRODUCTS 9 revision 4.8, 5 February 2002 MC33690 STANDALONE CONFIGURATION WITH ONE WIRE BUS The circuit can be put into standby mode by forcing the K line at zero during more than 2 ms after entering the write mode. Once the K line is released, the circuit sends an acknowledge pulse before entering into standby mode. In standby mode, the oscillator and most of the internal biasing currents are switched off. Therefore, the functions (tag reader, ISO 9141 driver) are inactive except the voltage regulator and the ISO 9141 receiver on pin K. The driver output TD1 forces a low level and TD2 a high level. A rising edge on K wakes up the circuit. After completion of the wake-up sequence, the circuit is automatically set in read mode. In configuration A, DOUT and Rx outputs always force a low level, Tx is disabled. When a low level is applied on pins MODE1 and MODE2, the circuit is in configuration A (standalone single wire bus configuration, see figure 13 page 18). After power on, the circuit is set into read mode. The demodulator output is directly routed to the ISO 9141 interface output K. The circuit can be set into write mode at anytime by violation of all possible patterns on the single wire bus during more than 1ms. Then the K line achieves the amplitude modulation by switching on/off both antenna drivers. After 1ms of inactivity at the end of the challenge phase (bus in idle recessive one state), the circuit is set back into read mode. Figure 6 : Mode access description in one wire bus configuration Read to write mode : T0 ≤ t < T 0 ’+T 1 ’ K line 1 1 1 read mode 0 0 0 write mode Write to read mode : t ≥T0 K line read mode write mode Write to standby mode : t ≥ T1 K line T2 T2 acknowledge write mode standby mode Standby mode to read mode : K line wake-up sequence standby mode read mode Figure 7 : Configuration A state diagram T 0 ≤ K line low write reset read TD1/2 off K line high < T 0 ’ K line low T 0 ≤ K line high write TD1/2 switching T 1 ≤ K line low wake up K © Motorola, Inc., 2002. standby MOTOROLA SEMICONDUCTORS PRODUCTS 10 revision 4.8, 5 February 2002 MC33690 Timing definitions for a 8MHz crystal: - Tref is crystal oscillator period (125 ns typ.) - T0=8064.Tref = 1.008ms typ. - T0’=7932.Tref = 0.992ms typ. - T1=16256.Tref = 2.032ms typ. - T1’=16128.Tref = 2.016ms typ. - T2=4096.Tref, = 512µs typ. T0 is the minimum time required to guarantee that the device toggles from read to write (or from write to read). But indeed, the STARC may toggle from read to write (or from write to read) between T0 and T0’. T1 is the minimum time required to guarantee that the device toggles from write to standby. But indeed, the STARC may toggle in standby between T1 and T1’. © Motorola, Inc., 2002. MOTOROLA SEMICONDUCTORS PRODUCTS 11 revision 4.8, 5 February 2002 MC33690 STANDALONE CONFIGURATION WITH TWO WIRES BUS forcing the AM line at zero during more than 2 ms. The circuit sends an acknowledge pulse before entering into standby mode In standby mode, the oscillator and most of the internal biasing currents are switched off. Therefore, the functions (tag reader, ISO 9141 driver) are inactive except the voltage regulator and the ISO 9141 receiver on pin AM. The driver output TD1 forces a low level and TD2 a high level. A rising edge on AM wakes up the circuit. After completion of the wake-up sequence, the circuit is automatically set in read mode. When a low level is applied on MODE1 and a high level on MODE2, the circuit is in configuration B (standalone 2 wires bus configuration, see figure 14 page 19). The K pin is set as an output sending the demodulated data. The AM pin is set as a VSUP referenced input pin receiving the amplitude modulation and the shutdown/wake-up commands. Forcing high and low levels on AM achieves the amplitude modulation by switching on/off both antenna drivers. Meanwhile, this amplitude modulation can be monitored on the K output. This allows antenna short and open circuit diagnosis. The circuit can be put into standby mode by In configuration B, DOUT and Rx outputs always force a low level, Tx is disabled. Figure 8 : Modes access description in two wires bus configuration Read & write sequences : drivers on data write modulation drivers off 1 1 AM line 1 data read K line 1 1 0 0 1 0 0 0 AM line monitoring Entering into standby mode : AM line 0 data write t ≥ T1 standby mode acknowledge K line T2 T1 T2 Coming out of standby mode : AM line standby mode wake-up sequence data read K line Figure 9 : Configuration B state diagram reset TD1/2 switching AM line low AM line high AM line high TD1/2 off wake up AM line low T1 ≤ AM line low AM © Motorola, Inc., 2002. standby MOTOROLA SEMICONDUCTORS PRODUCTS 12 revision 4.8, 5 February 2002 MC33690 DIRECT CONNECTION TO A MICROCONTROLLER CONFIGURATION When a high level is applied on MODE1, the circuit is in configuration C (direct connection to a microcontroller configuration, see figure 15 page 19). regulator. The driver outputs TD1 and TD2 are frozen in their state (high or low level) before entering into standby mode. DOUT forces a low level. The demodulated data are sent through DOUT. The AM pin is set as a VDD referenced input pin receiving the AM command. Forcing high and low levels on AM achieves the amplitude modulation by switching on/off both antenna drivers. Meanwhile, this amplitude modulation can be monitored on DOUT. This allows antenna short and open circuit diagnosis. The ISO 9141 interface K is standalone and can be directly controlled by the input pin Tx and monitored by the output Rx. Applying a logic high level on Tx switches the output driver K on (dominant zero state when an external pull-up resistor is connected between K and VBAT). Applying a logic low level turns the driver off (one recessive state). Rx monitors the voltage at the K pin. When the voltage is below the low threshold voltage, Rx forces a logic low level. When the voltage is above the high threshold voltage, Rx forces a logic high level. In standby mode, Tx is disabled and Rx output monitors the voltage at the K pin. The circuit can be put into standby mode by applying a low level on the MODE2 pin. In standby mode, the oscillator and most of the internal biasing currents are switched off. Therefore, the functions (tag reader, ISO 9141 interface) are inactive except the voltage Figure 10 : Configuration C state diagram reset TD1/2 switching AM low AM high AM high TD1/2 off wake up AM low mode2 low mode2 low mode2 high standby © Motorola, Inc., 2002. MOTOROLA SEMICONDUCTORS PRODUCTS 13 revision 4.8, 5 February 2002 MC33690 ELECTRICAL CHARACTERISTICS Typical values reflect average measurements at VSUP=12V and TJ=25°C. SUPPLY CURRENT 6V ≤ VSUP ≤ 16V, VSS = 0V, TJ = –40°C to +125°C, unless otherwise noted Test Conditions & Comments Min Typ Max - 300 500 µA 9.2 Operating mode current I SUP2 See note 1 1. Circuit in configuration C, no current sunk from VDD, drivers TD1/2 switched off, Tx forced to low. 1.5 2.5 mA Min Typ Max 4.75 5.0 5.25 V - - 50 mA - 20 60 mV 4.7 5.0 5.3 V - - 150 mA - 65 150 mV Parameter Symbol Unit Type Pin VSUP 9.1 Standby mode current I SUP1 VOLTAGE REGULATOR 6V ≤ VSUP ≤ 16V, VSS = 0V, TJ = –40°C to +125°C, unless otherwise noted Parameter Symbol Test Conditions & Comments Unit Type Pins VSUP & VDD 1.1 Output Voltage (5.5V ≤ V SUP ≤ 40V) V VDD1 1.3 Total Output Current I VDD1 1.5 Load Regulation 1.9 Output Voltage (5.5V ≤ V SUP ≤ 40V) 1.11 Total Output Current 1.6 Load Regulation V LoadReg1 V VDD2 I VDD2 V LoadReg2 Without external MOS transistor I OUT ≤ 50mA Without external MOS transistor 1 to 50mA I OUT change With external MOS transistor, see notes 1 and 2 I OUT ≤ 150mA With external MOS transistor 1 to 150mA I OUT change 1.4 Line Regulation (6V ≤ V SUP ≤ 16V) V LineReg I OUT = 1mA -15 -1 mV 1. The stability is ensured with a decoupling capacitor between VDD and VSS : COUT ≥ 10µF with ESR ≤ 3Ω. 2. The current capability can be increased up to 150mA by using an external N channel MOS transistor (see figure 1 page 2). The main characteristics for choosing this component are : VT < 1.8V and BVDSS > 40V. © Motorola, Inc., 2002. MOTOROLA SEMICONDUCTORS PRODUCTS 14 revision 4.8, 5 February 2002 MC33690 LOW VOLTAGE RESET 6V ≤ VSUP ≤ 16V, VSS = 0V, TJ = –40°C to +125°C, unless otherwise noted Parameter Symbol Test Conditions & Comments Min Typ Max Unit Type 4.1 4.35 4.6 V 50 100 150 mV 15 µA Pin LVR 1.6 Low Voltage Reset Low Threshold 1.7 Low Voltage Reset Hysteresis V LVRH 1.12 Pull-up Current 1.13 Output Resistance in reset condition 1.14 Input Low Voltage V LVRON See note 1 and figure 11 I LVRUP VLVR = 2.5V 5 10 R LVR VLVR = 2.5V 200 370 500 Ω - 0.3 x V DD V V ILLVR 0 0.7 x V DD V V DD 1. As the voltage regulator and the low voltage reset are using the same internal voltage reference, it is ensured that the low voltage reset will only occur when the voltage regulator is out of regulation. 1.15 Input High Voltage V IHLVR Figure 11 : Low voltage reset waveform VDD VLVRON + VLVRH VLVRON LVR OSCILLATOR 6V ≤ VSUP ≤ 16V, VSS = 0V, TJ = –40°C to +125°C, unless otherwise noted Characteristic Symbol Test Condition & Comments Min C XTAL1 V XTAL1 = 2.5V - 5 - pF A OSC V XTAL1 = 2.5V - 25 - - Typ Max Unit Type Pins XTAL1, XTAL2 8.0 Input Capacitance 8.1 Voltage gain V XTAL2 / V XTAL1 1 8.3 Clock input level V XTAL1 1.5 V DD See note Vpp 1. This level ensures the circuit operation with a 8MHz clock. It is applied through a capacitive coupling. A 1MΩ resistor connected between XTAL1 and XTAL2 biases the oscillator input. © Motorola, Inc., 2002. MOTOROLA SEMICONDUCTORS PRODUCTS 15 revision 4.8, 5 February 2002 MC33690 TAG READER 6V ≤ VSUP ≤ 16V, VSS = 0V, TJ = –40°C to +125°C, unless otherwise noted Parameter Symbol Test Conditions & Comments Min Typ Max Unit Type DEMODULATOR (pin RD) 2.0 Input Voltage Range V INRD 3 4 5 V 2.2 Input Modulation Frequency F MOD 0.5 4 8 kHz 2.3 Demodulator Sensitivity V SENSE1 6.5V ≤ V SUP ≤ 16V See figure 12 and note 1 - 5 15 mV 2.31 Demodulator Sensitivity V SENSE2 6V ≤ V SUP < 6.5V See figure 12 and note 1 - 7 30 mV - 7.5 10 µs - 394 400 µs - 646 700 µs - 64 - - - - 250 ns - 2.4 4 Ω 2.4 Demodulation Delay t Demod 2.5 After Write Pulse Settling Time t Settling1 2.6 Recovery Time after wake-up or reset from clock stable to demodulator valid output t Settling2 See figure 12 Configuration C see note 2 for configurations A and B See note 3 DRIVERS (pins TD1, TD2) 3.5 Output Carrier Frequency to Crystal Frequency Ratio R FTD/ FXTAL 3.0 Turn on/off Delay t on/off 3.1 Driver1/2 Low Side Out. Resistance R TDL I LOAD = 150mA DC I LOAD = -150mA DC 2.1 4 Ω 3.2 Driver1/2 High Side Out. Resistance R TDH 1. The sensitivity is measured in the following application conditions : IANTENNA = 50mA peak, VRD = 4V peak, CEXT = 10nF, square wave modulation FMOD=FTD1/32. 2. Not including the delay due to the slew rate of the K output. 3. Clock stable condition implies VXTAL1 meets the specification (see page 15). Figure 12 : Demodulator parameters definition VRD Demodulator output (K or DOUT) © Motorola, Inc., 2002. VSENSE tDemod MOTOROLA SEMICONDUCTORS PRODUCTS 16 revision 4.8, 5 February 2002 MC33690 ISO 9141 INTERFACE 6V ≤ VSUP ≤ 16V, VSS = 0V, TJ = –40°C to +125°C, unless otherwise noted Parameter Symbol Test Conditions & Comments Min Typ Max Unit Type Receiver (pins K & AM) 4.0 Input Low Voltage V IL -3 - 0.3 x V SUP V 4.1 Input High Voltage V IH 0.65 x V SUP - 40 V 4.2 Input Hysteresis Voltage 4.3 Biasing Current 4.31 Input Current 4.4 0.4 0.65 1.3 V IB 0V ≤ V IN ≤ 16V 1 3 5 µA I BM -3 ≤ V IN < 0 -2 -1 - mA 2 10 µs 3.5 5 6.5 V/µs 3.5 5 6.5 V/µs -1 0 1 V/µs V HY1 K to Rx delay tdkrx Driver (pin K) 5.0 Output Falling Edge Slew Rate 5.1 Output Rising Edge Slew Rate SR R Rise Fall Slew Rates Symmetry SR SYME- 5.2 SR F R Pull-up = 510Ω, see note 1 TRY V OLK I LOAD = 25mA - 1.1 1.4 V Input Current (driver switched on or off) I IK -3V ≤ V IN ≤ 0V -2 - 0 mA Current Limitation Threshold IL 0V ≤ V IN ≤ 40V 5.3 Output Low Voltage 5.4 5.5 5.6 Thermal Shutdown Threshold TH SDWN 1. Calculated from 20% to 80% of the output swing. 35 50 65 mA 130 150 170 °C Min Typ Max DIGITAL I/O 6V ≤ VSUP ≤ 16V, VSS = 0V, TJ = –40°C to +125°C, unless otherwise noted Characteristic Symbol Test Condition & Comments Unit Type INPUT (pins MODE1, MODE2, AM, TX) 6.0 Input Low Voltage V ILD 0 - 0.3 x V DD V 6.1 Input High Voltage V IHD 0.7 x V DD - V DD V 6.2 Input Hysteresis Voltage V HD .24 .7 1 V OUTPUT (pins DOUT,RX) 7.0 Output Low Voltage V OL I LOAD = 500uA 0 0.5 0.2 x V DD V 7.1 Output High Voltage V OH I LOAD = -500uA 0.8 x V DD 4.6 V DD V C LOAD =10pF, see note 1 - - 150 ns 7.2 Fall/Rise Time t F/R 1. Calculated from 10% to 90% of the output swing. © Motorola, Inc., 2002. MOTOROLA SEMICONDUCTORS PRODUCTS 17 revision 4.8, 5 February 2002 MC33690 APPLICATION SCHEMES Figure 13 : Standalone configuration with one wire bus VBAT VSUP C1 NC GATE NC SOURCE C2 VSS NC C3 CA LVR VSS XTAL1 TD1 XTAL2 8.2pF 10µ F 100n F RA LA VDD R1 RD R2 TD2 STARC 8MHz 1MΩ 8.2pF MODE1 MODE2 NC CEXT CEXT 10nF AGND Tx DOUT VSUP AM VBAT 510Ω K NC Rx If no external MOS transistor is necessary to increase the voltage regulator current capability, the pins GATE and SOURCE must be left unconnected. In this configuration, the outputs Rx and DOUT force a low level. C1 is not required for the STARC functionality and only acts as a reservoir of energy. To preserve the demodulator sensitivity, CEXT and R2 should be connected to AGND, and VSS connected to AGND using a low resistance path. © Motorola, Inc., 2002. MOTOROLA SEMICONDUCTORS PRODUCTS 18 revision 4.8, 5 February 2002 MC33690 Figure 14 : Standalone configuration with two wires bus VBAT VSUP C1 NC GATE NC SOURCE C2 VSS C3 CA LVR VSS XTAL1 TD1 XTAL2 8.2pF 10µ F 100n F RA LA NC VDD R1 RD R2 TD2 STARC 8MHz 1MΩ MODE1 MODE2 8.2pF VDD VBAT NC CEXT CEXT DOUT 510Ω 10nF AGND Tx NC K AM Rx If no external MOS transistor is necessary to increase the voltage regulator current capability, the pins GATE and SOURCE must be left unconnected. C1 is not required for the STARC functionality and only acts as a reservoir of energy. To preserve the demodulator sensitivity, CEXT and R2 should be connected to AGND, and VSS connected to AGND using a low resistance path. © Motorola, Inc., 2002. MOTOROLA SEMICONDUCTORS PRODUCTS 19 revision 4.8, 5 February 2002 MC33690 Figure 15 : Direct connection to a microcontroller VBAT VSUP C1 NC GATE NC SOURCE To microcontroller power supply pin C2 VSS C3 To microcontroller port/reset pin VDD LVR VSS XTAL1 TD1 XTAL2 RA LA 8.2pF 10u F 100n F R1 R2 CA RD TD2 CEXT CEXT Tx 1MΩ VDD 8.2pF MODE1 MODE2 DOUT 10nF AGND To microcontroller port STARC 8MHz AM To microcontroller port VBAT 510Ω K Rx If no external MOS transistor is necessary to increase the voltage regulator current capability, the pins GATE and SOURCE must be left unconnected. C1 is not required for the STARC functionality and only acts as a reservoir of energy. To preserve the demodulator sensitivity, CEXT and R2 should be connected to AGND, and VSS connected to AGND using a low resistance path. © Motorola, Inc., 2002. MOTOROLA SEMICONDUCTORS PRODUCTS 20 revision 4.8, 5 February 2002 MC33690 Notes © Motorola, Inc., 2002. MOTOROLA SEMICONDUCTORS PRODUCTS 21 revision 4.8, 5 February 2002 MC33690 Notes © Motorola, Inc., 2002. MOTOROLA SEMICONDUCTORS PRODUCTS 22 revision 4.8, 5 February 2002 MC33690 Notes © Motorola, Inc., 2002. MOTOROLA SEMICONDUCTORS PRODUCTS 23 revision 4.8, 5 February 2002 MC33690 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. All other product or service names are the property of their respective owners. © Motorola, Inc. 2002 HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution: P.O. 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