L5962 Multiple linear/switching voltage regulator for car-radio Features ■ ■ ■ Step-down synchronous switching voltage regulator – Internal high-side/ Low-side NDMOS – 1.2 < Vout < 8 V selectable through external resistors – 1.2/2.5 A load current selected through dedicated pin – 185 kHz free-run frequency – SYNC function (220 < fsw < 400 kHz) Linear regulators – 3.3/5 V @ 150 mA standby regulator selected through dedicated pin (VSTBYSEL) – 5/8.5 V @ 350 mA switched linear regulator enabled and selected through I2C bus (VLR1) – 3.3/10 V @ 1 A switched linear regulator enabled and selected through I2C bus (VLR2) 2 High side drivers (0.5 V max drop @ 0.5 A) enabled through I2C bus and equipped with protection circuit against: – short to ground and battery – loss of ground and battery – unsupplied short to battery ■ Reset function with configurable delay (RST, RSTDLY) ■ I2C bus Table 1. PowerSO36 (slug-up) ■ Enable pin to drive switching regulator and I2C bus logic ■ Under/over voltage battery detector (VBATVW) – Under voltage threshold adjustable through dedicated pin (LVWIN) ■ Load dump protection ■ Independent thermal protection on all regulators Description L5962 is a very versatile device exploiting BCD technology characteristics to provide a complete set of regulated voltages covering all the needs of a car-radio set. In standby condition the device guarantees extremely low quiescent current (90 µA max 40 °C < T < 85 °C) and minimum operating voltage (4.5 V using an external Schottky diode for the back-up function). Device summary Order code Package Packing L5962 PowerSO36 Tray L5962TR PowerSO36 Tape and reel December 2009 Doc ID 16819 Rev 2 1/24 www.st.com 1 Contents L5962 Contents 1 Block and application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 4.2 5 4.1.1 Linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1.2 Switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 High side drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 6 Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Battery detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.2 Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 Software specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2/24 Doc ID 16819 Rev 2 L5962 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chip address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 IB1 data byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 VLR2 output level selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Doc ID 16819 Rev 2 3/24 List of figures L5962 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. 4/24 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Low voltage warning high level block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Data validity on the I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Timing diagram on the I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Acknowledge on the I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PowerSO36 (slug-up) mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . 22 Doc ID 16819 Rev 2 L5962 1 Block and application diagram Block and application diagram Figure 1. Block diagram VINSW VBATP Bandgap External Storage Reference PH Switching Regulator POR & Startup Logic CBS CLIM VFB VCMP SOST Standby Regulator Oscillator SYNCH LVWIN VBATVW RST RSTDLY VSTBYSEL VSTBY Clock UV / OV Detect Linear Regulator #1 Synch Logic Reset & Delay Linear Regulator #2 SDA SCL I2Cbus Logic VLR1 VINLR2 VLR2 HSD HSD1 HSD HSD2 EN Ground AC00428 TAB PGND AGND SUBS Doc ID 16819 Rev 2 VBAT 5/24 6/24 22K Doc ID 16819 Rev 2 0.1µ VLR2 2.7nF 3.3nF 1µ 0.1µ 1µ VLR1 VSTBY 10K RESET 1.8nF 75k 22k/(VDCOUT-1) S2 VBATW SCL SDA EN R2 R1 VBAT VSTBY 10K +5V 47K SYNC 47K S1 L5962 NC 18 19 NC 0.1µ NC 17 AGND 16 20 NC 21 LVWIN VSTBYS 15 VSTBY 14 23 VLR1 22 VBATW RSTDLY 13 VBATP 12 HSD2 11 VBAT 10 HSD1 9 VINsw 8 24 SDA 25 VINLR 26 VLR2 27 RESET 28 EN 29 SCL SUBGND 7 NC 6 30 SYNC NC 5 31 SOST PHASE 4 33 VFB 32 VCMP CBS 3 35 NC 34 CLIM TAB 1 PGND 2 36 NC S3 0.1µF 1µ VSTBY 30µ/35V 0.1µ 0.1µ 0.1µ 200u/10V 470µ/25V 4.7µ 1500pF 22 22µH HSD2 HSD1 2.2µ VBAT VDCOUT Figure 2. 470 +5V Block and application diagram L5962 Application diagram 1000u/50V 0.1µ L5962 2 Pin description Pin description Figure 3. Pin connection (top view) N.C. 36 1 TAB N.C. 35 2 PGND CLIM 34 3 CBS VFB 33 4 PH VCMP 32 5 N.C. SOST 31 6 N.C. SYNC 30 7 SUBGND SCL 29 8 VINsw EN 28 9 HSD1 RST 27 10 VBAT VLR2 26 11 HSD2 VINLR2 25 12 VBATP SDA 24 13 RSTDLY VLR1 23 14 VSTBY VBATW 22 15 VSTBYSEL LVWIN 21 16 AGND N.C. 20 17 N.C. N.C. 19 18 N.C. AC00429 Table 2. Pin description Pin # Pad name 1 TAB 2 PGND 3 CBS 4 Function Description This pin must be connected to GND Switching regulator ground It is the power ground reference Bootstrap for switching regulator Bootstrap capacitor Input for the switching regulator PH Switching stage output Phase output. It is the switching output of the switching regulator. It also provides phase reference for bootstrap drive. 5 N.C. Not connected - 6 N.C. Not connected - 7 SUBGND Substrate ground Substrate ground 8 VINsw Switching regulator supply voltage Battery voltage for the switching regulator 9 HSD1 High side driver 1 Output of the 1st high side driver 10 VBAT VLR1/HSD1/HSD2 supply voltage Voltage input for linear regulator #1 high side driver and battery warnings 11 HSD2 High side driver 2 Output of the 2nd high side driver 12 VBATP Standby regulator supply voltage Protected battery input for bias, bandgap, oscillator, and VSTBY regulator 13 RSTDLY Reset delay function Input 14 VSTBY Standby regulator output Output of the standby regulator Doc ID 16819 Rev 2 7/24 Pin description Table 2. Pin # 15 L5962 Pin description (continued) Pad name Function VSTBYSEL Standby regulator selector Description Selection input for standby regulator output (3.3 V or 5 V) 16 AGND Analog ground Analog voltage reference 17 N.C. Not connected - 18 N.C. Not connected - 19 N.C. Not connected - 20 N.C. Not connected - 21 LVWIN Battery detector adjustment input Low-voltage warning input 22 VBATW Battery detector output (open-drain) Battery voltage warning output 23 VLR1 Switched linear regulator 1 Output of the 1st linear regulator 24 SDA I2C bus data I2C data line 25 VINLR2 VLR2 supply voltage Battery supply for the 2nd linear regulator 26 VLR2 Switched linear regulator 2 Output of the 2nd linear regulator 27 RST Reset Output 28 EN Enable Active mode enable input. Active high 29 SCL I2C bus clock I2C clock source supplied by the master device 30 SYNC Switching regulator SYNC function Synchronization Input 31 SOST Switching regulator soft-start Soft start external capacitor 32 VCMP Switching regulator compensation Feedback compensation input. 33 VFB Switching regulator feedback Regulated output voltage sense 34 CLIM Switching regulator current limit selector Choose between two current limits 35 N.C. Not connected - 36 N.C. Not connected - 8/24 Doc ID 16819 Rev 2 L5962 Electrical specification 3 Electrical specification 3.1 Absolute maximum ratings Table 3. Absolute maximum ratings Pin name/Symbol VsMAX VpinMAX AGND, PGND, SUBGND, TAB 3.2 Parameter Value Unit Operating supply voltage (VBAT, VBATP, VINSW, VINLR2) -0.3 to 27 V Transient supply voltage (VBAT, VBATP, VINSW, VINLR2) -0.3 to 50 V Input pin voltage (EN, RSTDLY, VSTBYSEL, SYNCH, SCL, SDA, VCMP, VFB, CLIM, SOST) -0.3 to 6 V -0.3 to +0.3 V Ground pin voltage Top Operating temperature range -40 to 85 °C Tstg Storage temperature range -55 to 150 °C Value Unit 2 °C/W Thermal data Table 4. Thermal data Symbol Rth j-case 3.3 Parameter Thermal resistance junction-to-case (max) Electrical characteristics VBAT= VINSW = VINLR2 = 14.4 V, Tamb = 25 °C unless otherwise specified. Table 5. ( Electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit 4.1 - - V - - 90 75 µA 27 29 31 V Input supplies Vmin VBATP operating voltage - Iq Total quiescent current EN = 0; IVSTBY=100 µA @ T = -40 °C @ 25 °C < T < 85 °C VOV Overvoltage shut-down VBAT rising Hysteresis on VOV - - 400 - mV VBAT undervoltage threshold VBAT falling; VBATVW transition to 0 V 7 7.5 8 V HYSOV VUV Doc ID 16819 Rev 2 9/24 Electrical specification Table 5. L5962 Electrical characteristics (continued) Symbol HYSUV Parameter Test conditions Min. Typ. Max. Unit - 1 - V Hysteresis on VUV - VoutVSTBY3 Output voltage 0 < Iload < 150 mA 3.2 3.3 3.4 V LnRVSTBY3 Line regulation 4.1 <VBATP<18V Iload=150mA -10 - +50 mV LdRVSTBY3 Load regulation 0<Iload<150mA - - 20 mV VdoVSTBY3 Drop out voltage Iload=150mA - - 600 mV 250 - 450 mA - - ±5 % VSTBY (3.3 V) IshortVSTBY3 Short circuit current limit - OS/USVSTBY3 Overshoot/Undershoot Iload 0 ↔ 150 mA, t > 50µs C = 1 µF ceramic PSRRVSTBY3 Power supply rejection ratio Iload = 50 mA 120 Hz < f < 10 kHz VBATPac = 1 Vpp 70 - - dB Output noise A-weighted filter 20 Hz < f < 20 kHz Iload = 5 mA - - 200 µV Thermal shut-down temperature Temperature rising 150 - 190 °C Hysteresis on thermal shutdown temperature - 5 - 15 °C - - 0.2 Ω nVSTBY3 TSVSTBY3 HYSTS-VSTBY3 ESRVSTBY3 External filtering capacitor ESR C > 0.5 µF VSTBY (5 V) VoutVSTBY5 Output voltage 0 < Iload < 150 mA 4.80 5 5.15 V LnRVSTBY5 Line regulation 6<VBATP<18V Iload=150mA -10 - +60 mV LdRVSTBY5 Load regulation 0 < Iload < 150 mA - - 25 mV VdoVSTBY5 Drop out voltage Iload = 150 mA - - 600 mV 250 - 450 mA - - ±5 % IshortVSTBY5 Short circuit current limit - OS/USVSTBY5 Overshoot/Undershoot Iload 0 ↔ 150 mA, t > 50µs C = 1 µF ceramic PSRRVSTBY5 Power supply rejection ratio Iload = 50 mA 120 Hz < f < 10 kHz VBATPac=1 Vpp 70 - - dB A-weighted filter 20 Hz < f < 20 kHz Iload = 5 mA - - 200 µV 150 - 190 °C 5 - 15 °C - - 0.2 Ω nVSTBY5 TSVSTBY5 HYSTSVSTBY5 ESRVSTBY5 10/24 Output noise Thermal shut-down temperature Temperature rising Hysteresis on thermal shutdown temperature - External filtering capacitor ESR C > 0.5 µF Doc ID 16819 Rev 2 L5962 Table 5. Electrical specification Electrical characteristics (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit VLR1 (5 V) VoutVLR1-5 Output voltage 0 < Iload < 350 mA 4.85 5 5.15 V LnRVLR1-5 Line regulation 6<VBAT<18 V Iload =350 mA -25 - +25 mV LdRVLR1-5 Load regulation 0 < Iload < 350 mA -90 - - mV VdoVLR1-5 Drop out voltage Iload = 350 mA - - 650 mV Short circuit current limit - 500 650 850 mA - - ±3 % IshortVLR1-5 OS/USVLR1-5 Overshoot/Undershoot Iload 0 ↔ 350 mA, t > 50µs C = 1 µF ceramic PSRRVLR1-5 Power supply rejection ratio Iload = 170 mA 120 Hz < f < 10 kHz VBATac=1 Vpp 60 - - dB Output noise A-weighted filter 20 Hz < f < 20 kHz Iload = 5 mA - - 350 µV Thermal shut-down temperature Temperature rising 150 - 190 °C Hysteresis on thermal shutdown temperature - 5 - 15 °C - - 0.2 Ω nVLR1-5 TSVLR1-5 HYSTS-VLR1-5 ESRVLR1-5 External filtering capacitor ESR C > 0.5 µF VLR1 (8.5 V) VoutVLR1-8 Output voltage 0 < Iload < 350 mA 8.3 8.5 8.7 V LnRVLR1-8 Line regulation 9.6<VBAT<18VIload=350mA -25 - +25 mV LdRVLR1-8 Load regulation 0 < Iload < 350 mA -90 - - mV VdoVLR1-8 Drop out voltage Iload = 350 mA - - 650 mV Short circuit current limit - 500 650 850 mA - - ±3 % IshortVLR1-8 OS/USVLR1-8 Overshoot / undershoot PSRRVLR1-8 nVLR1-8 TSVLR1-8 HYSTS-VLR1-8 ESRVLR1-8 Iload 0 ↔ 350 mA, t > 50µs C = 1 µF ceramic Power supply rejection ratio Iload = 170 mA 120 Hz < f < 10 kHz VBATac=1 Vpp 60 - - dB Output noise A-weighted filter 20 Hz < f < 20 kHz Iload = 5 mA - - 350 µV Thermal shut-down temperature Temperature rising 150 - 190 °C Hysteresis on thermal shutdown temperature - 5 - 15 °C - - 0.2 Ω External filtering capacitor ESR C > 0.5 µF Doc ID 16819 Rev 2 11/24 Electrical specification Table 5. L5962 Electrical characteristics (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit VLR2 (3.3 V) VoutVLR2-3 Output voltage 0 < Iload < 1 A 3.2 3.3 3.4 V LnRVLR2-3 Line regulation 4.5 < VINLR2 < 18 V Iload = 1 A -20 - +20 mV LdRVLR2-3 Load regulation 0 < Iload < 1 A -70 - - mV VdoVLR2-3 Drop out voltage Iload = 1 A - - 1.2 V 1.5 - 2.5 A - - ±3 % 60 - - dB - - 350 µV 150 - 190 °C 5 - 15 °C - - 0.2 Ω IshortVLR2-3 Short circuit current limit OS/USVLR2-3 Overshoot / undershoot PSRRVLR2-3 nVLR2-3 TSVLR2-3 HYSTS-VLR2-3 ESRVLR2-3 Iload 0 ↔ 1A, t > 50µs C = 1 µF ceramic Power supply rejection ratio Iload = 500 mA 120 Hz < f < 10 kHz VINLR2ac=1 Vpp Output noise A-weighted filter 20Hz<f<20kHz Iload=5mA Thermal shut-down temperature Temperature rising Hysteresis on thermal shutdown temperature - External filtering capacitor ESR C>0.5µF VLR2 (10 V) VoutVLR2-10 Output voltage 0<Iload<1 A 9.7 10 10.3 V LnRVLR2-10 Line regulation 11.4<VBAT<18 V Iload=1 A -25 - +25 mV LdRVLR2-10 Load regulation 0<Iload<1 A -70 - - mV VdoVLR2-10 Drop out voltage Iload=1 A - - 0.75 V 1.5 - 2.5 A - - ±3 % IshortVLR2-10 Short circuit current limit OS/USVLR2-10 Overshoot / undershoot Iload 0 ↔ 1 A, t > 50 µs C = 1 µF ceramic PSRRVLR2-10 Power supply rejection ratio Iload = 500 mA 120 Hz<f<10 kHz VINLR2ac=1 Vpp 60 - - dB Output noise A-weighted filter 20 Hz < f < 20 kHz Iload = 5 mA - - 350 µV Thermal shut-down temperature Temperature rising 150 - 190 °C Hysteresis on thermal shutdown temperature - 5 - 15 °C - - 0.2 Ω nVLR2-10 TSVLR2-10 HYSTS-VLR2-10 ESRVLR2-10 12/24 External filtering capacitor ESR C > 0.5 µF Doc ID 16819 Rev 2 L5962 Electrical specification Table 5. Electrical characteristics (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit HSD1 VdropHSD1 Output saturation Iload = 0.5 A - - 500 mV IleakHSD1 Leakage current HSD off output shorted to GND - - 10 µA IshortHSD1 Short circuit current limit - 0.75 - 1.5 A Thermal shut-down temperature Temperature rising 150 - 190 °C Hysteresis on thermal shutdown temperature - 5 - 15 °C VdropHSD2 Output saturation Iload = 0.5 A - - 500 mV IleakHSD2 Leakage current HSD off output shorted to GND - - 10 µA IshortHSD2 Short circuit current limit - 0.75 - 1.5 A Thermal shut-down temperature Temperature rising 150 - 190 °C Hysteresis on thermal shutdown temperature - 5 - 15 °C 1.2 - 8 V TSHSD1 HYSTS-HSD1 HSD2 TSHSD2 HYSTS-HSD2 Switching regulator Output voltage Selectable through external resistor divider Load current limitation VoutSW decreasing of 100 mV (1) CLIM = 0 V CLIM = 5 V 1.2 2.5 fsw Free-run switching frequency - 150 180 210 kHz VFB FB voltage - 970 - 1030 mV Dropout voltage VoutSW = 8 V IloadSW = 2.5 A(1) - - 1.2 V 220 - 400 kHz 85 - - % VoutSW ILOADmaxSW VdropSW fSYNC Switching frequency selectable through SYNC pin - 3 6 A Efficiency free run frequency (1) VoutSW = 8 V; Iload = 2.5 A SRSS Soft-start pin slew rate CSOST = 10 nF (1) - - 10 V/ms TSSW Thermal shut-down temperature Temperature rising 150 - 190 °C Hysteresis on thermal shutdown temperature - 5 - 15 °C η HYSSW Doc ID 16819 Rev 2 13/24 Electrical specification Table 5. L5962 Electrical characteristics (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit Reset function THRRST Reset threshold on VSTBY VSTBY = 3.3 V 93 - 98 % HYSRST Hysteresis on RST - 30 - 150 mV VsatRST RST pin saturation voltage IRST = 0.5 mA - - 0.4 V DLYRST RST delay time C = 100 pF on RSTDLY pin 25 - 75 µs TfallRST RST fall time R = 47 kΩ C = 50 pF - - 1 µs TglitchRST Glitch filter time for RST - 5 - 20 µs THRRSTDLY RSTDLY pin threshold RST falling 3 - 3.7 V IRSTDLY RSTDLY output current RSTDLY = Off 7 - 13 µA EN minimum level recognized as high - 2 - - V EN maximum level recognized as low - - 0.8 V HYSEN Hysteresis on EN - 150 - - mV leakEN EN pin leakage current - -1 - 1 µA - 0.8 - - - 2 Controls THREN THRCLIM CLIM pin threshold leakCLIM CLIM pin leakage current - -1 - 1 µA THRLVWIN LVWIN threshold - 1.225 - 1.275 V HYSTLVWIN LVWIN hysteresis - 100 - 200 mV CLOCK minimum level recognized as High - 2.2 - - V CLOCK maximum level recognized as low - - - 0.8 V DATA minimum level recognized as High - 2.2 - - V DATA maximum level recognized as low - - - 0.8 V Clock frequency - - - 400 kHz V - I2C bus THRSCL THRSDA fSCL 1. by bench characterization 14/24 Doc ID 16819 Rev 2 L5962 4 Device description Device description The IC includes one standby regulator, always active to guarantee the standby functions; two switched linear regulators, managed by the I2C bus and a step-down switching voltage regulator with selectable current limit. 4.1 Regulators The VSTBY regulator is always active when the IC is supplied. The other regulators can be enabled or disabled. Their outputs are automatically disabled whenever the VBAT voltage exceeds the over-voltage shutdown threshold. Upon return from over-voltage shutdown, the outputs recover without intervention from the system. 4.1.1 Linear regulators VSTBY (3.3 V / 5.0 V standby) VSTBY is a linearly regulated 3.3/5 V output. This output is enabled on battery connect. It is supplied from the protected battery input (VBATP). In order to select the 3.3 V output, the VSTBYSEL pin must be connected to ground. In order to select the 5.0 V output, the VSTBYSEL pin must be connected to 5 V. When the dropout voltage of the regulator cannot be maintained, the output shall track the VBATP input voltage less the saturation voltage of the regulator pass element. This regulator has a short circuit protection consisting of current limit, and thermal shutdown. If the local die temperature exceeds the thermal shutdown detection threshold, the output is disabled. The thermal shutdown circuitry has hysteresis such that the output is enabled only after the die temperature falls below the thermal shutdown disable threshold. Thermal shutdown on this output doesn't directly disable any other circuitry. RST provides an indication that VSTBY is in regulation. It is an open drain output used to indicate that VSTBY is in regulation (below the low-voltage threshold). RST remains low until VSTBY achieves regulation and the RSTDLY input has charged to its threshold. For instance, RST remains low during battery connect and disconnect and under low-voltage battery lockout. The transition from standby mode to active mode (and vice versa) does not cause the RST output to be triggered. RSTDLY provides a means to delay the releasing of RST once VSTBY has achieved regulation. It is used to delay the release of RST when VSTBY achieves regulation. This input has a current source to charge an external capacitor and an internal pull-down to discharge the external capacitor. The voltage on this capacitor is used to control the operation of the RST output. The RSTDLY pull-down is activated when a loss of regulation is detected. The input remains low until VSTBY once again achieves regulation. When the RSTDLY is released the current source charges the external capacitor. When the voltage exceeds the pin's threshold, RST pin is also released, disabling its pull-down. Doc ID 16819 Rev 2 15/24 Device description L5962 VLR1 (5.0 V /8.5 V) and VLR2 (3.3 V, 5.0 V, 5.5 V, 6.0 V, 7.0 V, 7.5 V, 8.0 V, 10.0 V) The output of these two regulators can be selected through the I2C bus. When the dropout voltage of the regulator cannot be maintained, the output tracks the VBAT input voltage less the saturation voltage of the regulator pass element. This regulator has a short circuit protection consisting of current limit and thermal shutdown. If the local die temperature exceeds the thermal shutdown detection threshold, the output is disabled. The thermal shutdown circuitry has hysteresis such that the output is enabled only after the die temperature falls below the thermal shutdown disable threshold. Thermal shutdown on this output doesn't directly disable any other circuitry. VLR2 has its own power supply (VINLR2) because of its high current capability. 4.1.2 Switching regulator The IC contains an independent, step-down, synchronous switching regulator, which is used to produce an output voltage that is adjustable in the system by means of an external resistor divider. The switching regulator functionality is guaranteed in the 1.2-8.0 V output voltage range. The switching frequency is externally synchronizable. The switcher has its own supply input pin (VINSW) and is enabled by the EN input. The regulator contains soft-start control to protect external devices from excessive in-rush currents. This control is independent of the presence of a synchronizing signal on the SYNCH input. The switching cycle is synchronized to the internal oscillator unless a signal is present on the SYNC input. The signal present on the SYNCH input overrides the internal oscillator to control the switching of the regulator if its frequency gets inside the allowed range (220400 kHz). The IC detects a small number of edges (e.g. 2-5) prior to recognize a valid input signal and synchronizing internal operation to the external signal. It is designed to operate in continuous conduction mode (CCM), where the inductor current remains continuous throughout the entire load range of the output. It can also work in DCM mode. This regulator has short circuit protection consisting of cycle-by-cycle duty-cycle limitation. Upon return from over-voltage shutdown this regulator employs the soft-start. An external bootstrap capacitor must be connected between the output (PH, phase output pin) and the CBS pin. The switching regulator output slew rate can be controlled with an external capacitor on the SOST (soft start) pin. This protects the device against excessive dV/dt transients, lowering the stress of the internal components. A maximum slews rate of 10 V/ms is suggested. Two separate current limits for the switching regulator can be chosen in order to guarantee a proper protection for the device at the desired load current rating. The CLIM pin should be tied to ground for the low limit (max 3 A) or to 5.0 V for the high limit (max 6 A). The VFB pin is the voltage feedback from the regulated output for the switching regulator; the VCMP one is the compensation feedback for the switching regulator. 16/24 Doc ID 16819 Rev 2 L5962 4.2 Device description High side drivers The device embeds fully-protected high-side drivers for use outside of the car-radio module. HSD1, HSD2 These high side driver outputs have short circuit protections consisting of current limit and independent thermal shutdown. If the local die temperature exceeds the thermal shutdown detection threshold, the output is disabled. The thermal shutdown circuitry has hysteresis such that the output is enabled only after the die temperature falls below the thermal shutdown disable threshold. Thermal shutdown on any one output doesn't directly disable any other circuitry. HSD1 and HSD2 are protected from shorts to ground and shorts to battery (0-18 V) during a loss of car-radio module battery. Doc ID 16819 Rev 2 17/24 Operating mode 5 L5962 Operating mode When a power source is connected to the IC, the internal circuitry begins to establish internal bias, the bandgap reference voltage, and other related functions. The standby (VSTBY) regulator and battery detection are functional. The standby mode is activated when the enable (EN) input is asserted low. When the enable (EN) input is set high (EN =1: active mode.), the IC exits the standby mode and enters the active mode. During active mode, I2C interface is activated and all functions are operational. The IC remains in active mode until either the standby regulator falls out of regulation (where the IC enters the low-voltage reset state) or until the enable (EN) input is brought back to 0 V (where the IC enters the standby state). 5.1 Battery detection The operating voltage for VLR1, high side drivers and battery warnings is provided by VBAT pin. This input is also used as reference to detect an over-voltage or an under-voltage condition. When such condition is detected, the VBATVW output is pulled down. The overvoltage detection circuit has hysteresis for noise rejection. Two external resistors (Rext1, Rext2), whose values are lower than 100 kohm, are connected to the LWIN (low warning input) pin to give the possibility to trim the threshold at which the low voltage warning comparator triggers. When LVWIN voltage is below the input voltage threshold (1.25 V typ), the VBATW (battery voltage warning) output is pulled down and a low-voltage warning is indicated. When no external resistor network is connected to LVWIN, the detector sets the threshold to a nominal 7.5 V. No external interaction is required to reset the output state, because it is automatically reset when the fault condition is removed. Figure 4 shows an high level block diagram of the low-voltage warning circuit. VBAT is divided by two internal resistors (Rint1, Rint2) and two external programming resistors (Rext1, Rext2). When VBAT decreases so that LVWIN voltage gets lower than the internal reference (VBG), VBATW is pulled down to ground. Figure 4. Low voltage warning high level block diagram VBAT VBATW Rext1 LVWIN Rint1 =13.89 M ohm comparator VBG Rext2 18/24 Rint2 = 2.83 M ohm Doc ID 16819 Rev 2 I2C bus interface L5962 6 I2C bus interface Data transmission from microprocessor to the L5962 and viceversa takes place through the 2 wires I2C bus interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). 6.1 Data validity As shown by Figure 5, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. 6.2 Start and stop conditions As shown by Figure 6 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. 6.3 Byte format Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. 6.4 Acknowledge The transmitter* puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see Figure 6). The receiver** the acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDAline is stable LOW during this clock pulse. * Transmitter – master (µP) when it writes an address to the L5962 – slave (L5962) when the µP reads a data byte from L5962 ** Receiver – slave (L5962) when the µP writes an address to the L5962 – master (µP) when it reads a data byte from L5962 Figure 5. Data validity on the I2C bus SDA SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED Doc ID 16819 Rev 2 D99AU1031 19/24 I2C bus interface L5962 Figure 6. Timing diagram on the I2C bus SCL I2CBUS SDA D99AU1032 START Figure 7. STOP Acknowledge on the I2C bus SCL 1 2 3 7 8 9 SDA MSB START 20/24 D99AU1033 Doc ID 16819 Rev 2 ACKNOWLEDGMENT FROM RECEIVER L5962 7 Software specifications Software specifications Table 6. Chip address D7 (MSB) D0 (LSB) 0 0 0 1 0 0 0 R/W 10 Hex IC functions can be driven sending one data byte IB1 Table 7. IB1 data byte Bit position Bit name Function description D7 VLR2EN VLR2 enable D6 VLR2SEL2 VLR2 selection D5 VLR2SEL1 D4 VLR2SEL0 D3 VLR1EN VLR1 enable D2 VLR1SEL VLR1 selection D1 HSD2EN HSD2 enable D0 HSD1EN HSD1 enable Bits D6-D4 are used to select VLR2 output voltage according to the following table Table 8. VLR2 output level selection VLR2SEL2 VLR2SEL1 VLR2SEL0 VLR2 output voltage 0 0 0 3.3V 0 0 1 5.0V 0 1 0 5.5V 0 1 1 6.0V 1 0 0 7.0V 1 0 1 7.5V 1 1 0 8.0V 1 1 1 10.0V Doc ID 16819 Rev 2 21/24 Package information 8 L5962 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 8. PowerSO36 (slug-up) mechanical data and package dimensions DIM. A A2 A4 A5 a1 b c D D1 D2 E E1 E2 E3 E4 e e3 G H h L N s MIN. 3.270 3.100 0.800 0.030 0.220 0.230 15.800 9.400 13.900 10.900 5.800 2.900 0 15.500 0.800 - mm TYP. 0.200 1.000 0.650 11.050 - MAX. 3.410 3.180 1.000 -0.040 0.380 0.320 16.000 9.800 14.500 11.100 2.900 6.200 3.200 0.075 15.900 1.100 1.100 10˚ 8˚ MIN. 0.1287 0.1220 0.0315 0.0012 0.0087 0.0091 0.6220 0.3701 0.5472 0.4291 0.2283 0.1142 0 0.6102 0.0315 - inch TYP. 0.0079 0.0394 0.0256 0.4350 - MAX. 0.1343 0.1252 0.0394 -0.0016 0.0150 0.0126 0.6299 0.3858 0.5709 0.4370 0.1142 0.2441 0.1260 0.0031 0.6260 0.0433 0.0433 10˚ 8˚ OUTLINE AND MECHANICAL DATA PowerSO36 (SLUG UP) (1) “D and E1” do not include mold flash or protusions. Mold flash or protusions shall not exceed 0.15mm (0.006”). (2) No intrusion allowed inwards the leads. 7183931 G 22/24 Doc ID 16819 Rev 2 L5962 9 Revision history Revision history Table 9. Document revision history Date Revision Changes 24-Nov-2009 1 Initial release. 10-Dec-2009 2 Updated Figure 8: PowerSO36 (slug-up) mechanical data and package dimensions on page 22. Doc ID 16819 Rev 2 23/24 L5962 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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