MAXIM MAXQ2000-RBX

Rev 2; 12/04
Low-Power LCD Microcontroller
Features
The MAXQ2000 microcontroller is a low-power, 16-bit
device that incorporates a liquid-crystal display (LCD)
interface that can drive up to 100 (-RBX) or 132 (-RAX)
segments. The MAXQ2000 is uniquely suited for the
blood-glucose monitoring market, but can be used in
any application that requires high performance and lowpower operation. The device can operate at a maximum
of either 14MHz (VDD > 1.8V) or 20MHz (VDD > 2.25V).
The MAXQ2000 has 32kWords of flash memory, 1kWord
of RAM, three 16-bit timers, and one or two universal
synchronous/asynchronous receiver/transmitters
(UARTs). Flash memory aids prototyping and low-volume production. The microcontroller core is powered by
a 1.8V supply, with a separate I/O supply for optimum
flexibility. An ultra-low-power sleep mode makes these
parts ideal for battery-powered, portable equipment.
♦ High-Performance, Low-Power, 16-Bit RISC Core
DC to 20MHz Operation, Approaching 1MIPS per MHz
Dual 1.8V Core/3V I/O Enables Low Power/Flexible
Interfacing
33 Instructions, Most Single Cycle
Three Independent Data Pointers Accelerate Data
Movement with Automatic Increment/Decrement
16-Level Hardware Stack
16-Bit Instruction Word, 16-Bit Data Bus
16 x 16-Bit, General-Purpose Working Registers
Optimized for C-Complier (High-Speed/Density Code)
♦ Program and Data Memory
32kWords Flash Memory, Mask ROM for HighVolume Applications
10,000 Flash Write/Erase Cycles
1kWord of Internal Data RAM
JTAG/Serial Boot Loader for Programming
♦ Peripheral Features
Up to 50 General-Purpose I/O Pins
100/132 Segment LCD Driver
Up to 4 COM and 36 Segments
Static, 1/2, and 1/3 LCD Bias Supported
No External Resistors Required
SPITM and 1-Wire® (-RAX Only) Hardware I/O Ports
One or Two Serial UARTs
One-Cycle, 16 x 16 Hardware Multiply/Accumulate
with 48-Bit Accumulator
Three 16-Bit Programmable Timers/Counters
8-Bit, Subsecond, System Timer/Alarm
32-Bit, Binary Real-Time Clock with Time-of-Day Alarm
Programmable Watchdog Timer
♦ Flexible Programming Interface
Bootloader Simplifies Programming
In-System Programming Through JTAG
Supports In-Application Programming of Flash Memory
♦ Ultra-Low Power Consumption
190µA typ at 8MHz Flash Operation, PMM1 at 2.2V
700nA typ in Lowest Power Stop Mode
Low-Power 32kHz Mode and Divide-by-256 Mode
Applications
Medical Instrumentation
Battery-Powered and Portable Devices
Electrochemical and Optical Sensors
Industrial Control
Data-Acquisition Systems and Data Loggers
Home Appliances
Consumer Electronics
Thermostats/Humidity Sensors
Security Sensors
Gas and Chemical Sensors
HVAC
Smart Transmitters
Typical Operating Circuit and Pin Configurations appear at
end of data sheet.
Ordering Information
TEMP RANGE
PROGRAM
MEMORY
DATA
MEMORY
LCD
SEGMENTS
EXTERNAL
INTERRUPTS
UARTS
MAXQ2000-RAX
-40°C to +85°C
32kWord Flash
1kWord SRAM
132
16
2
68 QFN
MAXQ2000-RBX
-40°C to +85°C
32kWord Flash
1kWord SRAM
100
14
1
56 TQFN
PART
PINPACKAGE
MAXQ is a trademark of Maxim Integrated Products, Inc.
SPI is a trademark of Motorola, Inc.
1-Wire is a registered trademark of Dallas Semiconductor Corp.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of
any device may be simultaneously available through various sales channels. For information about device errata, go to:
www.maxim-ic.com/errata.
______________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAXQ2000
General Description
MAXQ2000
Low-Power LCD Microcontroller
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to
Ground Except VDD .................................-0.5V to (VDDIO + 0.5)V
Voltage Range on VDD Relative to Ground .........-0.5V to +2.75V
Voltage Range on VDDIO Relative to Ground........-0.5V to +3.6V
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Soldering Temperature ....................See IPC/JEDEC J-STD-020
.................................................................................Specification
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = VDD(MIN) to VDD(MAX), VDDIO = 2.7V to 3.6V, TA = -40°C to +85°C.) (Note 1)
PARAMETER
Core Supply Voltage
I/O Supply Voltage
Active Current,
fHFIN = 14MHz
(Note 2)
Active Current,
fHFIN = 20MHz
(Note 2)
SYMBOL
VDD
TYP
MAX
1.8
2.5
2.75
Flash programming
2.25
2.5
2.75
VDD
3.6
IDD1
/1 mode
6.0
9.2
IDD2
/2 mode
5.6
8.6
IDD3
/4 mode
3.4
5.1
IDD4
/8 mode
1.9
2.9
0.7
UNITS
V
V
mA
IDD5
PMM1 mode
0.5
IDD6
PMM2 mode; 32KIN = 32.768kHz
4.8
7.6
IDD1
/1 mode
6.5
10.4
IDD2
/2 mode
5.9
9.6
IDD3
/4 mode
3.8
6.2
IDD4
/8 mode
2.2
3.8
IDD5
PMM1 mode
0.6
1.4
IDD6
PMM2 mode; 32KIN = 32.768kHz
4.8
8.1
Execution from flash memory, 20MHz,
VDD = 2.2V, TA = +25°C
5.1
Execution from flash memory, 8MHz,
/8 mode, VDD = 2.2V, TA = +25°C
0.85
Execution from flash memory, 8MHz,
PMM1 mode, VDD = 2.2V, TA = +25°C
0.19
Execution from RAM, 8MHz,
/8 mode, VDD = 2.2V, TA = +25°C
0.30
Execution from RAM, 1MHz,
/1 mode, VDD = 2.2V, TA = +25°C
0.14
-40°C < TA < +25°C
0.7
55
TA = +85°C
20
550
RTC enabled; HFIN ≥ 14MHz;
all I/O disconnected
1
50
µA
VDDIO
V
ISTOP(VDD)
Digital I/O Supply Current
IDDIO
Input High Voltage:
HFIN and 32KIN
VIH1
2
CONDITIONS
VDDIO
Active Current
Stop-Mode Current
MIN
32k x 16 flash
_____________________________________________________________________
0.75 x
VDDIO
mA
mA
µA
Low-Power LCD Microcontroller
(VDD = VDD(MIN) to VDD(MAX), VDDIO = 2.7V to 3.6V, TA = -40°C to +85°C.) (Note 1)
PARAMETER
SYMBOL
Input High Voltage:
P6.4–P6.5 and P7.0–P7.1
VIH2
Input High Voltage:
All Other Pins
CONDITIONS
MAX
UNITS
0.75 x
VDDIO
VLCD
V
VIH3
0.75 x
VDDIO
VDDIO
V
Input Low Voltage:
HFIN and 32KIN
VIL1
0
0.2 x
VDDIO
V
Input Low Voltage:
All Other Pins
VIL2
0
0.25 x
VDDIO
V
Output High Voltage:
P6.4–P6.5 and P7.0–P7.1
VOH1
SVS on; IOH(MAX) = 0.75mA; VLCD = 2.7V
VLCD 0.2
V
Output High Voltage:
All Other Pins
VOH2
IOH(MAX) = 0.75mA; VDDIO =1.8V
VDDIO 0.2
V
Output Low Voltage for
All Other Pins
VOL1
IOL = 1.0mA; VDDIO = 1.8V
GND
0.2
V
Output Low Voltage for
P6.4–P6.5 and P7.0–P7.1
VOL2
IOL = 1.4mA; VDDIO = 2.7V
GND
0.2
V
SVS on, VLCD = 3.3V
MIN
TYP
Input Leakage Current
IL
Internal pullup disabled
-100
+100
nA
Input Pullup Current
IIP
Internal pullup enabled
-20
-5
µA
3.6
V
LCD INTERFACE
LCD Reference Voltage
VLCD
LCD Bias Voltage 1
VLCD1
1/3 bias
VADJ + 2/3 (VLCD - VADJ)
V
LCD Bias Voltage 2
VLCD2
1/3 bias
V
LCD Adjustment Voltage
VADJ
Guaranteed by design
VADJ + 1/3 (VLCD - VADJ)
0.4 x
0
LCD Bias Resistor
RLCD
LCD Adjustment Resistor
RLADJ
LCD Segment Voltage
2.7
LRA4:LRA0 = 0
3.3
V
100
kΩ
200
kΩ
When segment is driven at VLCD level;
VLCD = 3V; ISEGxx = -3µA;
guaranteed by design
VLCD 0.02
VLCD
When segment is driven at VLCD1 level;
VLCD1 = 2V; ISEGxx = -3µA;
guaranteed by design
VLCD1 0.02
VLCD1
VSEGxx
V
When segment is driven at VLCD2 level;
VLCD2 = 1V; ISEGxx = -3µA;
guaranteed by design
VLCD2 0.02
VLCD2
When segment is driven at VADJ level;
VADJ = 0V; ISEGxx = -3µA;
guaranteed by design
-0.1
VADJ
_____________________________________________________________________
3
MAXQ2000
ELECTRICAL CHARACTERISTICS (continued)
MAXQ2000
Low-Power LCD Microcontroller
ELECTRICAL CHARACTERISTICS (continued)
(VDD = VDD(MIN) to VDD(MAX), VDDIO = 2.7V to 3.6V, TA = -40°C to +85°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
EXTERNAL CLOCK SOURCE
External oscillator, VDD ≥ 2.25V
External-Clock Frequency
fHFIN
External-Clock Period
tCLCL
System-Clock Frequency
fCK
System-Clock Period
tCK
0
20
External oscillator, VDD < 2.25V
0
14
External crystal, VDD ≥ 2.25V
3
20
External crystal, VDD < 2.25V
3
14
Flash programming, VDD ≥ 2.25V
2
20
Flash programming, VDD < 2.25V
2
14
48% minimum duty cycle
50
MHz
ns
2.25V ≤ VDD ≤ 2.75V
0
20
1.8V ≤ VDD ≤ 2.75V
0
14
50
MHz
ns
REAL-TIME CLOCK
RTC Input Frequency
f32KIN
32kHz watch crystal
32.768
kHz
JTAG/FLASH PROGRAMMING
Flash Erase Time
Mass erase
200
Page erase
20
Flash Programming Time
ms
2.5
Write/Erase Cycles
Data Retention
5.0
ms
10,000
cycles
100
years
SPI TIMING
SPI Master Operating
Frequency
1/tMCK
fCK / 2
MHz
SPI Slave Operating
Frequency
1/tSCK
fCK / 8
MHz
SCLK Output Pulse-Width
High/Low
tMCH, tMCL
SCLK Input Pulse-Width
High/Low
tSCH, tSCL
MOSI Output Hold Time
after SCLK Sample Edge
tMOH
MOSI Output Valid to
Sample Edge
tMCK / 2
- 25
ns
tSCK / 2
ns
tMCK / 2
- 25
ns
tMOV
tMCK / 2
- 25
ns
MISO Input Valid to SCLK
Sample Edge Rise/Fall
Setup
tMIS
30
ns
MISO Input to SCLK
Sample Edge Rise/Fall
Hold
tMIH
0
ns
4
CL = 50pF
_____________________________________________________________________
Low-Power LCD Microcontroller
(VDD = VDD(MIN) to VDD(MAX), VDDIO = 2.7V to 3.6V, TA = -40°C to +85°C.) (Note 1)
PARAMETER
SCLK Inactive to MOSI
Inactive
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
tMLH
tMCK / 2
- 25
ns
MOSI Input to SCLK
Sample Edge Rise/Fall
Setup
tSIS
30
ns
MOSI Input from SCLK
Sample Edge Transition
Hold
tSIH
tCK + 25
ns
MISO Output Valid after
SCLK Shift Edge
Transition
tSOV
SSEL Inactive
tSSH
tCK + 25
ns
SCLK Inactive to SSEL
Rising
tSD
tCK + 25
ns
MISO Output Disabled
after CS Edge Rise
tSLH
3tCK + 25
2tCK + 50
ns
ns
Note 1: Specifications to -40°C are guaranteed by design and not production tested.
Note 2: Measured on the VDD pin with VDD = 2.75V and not in reset.
_____________________________________________________________________
5
MAXQ2000
ELECTRICAL CHARACTERISTICS (continued)
Low-Power LCD Microcontroller
MAXQ2000
SPI Master Timing
SHIFT
SAMPLE
SHIFT
SAMPLE
SSEL
tMCK
SCLK
CKPOL/CKPHA
0/1 or 1/0
tMCH
SCLK
CKPOL/CKPHA
0/0 or 1/1
tMCL
tMOH
tMOV
MSB
MOSI
MSB-1
LSB
tMIH
tMIS
MSB
MISO
tMLH
MSB-1
LSB
SPI Slave Timing
SHIFT
SAMPLE
SHIFT
SAMPLE
tSSE
tSSH
SSEL
tSD
tSCK
SCLK
CKPOL/CKPHA
0/1 or 1/0
tSCH
SCLK
CKPOL/CKPHA
0/0 or 1/1
tSCL
tSIH
tSIS
MOSI
MSB
MSB-1
LSB
tSLH
tSOV
MISO
6
MSB
MSB-1
LSB
_____________________________________________________________________
Low-Power LCD Microcontroller
DIGITAL SUPPLY CURRENT
vs. CLOCK FREQUENCY
TA = 0°C
TA = -40°C
7
MAXQ2000 toc01
8
IDD1 (mA)
6
5
TA = +25°C
4
TA = +85°C
3
2
1
VDD = 2.75V
0
0
5
10
15
20
fHFIN (MHz)
Pin Description
PIN
NAME
FUNCTION
TQFN
QFN
40
49
VDD
22
27
VDDIO
I/O Supply Voltage
23, 35
28, 42
GND
Ground
45
54
VLCD
LCD Bias-Control Voltage. Highest LCD drive voltage used with static bias. Connected to an external
source.
46
55
VLCD1
LCD Bias, Voltage 1. LCD drive voltage used with 1/2 and 1/3 LCD bias. An internal resistordivider sets the voltage. External resistors and capacitors can be used to change the LCD voltage
or drive capability at this pin.
47
56
VLCD2
LCD Bias, Voltage 2. LCD drive voltage used with 1/3 LCD bias. An internal resistor-divider sets
the voltage. External resistors and capacitors can be used to change LCD voltage or drive
capability at this pin.
48
57
VADJ
LCD Adjustment Voltage. Connect to an external resistor to provide external control of the LCD
contrast. Leave disconnected for internal contrast adjustment.
Digital Supply Voltage
28
33
RESET
Digital, Active-Low, Reset Input/Output. The CPU is held in reset when this is low and begins
executing from the reset vector when released. The pin includes pullup current source and should
be driven by an open-drain, external source capable of sinking in excess of 2mA. This pin is
driven low as an output when an internal reset condition occurs.
42
51
HFXIN
High-Frequency Crystal Input. Connect an external crystal or resonator between HFXIN and
HFXOUT as the high-frequency system clock. Alternatively, HFXIN is the input for an external,
high-frequency clock source when HFXOUT is floating.
41
50
HFXOUT
High-Frequency Crystal Output/Input. Connect an external crystal or resonator between HFXIN
and HFXOUT as the high-frequency system clock. Alternatively, float HFXOUT when an external,
high-frequency clock source is connected to the HFXIN pin.
_____________________________________________________________________
7
MAXQ2000
Typical Operating Characteristics
MAXQ2000
Low-Power LCD Microcontroller
Pin Description (continued)
PIN
NAME
FUNCTION
TQFN
QFN
29
34
32KIN
32kHz Crystal Input. Connect an external, 32kHz watch crystal between 32KIN and 32KOUT as
the low-frequency system clock. Alternatively, 32KIN is the input for an external, 32kHz clock
source when 32KOUT is floating.
30
35
32KOUT
32kHz Crystal Output/Input. Connect an external, 32kHz watch crystal between 32KIN and
32KOUT as the low-frequency system clock. Alternatively, float 32KOUT when an external, 32kHz
clock source is connected to the 32KIN pin.
General-Purpose, 8-Bit, Digital, I/O, Type-C Port; LCD Segment-Driver Output. These port pins
function as both bidirectional I/O pins and LCD segment-drive outputs. All port pins are defaulted
as input with weak pullup after a reset. Enabling a pin’s LCD function disables the generalpurpose I/O on the pin. Setting the PCF1 bit enables the LCD for all pins on this port and disables
the general-purpose I/O function on all pins.
56-PIN
68-PIN
PORT
ALTERNATE FUNCTION
1–8
66, 67,
68; 1–5
P1.0–P1.7;
SEG8–
SEG15
1
66
P1.0
SEG8
2
67
P1.1
SEG9
3
68
P1.2
SEG10
4
1
P1.3
SEG11
5
2
P1.4
SEG12
6
3
P1.5
SEG13
7
4
P1.6
SEG14
8
5
P1.7
SEG15
General-Purpose, 8-Bit, Digital, I/O, Type-C Port; LCD Segment-Driver Output. These port pins
function as both bidirectional I/O pins and LCD segment-drive outputs. All port pins are defaulted
as input with weak pullup after a reset. Enabling a pin’s LCD function disables the generalpurpose I/O on the pin. Setting the PCF2 bit enables the LCD for all pins on this port and disables
the general-purpose I/O function on all pins.
ALTERNATE FUNCTIONS
56-PIN
68-PIN
PORT
56-PIN
68-PIN
9–12
8
6–13
P2.0–P2.7;
SEG16–
SEG23
—
6
P2.0
—
SEG16
—
7
P2.1
—
SEG17
—
8
P2.2
—
SEG18
—
9
P2.3
—
SEG19
9
10
P2.4
SEG16
SEG20
10
11
P2.5
SEG17
SEG21
11
12
P2.6
SEG18
SEG22
12
13
P2.7
SEG19
SEG23
_____________________________________________________________________
Low-Power LCD Microcontroller
PIN
TQFN
QFN
NAME
FUNCTION
General-Purpose, Digital, I/O, Type-D Port; LCD Segment-Driver Output; External EdgeSelectable Interrupt. This port functions as both bidirectional I/O pins and LCD segment-drive
outputs. All port pins are defaulted as inputs with weak pullups after a reset. The port pads can be
configured as an external interrupt for pins 7 to 4. If the external interrupt is enabled, the LCD function
on the associated pin is disabled. Setting the PCF3 bit enables the LCD for all pins on this port and
disables the general-purpose I/O function on all pins.
13–16
14–21
It is possible to mix the LCD and interrupt functions on the same port. To do this, the interrupt
enable must be established prior to setting the PCF0 bit. Care must be taken not to enable the
external interrupt while the LCD is in normal operational mode, as this could result in potentially
harmful contention between the LCD controller output and the external source connected to the
P3.0–P3.7; interrupt input.
SEGx;
ALTERNATE FUNCTIONS
INT4–INT7
56-PIN
68-PIN
PORT
56-PIN
68-PIN
—
14
P3.0
—
SEG24
—
15
P3.1
—
SEG25
—
16
P3.2
—
SEG26
—
17
P3.3
—
SEG27
13
18
P3.4
SEG20/INT4
SEG28/INT4
14
19
P3.5
SEG21/INT5
SEG29/INT5
15
20
P3.6
SEG22/INT6
SEG30/INT6
16
21
P3.7
SEG23/INT7
SEG31/INT7
LCD Segment-Driver Output; LCD Common-Drive Output. The selection of a pin function as either
segment or its alternative common-mode signal is controlled by the choice of duty cycle (DUTY1:0).
17–21
22–26
SEGx;
COM3–
COM0
56-PIN
68-PIN
17
18
FUNCTION
ALTERNATE FUNCTIONS
56-PIN
68-PIN
22
SEG24
SEG32
—
23
SEG25
SEG33
COM3
19
24
SEG26
SEG34
COM2
20
25
SEG27
SEG35
COM1
21
26
—
COM0
—
General-Purpose, Digital, I/O, Type-D Port; Debug Port Signal; External Edge-Selectable
Interrupt. Pins default to JTAG on POR; other functions must be enabled from software.
24–27
29–32
P4.0–P4.3;
TCK/TDI/
TMS/TDO;
INT8, INT9
56-PIN
68-PIN
PORT
ALTERNATE FUNCTIONS
24
29
P4.0
TCK
INT8
25
30
P4.1
TDI
INT9
26
31
P4.2
TMS
—
27
32
P4.3
TDO
—
_____________________________________________________________________
9
MAXQ2000
Pin Description (continued)
MAXQ2000
Low-Power LCD Microcontroller
Pin Description (continued)
PIN
NAME
FUNCTION
TQFN
QFN
—
36
P5.2/RX1/
INT10
General-Purpose, Digital, I/O, Type-D Port; Serial Port 1 Receive; External Edge-Selectable
Interrupt 10
—
37
P5.3/TX1/
INT11
General-Purpose, Digital, I/O, Type-D Port; Serial Port 1 Transmit; External Edge-Selectable
Interrupt 11
31
38
P5.4/SS
General-Purpose, Digital, I/O, Type-C Port; Active-Low, SPI, Slave-Select Input. Becomes the
slave-select input in SPI mode.
32
39
P5.5;
MOSI
General-Purpose, Digital, I/O, Type-C Port; SPI, Master-Out Slave-In Output. Data is clocked
out of the microcontroller on SCLK’s falling edge and into the slave device on SCLK’s rising edge.
Becomes MISO input in SPI mode.
33
40
P5.6;
SCLK
General-Purpose, Digital, I/O, Type-C Port; SPI, Clock Output. Becomes SCLK input in SPI
mode but limited to SYSCLK / 8.
34
41
General-Purpose, Digital, I/O, Type-C Port; SPI, Master-In Slave-Out Input. Data is clocked out
P5.7/MISO of the slave on SCLK’s falling edge and into the microcontroller on SCLK’s rising edge. Becomes
MOSI output in slave mode.
36
43
P6.0/T1B/
INT12
37
44
P6.1/T1/
INT13
General-Purpose, Digital, I/O Type-D Port; Timer 1 Output (PWM); External Edge-Selectable
Interrupt 13
—
45
P6.2/T2B/
OW_OUT
General-Purpose, Digital, I/O, Type-D Port; Timer 2 Alternative Output (PWM); 1-Wire Data
Output
—
46
P6.3/T2/
OW_IN
38
47
P6.4/T0B/
WKOUT0
39
48
P6.5/T0/
WKOUT1
General-Purpose, Digital, I/O, Type-C Port; Timer 0 Output (PWM); Wakeup Output 1
43
52
P7.0/TX0/
INT14
General-Purpose, Digital, I/O, Type-D Port; Serial Port 0 Transmit; External, Edge-Selectable
Interrupt 14
44
53
P7.1/RX0/
INT15
General-Purpose, Digital, I/O, Type-D Port; Serial Port 0 Receive; External Edge-Selectable
Interrupt 15
10
General-Purpose, Digital, I/O, Type-D Port; Timer 1 Alternative Output (PWM); External EdgeSelectable Interrupt 12
General-Purpose, Digital, I/O, Type-D Port; Timer 2 Output (PWM); 1-Wire Data Input
General-Purpose, Digital, I/O, Type-C Port; Timer 0 Alternative Output (PWM); Wakeup
Output 0
____________________________________________________________________
Low-Power LCD Microcontroller
PIN
TQFN
QFN
NAME
FUNCTION
General-Purpose, Digital, I/O, Type-D Port; LCD Segment-Driver Output; External EdgeSelectable Interrupt. This port functions as both bidirectional I/O pins and LCD segment-drive
outputs. All port pins are defaulted as input with weak pullup after a reset. The port pads can be
configured as an external interrupt for pins 7 to 4. If the external interrupt is enabled, the LCD function
on the associated pin is disabled. Setting the PCF0 bit enables the LCD for all pins on this port and
disables the general-purpose I/O function on all pins.
49–56
—
58–65
—
It is possible to mix the LCD and interrupt functions on the same port. To do this, the interrupt
enable must be established prior to setting the PCF0 bit. Care must be taken not to enable the
external interrupt while the LCD is in normal operational mode, as this could result in potentially
P0.0–P0.7;
harmful contention between the LCD controller output and the external source connected to the
SEG0–
interrupt input.
SEG7;
56-PIN
68-PIN
PORT
ALTERNATE FUNCTIONS
INT0–INT3
49
58
P0.0
SEG0
—
EP
50
59
P0.1
SEG1
—
51
60
P0.2
SEG2
—
52
61
P0.3
SEG3
—
53
62
P0.4
SEG4
INT0
54
63
P0.5
SEG5
INT1
55
64
P0.6
SEG6
INT2
56
65
P0.7
SEG7
INT3
Exposed Paddle. Exposed paddle is on the under side of the package. It should be left unconnected.
____________________________________________________________________
11
MAXQ2000
Pin Description (continued)
Low-Power LCD Microcontroller
MAXQ2000
Block Diagram
VDDIO
VLCD
SS
SCLK
3WINT
3/4-WIRE (SPI)
INTERFACE
WKUP
P5.6/SCLK
P5.7/MISO
WK_OUT
WKOUT_EN
1WINT
1-WIRE
INTERFACE
INTERRUPT
CONTROLLER
T0INT
WDINT
WATCHDOG
TIMER
SYS_AL
DAY_AL
T0CLK
T1INT
TIMER0
T1CLK
T2INT
TIMER1
T2CLK
TIMER2
OWOUT
OWIN
P6.4/T0/WKOUT
T0
T0B
T1
T1B
T2
T2B
P6.5/T0B/WKOUT
P6.1/T1/INT13
P6.0/T1B/INT12
P6.3/T2/OWIN
P6.2/T2B/OWOUT
PAD DRIVERS
MAXQ2000
WDCLK
P5.4/SS
P5.5/MOSI
MOSI
MISO
IOINT
TXD0
U1INT
U2INT
P7.0/TX0/INT14
SERIAL
UART1
RXD0
P7.1/RX0/INT15
TXD1
P5.3/TX1/INT11
SERIAL
UART2
RXD1
P5.2/RX1/INT10
SEG[28:31]/P3[4:7]/INT[4:7]
REGISTER
FILE
DPTR0
DPTR1
DPTR2
VDD
SEG[0]:SEG32
SEG[24:27]/P3[0:3]
SEG[16:23]/P2[0:7]
SEG[8:15]/P1[0:7]
SEG[0:3]/P0[0:3]
P4.0/TCK/INT8
P4.1/TDI/INT9
P4.2/TMS
P4.3/TDO
32k x 16
(64kByte)
FLASH ROM
OR
MASK ROM
16-BIT
RISC CPU
EMULATION/
DOWNLOAD
RESET
HF OSC HFCLK
HFXOUT
32KIN
32KOUT
VDDIO
32k
OSC
SCLKDIV
2:1
MUX
32KCLK
3
2:1
MUXES
VLCD
16 x 16
HW
MULTIPLY
SYSCLK
WDDIV
TCLKDIV
GND
LCD BIAS
CONTROL
2k x 8
RAM
GND
HFXIN
SEG[4:7]/P0[4:7]/INT[0:3]
17
x 8 LCD
DISPLAY
RAM
WDCLK
T0CLK
VLCD1
T1CLK
T2CLK
RTC AND
ALARMS
32KHz
HF OSC / 128
SYS_AL
DAY_AL
LCD
CONTROLLER/
DRIVER
VLCD2
LCD
CLK
SELECT
VADJ
GNDIO
SEG[32]/INT16
COM[0]
COM[3:1]/SEG[33:35]
12
____________________________________________________________________
Low-Power LCD Microcontroller
The following is an introduction to the primary features
of the microcontroller. More detailed descriptions of the
device features can be found in the data sheets, errata
sheets, and user’s guides described later in the
Additional Documentation section.
MAXQ Core Architecture
The MAXQ2000 is a low-cost, high-performance,
CMOS, fully static, 16-bit RISC microcontroller with flash
memory and an integrated 100- or 132-segment LCD
controller. It is structured on a highly advanced, accumulator-based, 16-bit RISC architecture. Fetch and execution operations are completed in one cycle without
pipelining, because the instruction contains both the op
code and data. The result is a streamlined 20 million
instructions-per-second (MIPS) microcontroller.
The highly efficient core is supported by a 16-level
hardware stack, enabling fast subroutine calling and
task switching. Data can be quickly and efficiently
manipulated with three internal data pointers. Multiple
data pointers allow more than one function to access
data memory without having to save and restore data
pointers each time. The data pointers can automatically
increment or decrement following an operation, eliminating the need for software intervention. As a result,
application speed is greatly increased.
Instruction Set
The instruction set is composed of fixed-length, 16-bit
instructions that operate on registers and memory locations. The instruction set is highly orthogonal, allowing
arithmetic and logical operations to use any register
along with the accumulator. Special-function registers
control the peripherals and are subdivided into register
modules. The family architecture is modular, so that
new devices and modules can reuse code developed
for existing products.
The architecture is transport-triggered. This means that
writes or reads from certain register locations can also
cause side effects to occur. These side effects form the
basis for the higher-level op codes defined by the
assembler, such as ADDC, OR, JUMP, etc. The op
codes are actually implemented as MOVE instructions
between certain register locations, while the assembler
handles the encoding, which need not be a concern to
the programmer.
The 16-bit instruction word is designed for efficient execution. Bit 15 indicates the format for the source field of
the instruction. Bits 0 to 7 of the instruction represent the
source for the transfer. Depending on the value of the
format field, this can either be an immediate value or a
source register. If this field represents a register, the
lower four bits contain the module specifier and the
upper four bits contain the register index in that module.
Bits 8 to 14 represent the destination for the transfer.
This value always represents a destination register, with
the lower four bits containing the module specifier and
the upper three bits containing the register subindex
within that module. Any time that it is necessary to
directly select one of the upper 24 registers as a destination, the prefix register, PFX, is needed to supply the
extra destination bits. This prefix register write is inserted automatically by the assembler and requires only
one additional execution cycle.
Memory Organization
The device incorporates several memory areas:
• 4kWords utility ROM,
• 32kWords of flash memory for program storage,
• 1kWord of SRAM for storage of temporary variables, and
• 16-level stack memory for storage of program return
addresses and general-purpose use.
The memory is arranged by default in a Harvard architecture, with separate address spaces for program and
data memory. A special mode allows data memory to be
mapped into program space, permitting code execution
from data memory. In addition, another mode allows program memory to be mapped into data space, permitting
code constants to be accessed as data memory.
The incorporation of flash memory allows the devices to
be reprogrammed, eliminating the expense of throwing
away one-time programmable devices during development and field upgrades. Flash memory can be password protected with a 16-word key, denying access to
program memory by unauthorized individuals.
A pseudo-Von Neumann memory map can also be
enabled. This places the utility ROM, code, and data
memory into a single contiguous memory map. This is
useful for applications that require dynamic program
modification or unique memory configurations.
Stack Memory
A 16-bit-wide internal stack provides storage for program return addresses and general-purpose use. The
stack is used automatically by the processor when the
CALL, RET, and RETI instructions are executed and
interrupts serviced. The stack can also be used explicitly to store and retrieve data by using the PUSH, POP,
and POPI instructions.
____________________________________________________________________
13
MAXQ2000
Detailed Description
MAXQ2000
Low-Power LCD Microcontroller
PROGRAM MEMORY
DATA MEMORY
FFFFh
FFFFh
0Fh
16 x 16
STACK
00h
8FFFh
4k x 16
UTILITY
ROM
REGISTERS
FFh
7FFFh
1Fh
0Fh
SPRs
32k x 16
FLASH
MEMORY
07h
06h
03FFh
SFRs
1k x 16 SRAM
00h
0000h
Figure 1. Memory Map
14
____________________________________________________________________
0000h
Low-Power LCD Microcontroller
Utility ROM
The utility ROM is a 4kWord block of internal ROM
memory that defaults to a starting address of 8000h.
The utility ROM consists of subroutines that can be
called from application software. These include:
• In-system programming (bootstrap loader) over JTAG
or UART interfaces
• In-circuit debug routines
• Test routines (internal memory tests, memory
loader, etc.)
• User-callable routines for in-application flash programming and fast table lookup
Following any reset, execution begins in the utility
ROM. The ROM software determines whether the program execution should immediately jump to location
0000h, the start of user-application code, or to one of
the special routines mentioned. Routines within the utility ROM are user-accessible and can be called as subroutines by the application software. More information
on the utility ROM contents is contained in the MAXQ
Family User’s Guide: MAXQ2000 Supplement.
Some applications require protection against unauthorized viewing of program code memory. For these
applications, access to in-system programming, inapplication programming, or in-circuit debugging functions is prohibited until a password has been supplied.
The password is defined as the 16 words of physical
program memory at addresses x0010h to x001Fh.
A single password lock (PWL) bit is implemented in the
SC register. When the PWL is set to one (power-on
reset default), the password is required to access the
utility ROM, including in-circuit debug and in-system
programming routines that allow reading or writing of
internal memory. When PWL is cleared to zero, these
utilities are fully accessible without password. The
password is automatically set to all ones following a
mass erase.
Programming
The flash memory of the microcontroller can be programmed by two different methods: in-system programming and in-application programming. Both
methods afford great flexibility in system design as well
as reduce the life-cycle cost of the embedded system.
These features can be password protected to prevent
unauthorized access to code memory.
In-System Programming
An internal bootstrap loader allows the device to be
reloaded over a simple JTAG interface. As a result,
software can be upgraded in-system, eliminating the
need for a costly hardware retrofit when updates are
required. Remote software uploads are possible that
enable physically inaccessible applications to be frequently updated. The interface hardware can be a
JTAG connection to another microcontroller, or a connection to a PC serial port using a serial-to-JTAG converter such as the MAXQJTAG-001, available from
Maxim Integrated Products. If in-system programmability is not required, a commercial gang programmer can
be used for mass programming.
Activating the JTAG interface and loading the test
access port (TAP) with the system programming instruction invokes the bootstrap loader. Setting the SPE bit to
1 during reset through the JTAG interface executes the
bootstrap-loader-mode program that resides in the utility
ROM. When programming is complete, the bootstrap
loader can clear the SPE bit and reset the device, allowing the device to bypass the utility ROM and begin execution of the application software.
The following bootstrap loader functions are supported:
• Load
• Dump
• CRC
• Verify
• Erase
Optionally, the bootstrap loader can be invoked by the
application code. In this mode, the application software
would configure the SPE and PSS bits for UART communication, then jump to the start of the utility ROM. In
this way, the bootstrap loader can be accessed through
another UART-enabled peripheral, or a PC serial port
through an RS-232 transceiver such as the MAX232.
Because the bootstrap loader defaults to the JTAG configuration on reset, the UART versus JTAG selection
must be made from the application code. As a result,
bootstrap loader access through the UART is not possible in an unprogrammed device.
____________________________________________________________________
15
MAXQ2000
On reset, the stack pointer, SP, initializes to the top of
the stack (0Fh). The CALL, PUSH, and interrupt-vectoring operations increment SP, then store a value at the
location pointed to by SP. The RET, RETI, POP, and
POPI operations retrieve the value @SP and then
decrement SP.
MAXQ2000
Low-Power LCD Microcontroller
In-Application Programming
The in-application programming feature allows the
microcontroller to modify its own flash program memory
while simultaneously executing its application software.
This allows on-the-fly software updates in missioncritical applications that cannot afford downtime.
Alternatively, it allows the application to develop custom loader software that can operate under the control
of the application software. The utility ROM contains
user-accessible flash programming functions that erase
and program flash memory. These functions are
described in detail in the user’s guide supplement for
this device.
Register Set
Most functions of the device are controlled by sets of registers. These registers provide a working space for memory operations as well as configuring and addressing
peripheral registers on the device. Registers are divided
into two major types: system registers and peripheral registers. The common register set, also known as the system registers, includes the ALU, accumulator registers,
data pointers, interrupt vectors and control, and stack
pointer. The peripheral registers define additional functionality that may be included by different products based
on the MAXQ architecture. This functionality is broken up
into discrete modules so that only the features required
for a given product need to be included. Tables 1 and 4
show the MAXQ2000 register set.
Table 1. System Register Map
REGISTER
INDEX
MODULE NAME (BASE SPECIFIER)
AP (8h)
A (9h)
PFX (Bh)
IP (Ch)
SP (Dh)
DPC (Eh)
DP (Fh)
0xh
AP
A[0]
PFX
1xh
APC
A[1]
—
IP
—
—
—
—
SP
—
—
2xh
—
A[2]
—
—
IV
—
—
3xh
—
A[3]
—
—
—
Offs
DP0
4xh
PSF
A[4]
—
—
—
DPC
—
5xh
IC
A[5]
—
—
—
GR
—
6xh
IMR
A[6]
—
—
LC0
GRL
—
7xh
—
A[7]
—
—
LC1
BP
DP1
8xh
SC
A[8]
—
—
—
GRS
—
9xh
—
A[9]
—
—
—
GRH
—
Axh
—
A[10]
—
—
—
GRXL
—
Bxh
IIR
A[11]
—
—
—
FP
—
Cxh
—
A[12]
—
—
—
—
—
Dxh
—
A[13]
—
—
—
—
—
Exh
CKCN
A[14]
—
—
—
—
—
Fxh
WDCN
A[15]
—
—
—
—
—
Note: Names that appear in italics indicate that all bits of a register are read-only. Names that appear in bold indicate that a register
is 16 bits wide. Registers in module AP are bit addressable.
16
____________________________________________________________________
—
—
—
—
GR.7
DP[1] (16 bits)
GR.7
DP[0] (16 bits)
GR.7
GR.15
DP[1]
GR.7
GR.0
DP[0]
GR.7
GR.1
FP (16 bits)
GR.7
GR.2
GR.7
FP
GR.7
GR.3
GR.8
GR.7
GR.7
GR.4
GR.9
GRXL
GR.5
GR.10
—
GR.15
GRS
GR.6
GR.11
—
GRH
GR.7
GR.12
—
BP (16 bits)
GR.13
—
BP
GR.14
—
GR.7
GR.15
GR
—
GRL
—
DPC
—
LC[1] (16 bits)
LC[1]
—
LC[0] (16 bits)
LC[0]
Offs
IV (16 bits)
IV
—
IP (16 bits)
IP
—
PFX (16 bits)
PFX
SP
A[n] (16 bits)
A[n]
(0..15)
RGSL
—
POR
CKCN
WDCN
—
IIS
IIR
—
GR.6
GR.14
GR.14
GR.6
GR.6
—
—
EWDI
—
IMS
—
S
IDS
TAP
—
6
—
SC
—
7
IMR
—
8
REGISTER BIT
—
9
IC
10
Z
11
CLR
12
PSF
13
APC
14
—
15
AP
REGISTER
5
GR.5
GR.13
GR.13
GR.5
GR.5
—
—
WD1
RGMD
—
—
—
CGDS
—
—
—
4
WDIF
SWB
II3
—
IM3
—
GPF0
—
3
GR.4
GR.12
GR.12
GR.4
GR.4
WBS2
GR.3
GR.11
GR.11
GR.3
GR.3
WBS1
Offs (8 bits)
—
WD0
STOP
II4
CDA0
IM4
—
GPF1
—
—
1
EWT
CD1
II1
PWL
IM1
INS
C
MOD1
GR.2
GR.10
GR.10
GR.2
GR.2
WBS0
GR.1
GR.9
GR.9
GR.1
GR.1
SDPS1
SP (4 bits)
WTRF
PMME
II2
ROD
IM2
—
OV
MOD2
AP (4 bits)
2
GR.0
GR.8
GR.8
GR.0
GR.0
SDPS0
RWT
CD0
II0
—
IM0
IGE
E
MOD0
0
MAXQ2000
Table 2. System Register Bit Functions
Low-Power LCD Microcontroller
____________________________________________________________________
17
MAXQ2000
Low-Power LCD Microcontroller
Table 3. System Register Bit Reset Values
REGISTER
REGISTER BIT
7
6
5
4
3
2
1
0
AP
0
0
0
0
0
0
0
0
APC
0
0
0
0
0
0
0
0
PSF
1
0
0
0
0
0
0
0
IC
0
0
0
0
0
0
0
0
IMR
0
0
0
0
0
0
0
0
SC
0
0
0
0
0
0
s
0
IIR
0
0
0
0
0
0
0
0
CKCN
0
s
s
0
0
0
0
0
WDCN
s
s
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A[n]
(0..15)
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
PFX
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IP
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SP
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
IV
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LC[0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LC[1]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DPC
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
GR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BP
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GRS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Offs
GRL
GRH
GRXL
18
0
0
0
0
0
0
0
0
FP
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DP0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DP1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
____________________________________________________________________
Low-Power LCD Microcontroller
MAXQ2000
Table 4. Peripheral Register Map
MODULE NAME (BASE SPECIFIER)
REGISTER
INDEX
M0 (x0h)
M1 (x1h)
M2 (x2h)
M3 (x3h)
M4 (x4h)
M5 (x5h)
0xh
PO0
PO4
MCNT
T2CNA0
T2CNA1
—
1xh
PO1
PO5
MA
T2H0
T2H1
—
2xh
PO2
PO6
MB
T2RH0
T2RH1
—
3xh
PO3
PO7
MC2
T2CH0
T2CH1
—
4xh
—
—
MC1
—
T2CNA2
—
5xh
—
—
MC0
SPIB
T2H2
—
6xh
EIF0
EIF1
SCON0
SCON1
T2RH2
—
7xh
EIE0
EIE1
SBUF0
SBUF1
T2CH2
—
8xh
PI0
PI4
SMD0
SMD1
T2CNB1
—
9xh
PI1
PI5
PR0
PR1
T2V1
—
Axh
PI2
PI6
—
—
T2R1
—
Bxh
PI3
PI7
MC1R
—
T2C1
—
Cxh
EIES0
EIES1
MC0R
T2CNB0
T2CNB2
—
Dxh
—
—
LCRA
T2V0
T2V2
—
Exh
—
—
LCFG
T2R0
T2R2
—
Fxh
—
—
LCD16
T2C0
T2C2
—
10xh
PD0
PD4
LCD0
T2CFG0
T2CFG1
—
11xh
PD1
PD5
LCD1
—
T2CFG2
—
12xh
PD2
PD6
LCD2
—
—
—
13xh
PD3
PD7
LCD3
OWA
—
—
14xh
—
—
LCD4
OWD
—
—
15xh
—
—
LCD5
SPICN
—
—
16xh
—
—
LCD6
SPICF
—
—
17xh
—
—
LCD7
SPICK
—
—
18xh
—
—
LCD8
ICDT0
—
—
19xh
RCNT
—
LCD9
ICDT1
—
—
1Axh
RTSS
—
LCD10
ICDC
—
—
1Bxh
RTSH
—
LCD11
ICDF
—
—
1Cxh
RTSL
—
LCD12
ICDB
—
—
1Dxh
RSSA
—
LCD13
ICDA
—
—
1Exh
RASH
SVS
LCD14
ICDD
—
—
1Fxh
RASL
WKO
LCD15
TM
—
—
Note: Names that appear in italics indicate that all bits of a register are read-only. Names that appear in bold indicate that a register
is 16 bits wide.
____________________________________________________________________
19
20
ACS
—
—
—
—
—
4
3
—
—
____________________________________________________________________
—
PI4
PD5 (8 bits)
PD6 (8 bits)
PD6
—
PD5
—
IT11
—
—
IT12
PD4
IT13
IT15
EIES1
IT14
PI6 (8 bits)
—
—
PI7
—
EX11
PI6
—
EX12
PI5 (8 bits)
—
EX13
PI5
—
EX14
IE11
—
EX15
IE12
EIE1
IE13
IE15
EIF1
IE14
PO6 (8 bits)
—
—
PO7
—
—
PO6
PO5 (8 bits)
—
RASL (16 bits)
PO5
PO4
RASL
RSSA (8 bits)
RASH (8 bits)
RASH
RTSL (16 bits)
RTSL
BUSY
RTSS (8 bits)
RDY
RSSA
RTSH (16 bits)
RTSH
RTSS
RDYE
PD3 (8 bits)
ALDF
PD3
ALSF
PD2 (8 bits)
PD2
RCNT
PD1 (8 bits)
PD1
IT3
PD0 (8 bits)
PD0
IT4
PI3 (8 bits)
IT5
PI2 (8 bits)
PI3
EIES0
PI1 (8 bits)
IT6
IE3
EX3
PI2
IT7
IE4
EX4
PI0 (8 bits)
EX5
IE5
5
PI1
EX6
IE6
6
PI0
IE7
EX7
EIF0
X32D
7
EIE0
WE
8
REGISTER BIT
PO3 (8 bits)
9
PO2 (8 bits)
10
PO3
11
PO1 (8 bits)
12
PO2
13
PO1
14
PO0 (8 bits)
15
PO0
REGISTER
Table 5. Peripheral Register Bit Functions
PD4 (5 bits)
IT10
—
PI4 (5 bits)
EX10
IE10
—
PO4 (5 bits)
ASE
IT2
EX2
IE2
2
RTCE
IT0
EX0
IE0
0
IE8
EX8
IT9
IT8
PI7 (2 bits)
EX9
IE9
PO7 (2 bits)
ADE
IT1
EX1
IE1
1
MAXQ2000
Low-Power LCD Microcontroller
DUTY1
DUTY0
FRM3
FRM2
MC0 (16 bits)
MC0
—
MC1 (16 bits)
MC1
—
MC2 (16 bits)
MC2
6
LRIG
TB8
OPCS
—
LRA3
—
CPRL2
—
LRA2
ESI0
RB8
MSUB
____________________________________________________________________
SPICN
STBY
—
OWA
OWD
T2CI
T2CFG0
T2C0.7
T2R0.7
T2C0.15 T2C0.14 T2C0.13 T2C0.12 T2C0.11 T2C0.10 T2C0.9 T2C0.8
T2C0
T2R0.8
T2R0.15 T2R0.14 T2R0.13 T2R0.12 T2R0.11 T2R0.10
T2R0
T2R0.9
ET2L
T2V0.7
T2V0.8
T2V0.15 T2V0.14 T2V0.13 T2V0.12 T2V0.11 T2V0.10 T2V0.9
T2V0
PR1 (16 bits)
—
SM0/FE
T2CNB0
PR1
SMD1
SBUF1
SCON1
SPIB (16 bits)
SPIC
—
DIV2
T2C0.6
T2R0.6
T2V0.6
T2OE1
—
SM1
ROVR
—
DIV1
T2C0.5
T2R0.5
T2V0.5
T2POL1
—
SM2
REN
TB8
—
T2MD
T2C0.3
T2R0.3
T2V0.3
TF2
—
WCOL
MODF
OWD (8 bits)
—
DIV0
T2C0.4
T2R0.4
T2V0.4
TR2L
—
SBUF1 (8 bits)
MODFE
A2
CCF1
T2C0.2
T2R0.2
T2V0.2
TF2L
ESI1
RB8
1
0
MSTM
A1
CCF0
T2C0.1
T2R0.1
T2V0.1
TCC2
SMOD1
TI
T2C0.9
T2R0.9
T2V0.9
SS2
OPM
LRA1
SMOD0
TI
MMAC
WKE1
SV71
SPIEN
A0
C/T2
T2C0.0
T2R0.0
T2V0.0
TC2L
FEDE1
RI
T2C0.8
T2R0.8
T2V0.8
G2EN
DPE
LRA0
FEDE0
RI
SUS
WKE0
SV70
PD7 (2 bits)
MAXQ2000
SPIB
T2C0.15 T2C0.14 T2C0.13 T2C0.12 T2C0.11 T2C0.10
TR2
—
WKL
T2CH0
TR2L
LCD[0..15] (8 bits)
PCF0
LRA4
—
2
—
T2V0.15 T2V0.14 T2V0.13 T2V0.12 T2V0.11 T2V0.10
T2POL0
PCF1
—
—
SBUF0 (8 bits)
REN
SQU
—
SV64
3
—
T2R0.15 T2R0.14 T2R0.13 T2R0.12 T2R0.11 T2R0.10
T2OE0
PCF2
LCCS
—
SM2
CLD
—
SV65
4
—
T2H0
ET2
PCF3
—
SM1
MCW
—
5
—
T2RH0
T2CNA0
LCD[0..15]
LCFG
FRM0
MC0R (16 bits)
FRM1
MC0R
LCRA
MC1R (16 bits)
MC1R
—
PR0 (16 bits)
PR0
SMD0
SBUF0
SM0/FE
MB (16 bits)
MB
SCON0
MA (16 bits)
MA
—
7
OF
8
REGISTER BIT
MCNT
9
SV66
10
—
11
SV67
12
SVS
13
WKO
14
—
15
—
PD7
REGISTER
Table 5. Peripheral Register Bit Functions (continued)
Low-Power LCD Microcontroller
21
22
—
—
T2V1.8
SS2
SS2
T2C1.15 T2C1.14 T2C1.13 T2C1.12 T2C1.11 T2C1.10 T2C1.9 T2C1.8
T2C1
T2CI
T2CI
T2CFG1
T2CFG2
T2C2.7
T2R2.7
T2C2.15 T2C2.14 T2C2.13 T2C2.12 T2C2.11 T2C2.10 T2C2.9 T2C2.8
T2C2
T2R2.8
T2R2.15 T2R2.14 T2R2.13 T2R2.12 T2R2.11 T2R2.10
T2R2
T2R2.9
T2V2.7
T2V2.15 T2V2.14 T2V2.13 T2V2.12 T2V2.11 T2V2.10 T2V2.9
T2V2
T2V2.8
ET2L
T2CNB2
T2C1.7
T2R1.7
T2R1.15 T2R1.14 T2R1.13 T2R1.12 T2R1.11 T2R1.10
T2R1
T2R1.8
T2V1.7
T2V1.15 T2V1.14 T2V1.13 T2V1.12 T2V1.11 T2V1.10 T2V1.9
T2V1
T2R1.9
ET2L
T2CNB1
____________________________________________________________________
DIV2
DIV2
T2C2.6
T2R2.6
T2V2.6
T2OE1
T2C1.6
T2R1.6
T2V1.6
T2OE1
DIV1
DIV1
T2C2.5
T2R2.5
T2V2.5
T2POL1
T2C1.5
T2R1.5
T2V1.5
T2POL1
DIV0
DIV0
T2C2.4
T2R2.4
T2V2.4
TR2L
T2C1.4
T2R1.4
T2V1.4
TR2L
T2MD
T2MD
T2C2.3
T2R2.3
T2V2.3
TF2
T2C1.3
T2R1.3
T2V1.3
TF2
CCF1
CCF1
T2C2.2
T2R2.2
T2V2.2
TF2L
T2C1.2
T2R1.2
T2V1.2
TF2L
CCF0
CCF0
T2C2.1
T2R2.1
T2V2.1
TCC2
T2C1.1
T2R1.1
T2V1.1
TCC2
T2C2.9
T2R2.9
CPRL2
T2C2.15 T2C2.14 T2C2.13 T2C2.12 T2C2.11 T2C2.10
TR2
T2R2.15 T2R2.14 T2R2.13 T2R2.12 T2R2.11 T2R2.10
TR2L
T2RH2
T2POL0
T2CH2
T2OE0
T2V2.9
ET2
T2V2.15 T2V2.14 T2V2.13 T2V2.12 T2V2.11 T2V2.10
T2H2
T2CNA2
T2C1.9
T2R1.9
CPRL2
T2C1.15 T2C1.14 T2C1.13 T2C1.12 T2C1.11 T2C1.10
TR2
T2R1.15 T2R1.14 T2R1.13 T2R1.12 T2R1.11 T2R1.10
TR2L
SPE
CMD1
CKR1
CKPHA
1
T2RH1
T2POL0
PSS0
CMD2
CKR2
CHR
2
T2CH1
T2OE0
PSS1
CMD3
CKR3
—
3
ICDB (8 bits)
—
—
CKR4
—
4
T2V1.9
ET2
—
REGE
CKR5
—
5
T2V1.15 T2V1.14 T2V1.13 T2V1.12 T2V1.11 T2V1.10
T2H1
T2CNA1
ICDA (16 bits)
ICDD (16 bits)
ICDA
ICDD
ICDB
ICDF
—
CKR6
DME
8
REGISTER BIT
ICDC
9
—
10
CKR7
11
ESPI1
12
SPICF
13
SPICK
14
6
15
7
REGISTER
Table 5. Peripheral Register Bit Functions (continued)
C/T2
C/T2
T2C2.0
T2R2.0
T2V2.0
TC2L
T2C1.0
T2R1.0
T2V1.0
TC2L
T2C2.8
T2R2.8
T2V2.8
G2EN
T2C1.8
T2R1.8
T2V1.8
G2EN
TXC
CMD0
CKR0
CKPOL
0
MAXQ2000
Low-Power LCD Microcontroller
Low-Power LCD Microcontroller
REGISTER
REGISTER BIT
7
6
5
4
3
2
1
0
PO0
1
1
1
1
1
1
1
1
PO1
1
1
1
1
1
1
1
1
PO2
1
1
1
1
1
1
1
1
PO3
1
1
1
1
1
1
1
1
EIF0
0
0
0
0
0
0
0
0
EIE0
0
0
0
0
0
0
0
0
PI0
s
s
s
s
s
s
s
s
PI1
s
s
s
s
s
s
s
s
PI2
s
s
s
s
s
s
s
s
PI3
s
s
s
s
s
s
s
s
EIES0
0
0
0
0
0
0
0
0
PD0
0
0
0
0
0
0
0
0
PD1
0
0
0
0
0
0
0
0
PD2
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
PD3
0
0
0
0
0
0
0
0
0
s
s
0
0
0
0
0
s
s
0
0
1
s
s
s
s
s
s
s
s
s
s
s
RTSH
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
RTSL
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
RSSA
0
0
0
0
0
0
0
0
RASH
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PO4
0
0
0
1
1
1
1
1
PO5
1
1
1
1
1
1
1
1
PO6
1
1
1
1
1
1
1
1
RCNT
RTSS
RASL
MAXQ2000
Table 6. Peripheral Register Reset Values
0
0
0
0
0
0
0
0
PO7
0
0
0
0
0
0
1
1
EIF1
0
0
0
0
0
0
0
0
EIE1
0
0
0
0
0
0
0
0
PI4
0
0
0
s
s
s
s
s
PI5
s
s
s
s
s
s
s
s
PI6
s
s
s
s
s
s
s
s
PI7
0
0
0
0
0
0
s
s
EIES1
0
0
0
0
0
0
0
0
PD4
0
0
0
0
0
0
0
0
PD5
0
0
0
0
0
0
0
0
PD6
0
0
0
0
0
0
0
0
PD7
0
0
0
0
0
0
0
0
SVS
0
0
0
0
0
0
0
0
WKO
0
0
0
0
0
0
0
0
____________________________________________________________________
23
MAXQ2000
Low-Power LCD Microcontroller
Table 6. Peripheral Register Reset Values (continued)
REGISTER
REGISTER BIT
15
14
13
12
11
10
9
8
MCNT
MA
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MC2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MC1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MC0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SCON0
0
0
0
0
0
0
0
0
SBUF0
0
0
0
0
0
0
0
0
SMD0
0
0
0
0
0
0
0
0
PR0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MC1R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MC0R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LCRA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LCFG
0
0
0
0
0
0
0
0
LCD[0..15]
0
0
0
0
0
0
0
0
T2CNA0
0
0
0
0
0
0
0
0
T2H0
0
0
0
0
0
0
0
0
T2RH0
0
0
0
0
0
0
0
0
T2CH0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SCON1
0
0
0
0
0
0
0
0
SBUF1
0
0
0
0
0
0
0
0
SMD1
0
0
0
0
0
0
0
0
SPIB
PR1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
T2CNB0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
T2V0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
T2R0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
T2C0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
T2CFG0
0
0
0
0
0
0
0
0
OWA
0
0
0
0
0
0
0
0
OWD
0
0
0
0
0
0
0
0
SPICN
0
0
0
0
0
0
0
0
SPICF
0
0
0
0
0
0
0
0
SPICK
0
0
0
0
0
0
0
0
ICDC
s
s
s
s
s
s
s
s
ICDF
s
s
s
s
s
s
s
s
ICDB
s
s
s
s
s
s
s
s
s
ICDA
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
ICDD
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
0
0
0
0
0
0
0
0
T2CNA1
24
0
0
____________________________________________________________________
Low-Power LCD Microcontroller
REGISTER
REGISTER BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
T2H1
0
0
0
0
0
0
0
0
T2RH1
0
0
0
0
0
0
0
0
T2CH1
0
0
0
0
0
0
0
0
T2CNA2
0
0
0
0
0
0
0
0
T2H2
0
0
0
0
0
0
0
0
T2RH2
0
0
0
0
0
0
0
0
T2CH2
0
0
0
0
0
0
0
0
T2CNB1
0
0
0
0
0
0
0
0
T2V1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
T2R1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
T2C1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
T2CNB2
T2V2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
T2R2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
T2C2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
T2CFG1
0
0
0
0
0
0
0
0
T2CFG2
0
0
0
0
0
0
0
0
____________________________________________________________________
25
MAXQ2000
Table 6. Peripheral Register Reset Values (continued)
System Timing
For maximum versatility, the MAXQ2000 generates its
internal system clock from one of five possible sources:
• Internal ring oscillator
• External high-frequency crystal or ceramic resonator,
using an internal oscillator
• External high-frequency clock source
A crystal warmup counter enhances operational reliability. Each time the external crystal oscillation must
restart, such as after exiting Stop mode, the device initiates a crystal warmup period of 65,536 oscillations.
This allows time for the crystal amplitude and frequency
to stabilize before using it as a clock source. While in
the warmup mode, the device can begin operation from
the internal ring oscillator and automatically switch
back to the crystal as soon as it is ready.
• External 32kHz crystal or ceramic resonator, using an
internal oscillator
• External 32kHz clock source
POWER-ON
RESET
RWT
RESET
STOP
RESET DOG
XDOG COUNT
RESET
WATCHDOG
TIMER
XDOG
STARTUP
TIMER
WATCHDOG RESET
WATCHDOG INTERRUPT
XDOG DONE
CLK INPUT
CRYSTAL KLL
HF
CRYSTAL
MAXQ2000
STOP
POWER-ON
RESET
CLOCK
DIVIDER
RING
GLITCH-FREE
MUX
GLITCH-FREE
MUX
ENABLE
CLOCK
GENERATION
SYSTEM CLOCK
ENABLE
WAKE-UP
ALARM
TIMERS
32kHz
CRYSTAL
DIV 1
DIV 2
DIV 4
DIV 8
32kHz
PWM
MAXQ2000
Low-Power LCD Microcontroller
SWB
INTERRUPT/SERIAL PORT
RESET
SELECTOR
DEFAULT
RING SELECT
STOP
INPUT
CRYSTAL
MONITOR
RGSL
ENABLE
RGMD
POWER-ON RESET
XDOG DONE
Figure 2. Clock Sources
26
____________________________________________________________________
Low-Power LCD Microcontroller
Advanced power-management features minimize
power consumption by dynamically matching the processing speed of the device to the required performance level. This means device operation can be
slowed and power consumption minimized during periods of reduced activity. When more processing power
is required, the microcontroller can increase its operating frequency. Software-selectable clock-divide operations allow flexibility, selecting whether a system clock
cycle is 1, 2, 4, or 8 oscillator cycles. By performing this
function in software, a lower power state can be
entered without the cost of additional hardware.
For extremely power-sensitive applications, three additional low-power modes are available:
• PMM1: divide-by-256 power-management mode
(PMME = 1, CD1:0 = 00b)
• PMM2: 32kHz power-management mode (PMME = 1,
CD1:0 = 11b)
• Stop mode (STOP = 1)
In PMM1, one system clock is 256 oscillator cycles, significantly reducing power consumption while the microcontroller functions at reduced speed. In PMM2, the
device can run even slower by using the 32kHz oscillator as the clock source. The optional switchback feature allows enabled interrupt sources including external
interrupts, UARTs, and the SPI module to quickly exit
the power-management modes and return to a faster
internal clock rate.
Power consumption reaches its minimum in Stop mode.
In this mode, the external oscillator, system clock, and all
processing activity is halted. Stop mode is exited when
an enabled external interrupt pin is triggered, an external
reset signal is applied to the RESET pin, or the RTC timeof-day alarm is activated. Upon exiting Stop mode, the
microcontroller can choose to wait for the external highfrequency crystal to complete its warmup period, or it
can start execution immediately from its internal ring
oscillator while the warmup period completes.
Interrupts
Multiple reset sources are available for quick response
to internal and external events. The MAXQ architecture
uses a single interrupt vector (IV), single interrupt-service routine (ISR) design. For maximum flexibility, interrupts can be enabled globally, individually, or by
module. When an interrupt condition occurs, its individual flag is set, even if the interrupt source is disabled at
the local, module, or global level. Interrupt flags must
be cleared within the user-interrupt routine to avoid
repeated interrupts from the same source. Application
software must ensure a delay between the write to the
flag and the RETI instruction to allow time for the interrupt hardware to remove the internal interrupt condition.
Asynchronous interrupt flags require a one-instruction
delay and synchronous interrupt flags require a twoinstruction delay.
When an enabled interrupt is detected, software jumps
to a user-programmable interrupt vector location. The
IV register defaults to 0000h on reset or power-up, so if
it is not changed to a different address, the user program must determine whether a jump to 0000h came
from a reset or interrupt source.
Once software control has been transferred to the ISR,
the interrupt identification register (IIR) can be used to
determine if a system register or peripheral register
was the source of the interrupt. The specified module
can then be interrogated for the specific interrupt
source and software can take appropriate action.
Because the interrupts are evaluated by user software,
the user can define a unique interrupt priority scheme
for each application. The following interrupt sources are
available. Sources marked with an asterisk are not
available on the 56-pin version.
• Watchdog Interrupt
• External Interrupts 0 to 15 (INT10*, INT11*)
• RTC Time-of-Day and Subsecond Alarms
• Serial Port 0 Receive and Transmit Interrupts
• Serial Port 1 Receive and Transmit Interrupts*
• SPI Mode Fault, Write Collision, Receive Overrun, and
Transfer Complete Interrupts
• Timer 0 Low Compare, Low Overflow,
Capture/Compare, and Overflow Interrupts
• Timer 1 Low Compare, Low Overflow,
Capture/Compare, and Overflow Interrupts
• Timer 2 Low Compare, Low Overflow,
Capture/Compare, and Overflow Interrupts
• 1-Wire Presence Detect, Transmit Buffer Empty,
Transmit Shift Register Empty, Receive Buffer Full,
and Shift Register Full, Short, and Low Interrupts*
Reset Sources
Several reset sources are provided for microcontroller
control. Although code execution is halted in the reset
state, the high-frequency oscillator and the ring oscillator
continue to oscillate. Internal resets such as the poweron and watchdog resets assert the RESET pin low.
____________________________________________________________________
27
MAXQ2000
Power Management
MAXQ2000
Low-Power LCD Microcontroller
Power-On Reset
An internal power-on reset circuit enhances system reliability. This circuit forces the device to perform a
power-on reset whenever a rising voltage on VDDIO
climbs above approximately 1.8V. At this point the following events occur:
• All registers and circuits enter their reset state
• The POR flag (WDCN.7) is set to indicate the source
of the reset
• The ring oscillator becomes the clock source and
• Code execution begins at location 8000h
Watchdog Timer Reset
The watchdog timer functions are described in the
MAXQ Family User’s Guide. Execution resumes at location 8000h following a watchdog timer reset.
External System Reset
Asserting the external RESET pin low causes the device
to enter the reset state. The external reset functions as
described in the MAXQ Family User’s Guide. Execution
resumes at location 8000h after the RESET pin is
released.
I/O Ports
The microcontroller uses the type C and type D bidirectional I/O ports described in the MAXQ Family User’s
Guide. The use of three port types allows for maximum
flexibility when interfacing to external peripherals. Each
port has eight independent, general-purpose I/O pins
and three configure/control registers. Many pins support
alternate functions such as timers or interrupts, which are
enabled, controlled, and monitored by dedicated peripheral registers. Using the alternate function automatically
converts the pin to that function.
Type-C port pins have Schmitt Trigger receivers and
full CMOS output drivers, and can support alternate
functions. The pin is either tri-stated or weak pullup
when defined as an input, dependent on the state of
the corresponding bit in the output register.
Type-D port pins have Schmitt Trigger receivers and
full CMOS output drivers, and can support alternate
functions. The pin is either tri-stated or weak pullup
when defined as an input, dependent on the state of
the corresponding bit in the output register. All type-D
pins also have interrupt capability.
VDDIO
WEAK
MUX
PD.x
SF DIRECTION
VDDIO
SF ENABLE
MUX
PO.x
SF OUTPUT
MAXQ2000
I/O PAD
PIN.x
PI.x OR SF INPUT
FLAG
INTERRUPT
FLAG
DETECT
CIRCUIT
EIES.x
TYPE-D PORT ONLY
Figure 3. Type-C/D Port Pin Schematic
28
____________________________________________________________________
Low-Power LCD Microcontroller
The hardware multiplier module performs high-speed
multiply, square, and accumulate operations, and can
complete a 16-bit x 16-bit multiply-and-accumulate
operation in a single cycle. The hardware multiplier
consists of two 16-bit parallel-load operand registers
(MA, MB), an accumulator that is formed by up to three
16-bit parallel registers (MC2, MC1, and MC0), and a
status/control register (MCNT). Loading the registers
can automatically initiate the operation, saving time on
repetitive calculations. The accumulate function of the
hardware multiplier is an essential element of digital filtering, signal processing, and PID control systems.
The hardware multiplier module supports the following
operations:
• Multiply unsigned (16 bit x 16 bit)
• Multiply signed (16 bit x 16 bit)
• Multiply-Accumulate unsigned (16 bit x 16 bit)
•
•
•
•
Multiply-Accumulate signed (16 bit x 16 bit)
Square unsigned (16 bit)
Square signed (16 bit)
Square-Accumulate unsigned (16 bit)
• Square-Accumulate signed (16 bit)
Real-Time Clock
A binary real-time clock keeps the time of day in
absolute seconds with 1/256-second resolution. The
32-bit second counter can count up to approximately
136 years and be translated to calendar format by the
application software. A time-of-day alarm and independent subsecond alarm can cause an interrupt, or wake
the device from Stop mode.
The independent subsecond alarm runs from the same
RTC, and allows the application to perform periodic
interrupts up to ones with a granularity of approximately
3.9ms. This creates an additional timer that can be
used to measure long periods without performance
degradations. Traditionally, long time periods have
been measured using multiple interrupts from shorter
programmable timers. Each timer interrupt required
servicing, with each accompanying interruption slowing
system operation. By using the RTC subsecond timer
as a long-period timer, only one interrupt is needed,
eliminating the performance hit associated with using a
shorter timer.
An internal crystal oscillator clocks the RTC using integrated 6pF load capacitors, and give the best performance when mated with a 32.768kHz crystal rated for a
6pF load. No external load capacitors are required.
Higher accuracy can be obtained by supplying an external clock source to the RTC. The frequency accuracy of
a crystal-based oscillator circuit is dependent upon crystal accuracy, the match between the crystal and the
oscillator capacitor load, ambient temperature, etc. An
error of 20ppm is equivalent to approximately 1 minute
per month.
Programmable Timers
The microcontroller incorporates three 16-bit programmable instances of the Timer 2 peripheral, denoted
TR2A, TR2B, and TR2C. These timers can be used in
counter/timer/capture/compare/PWM functions, allowing precise control of internal and external events.
Timer 2 supports optional single-shot, external gating,
and polarity control options.
Timer 2
The Timer 2 peripheral includes the following:
• 16-bit autoreload timer/counter
• 16-bit capture
• 16-bit counter
• 8-bit capture and 8-bit timer
• 8-bit counter and 8-bit timer
Watchdog Timer
An internal watchdog timer greatly increases system
reliability. The timer resets the device if software execution is disturbed. The watchdog timer is a free-running
counter designed to be periodically reset by the application software. If software is operating correctly, the
counter will be periodically reset and never reach its
maximum count. However, if software operation is interrupted, the timer does not reset, triggering a system
reset and optionally a watchdog timer interrupt. This
protects the system against electrical noise or electrostatic discharge (ESD) upsets that could cause uncontrolled processor operation. The internal watchdog
timer is an upgrade to older designs with external
watchdog devices, reducing system cost and simultaneously increasing reliability.
____________________________________________________________________
29
MAXQ2000
High-Speed Hardware Multiplier
MAXQ2000
Low-Power LCD Microcontroller
The watchdog timer is controlled through bits in the
WDCN register. Its timeout period can be set to one of
four programmable intervals ranging from 212 to 221
system clocks in its default mode, allowing flexibility to
support different types of applications. The interrupt
occurs 512 system clocks before the reset, allowing the
system to execute an interrupt and place the system in
a known, safe state before the device performs a total
system reset. At 16MHz, watchdog timeout periods can
be programmed from 256µs to 33.5s, depending on the
system clock mode.
Serial Peripherals
The microcontroller incorporates several common serial-peripheral interfaces for interconnection with popular
external devices. Multiple formats provide maximum
flexibility and lower cost when designing a system.
UARTs
Serial interfacing is provided through one (-RBX) or two
(-RAX) 8051-style universal synchronous/asynchronous
receiver/transmitters. The UART allows the device to
conveniently communicate with other RS-232 interfaceenabled devices, as well as PCs and serial modems
when paired with an external RS-232 line driver/receiver. The dual independent UARTs can communicate
simultaneously at different baud rates with two separate
peripherals. The UART can detect framing errors and
indicate the condition through a user-accessible software bit.
The time base of the serial ports is derived from either a
division of the system clock or the dedicated baud
clock generator. The following table summarizes the
operating characteristics as well as the maximum baud
rate of each mode:
MODE
1-Wire Bus Master
The MAXQ2000-RAX includes a Dallas Semiconductor
1-Wire bus master, which communicates to other 1-Wire
peripherals, including iButton® products, through a
simple bidirectional signaling scheme over a single
electrical connection. The bus master provides complete control of the 1-Wire bus and transmit and receive
activities, and generates all timing and control
sequences of the 1-Wire bus. Communication between
the CPU and the bus master is achieved through
read/write access of the 1-Wire master address (OWA)
and 1-Wire master data (OWD) peripheral registers.
Detailed operation of the 1-Wire bus is described in the
Book of iButton Standards (www.maxim-ic.com/
iButtonbook).
Serial-Peripheral Interface (SPI) Module
The SPI port is a common, high-speed, synchronous
peripheral interface that shifts a bit stream of variable
length and data rate between the microcontroller and
other peripheral devices. The SPI can be used to communicate with other microcontrollers, serial shift registers, or display drivers. Multiple master and slave
modes permit communication with multiple devices in
the same system. Programmable clock frequency,
character lengths, polarity, and error handling enhance
the usefulness of the peripheral. The maximum baud
rate of the SPI interface is 1/2 the system clock for master mode operation and 1/8 the system clock for slave
mode operation.
START BITS
DATA BITS
STOP BIT
Mode 0
Synchronous
N/A
8
N/A
4Mbps
Mode 1
Asynchronous
1
8
1
500kbps
Mode 2
Asynchronous
1
8+1
1
500kbps
Mode 3
Asynchronous
1
8+1
1
500kbps
iButton is a registered trademark of Dallas Semiconductor Corp.
30
MAX BAUD RATE
AT 16MHz
TYPE
____________________________________________________________________
Low-Power LCD Microcontroller
LCD Controller
Embedded debugging capability is available through
the JTAG-compatible Test Access Port. Embedded
debug hardware and embedded ROM firmware provide in-circuit debugging capability to the user application, eliminating the need for an expensive in-circuit
emulator. Figure 4 shows a block diagram of the in-circuit debugger. The in-circuit debug features include:
The MAXQ2000 microcontroller incorporates an LCD
controller that interfaces to common low-voltage displays. By incorporating the LCD controller into the
microcontroller, the design requires only an LCD glass
rather than a considerably more expensive LCD module. Every character in an LCD glass is composed of
one or more segments, each of which is activated by
selecting the appropriate segment and common signal.
The microcontroller can multiplex combinations of up to
33 segment (SEG0–SEG32) outputs and four common
signal outputs (COM0–COM3). Unused segment outputs can be used as general-purpose port pins.
• a hardware debug engine,
• a set of registers able to set breakpoints on register,
code, or data accesses, and
• a set of debug service routines stored in the utility
ROM.
The embedded hardware debug engine is an independent hardware block in the microcontroller. The debug
engine can monitor internal activities and interact with
selected internal registers while the CPU is executing
user code. Collectively, the hardware and software features allow two basic modes of in-circuit debugging:
• Background mode allows the host to configure and set
up the in-circuit debugger while the CPU continues to
execute the application software at full speed. Debug
mode can be invoked from background mode.
• Debug mode allows the debug engine to take control
of the CPU, providing read/write access to internal registers and memory, and single-step trace operation.
MAXQ2000
DEBUG
SERVICE
ROUTINES
(UTILITY ROM)
CPU
DEBUG
ENGINE
TMS
TCK
TDI
TDO
TAP
CONTROLLER
CONTROL
BREAKPOINT
ADDRESS
DATA
The segments are easily addressed by writing to dedicated display memory. Once the LCD controller settings and display memory have been initialized, the
17-byte display memory is periodically scanned, and
the segment and common signals are generated automatically at the selected display frequency. No additional processor overhead is required while the LCD
controller is running. Unused display memory can be
used for general-purpose storage.
The design is further simplified and cost-reduced by
the inclusion of software-adjustable internal voltage
dividers to control display contrast, using either VDDIO
or an external voltage. If desired, contrast can also be
controlled with an external resistance. The features of
the LCD controller include the following:
• Automatic LCD segment and common-drive signal
generation
• Four display modes supported:
Static (COM0)
1/2 duty multiplexed with 1/2 bias voltages (COM0,
COM1)
1/3 duty multiplexed with 1/3 bias voltages (COM0,
COM1, COM2)
1/4 duty multiplexed with 1/3 bias voltages (COM0,
COM1, COM2, COM3)
• Up to 36 segment outputs and four common-signal
outputs
• 17 bytes (136 bits) of display memory
• Flexible LCD clock source, selectable from 32kHz or
HFClk / 128
• Adjustable frame frequency
• Internal voltage-divider resistors eliminate requirement for external components
• Internal adjustable resistor allows contrast adjustment
without external components
Figure 4. In-Circuit Debugger
____________________________________________________________________
31
MAXQ2000
In-Circuit Debug
MAXQ2000
Low-Power LCD Microcontroller
• Flexibility to use external resistors to adjust drive voltages and current capacity
reduces component count and board space, critical
factors in the design of portable systems.
A simple LCD-segmented glass interface example
demonstrates the minimal hardware required to interface to a MAXQ2000 microcontroller. A two-character
LCD is controlled, with each character containing
seven segments plus decimal point. The LCD controller
is configured for 1/2 duty cycle operation, meaning the
active segment is controlled using a combination of
segment signals, and COM0 or COM1 signals are used
to select the active display.
The MAXQ2000 is ideally suited for applications such
as medical instrumentation, portable blood glucose
equipment, and data collection devices. For blood glucose measurement, the microcontroller integrates an
SPI interface that directly connects with analog front
ends for measuring test strips.
Applications
The low-power, high-performance RISC architecture of
the MAXQ2000 makes it an excellent fit for many
portable or battery-powered applications that require
cost-effective computing. The high-throughput core is
complemented by a 16-bit hardware multiplier-accumulator, allowing the implementation of sophisticated computational algorithms. Applications benefit from a wide
range of peripheral interfaces, allowing the microcontroller to communicate with many external devices. With
integrated LCD support of up to 100 or 132 segments,
applications can support complex user interfaces.
Displays are driven directly with no additional external
hardware required. Contrast can be adjusted using a
built-in, adjustable resistor. The simplified architecture
MAXQ2000
Additional Documentation
Designers must have four documents to fully use all the
features of this device. This data sheet contains pin
descriptions, feature overviews, and electrical specifications. Errata sheets contain deviations from published specifications. The user’s guides offer detailed
information about device features and operation. The
following documents can be downloaded from
www.maxim-ic.com/microcontrollers.
• The MAXQ2000 errata sheet, available at
www.maxim-ic.com/errata.
• The MAXQ Family User’s Guide, which contains
detailed information on core features and operation,
including programming.
• The MAXQ Family User’s Guide: MAXQ2000
Supplement, which contains detailed information on
features specific to the MAXQ2000.
SEG0
SEG4
SEG1
SEG5
SEG2
SEG3
SEG6
SEG7
SEG0:7
COM0
CONNECTED TO DARK GREY SEGMENTS
COM1
CONNECTED TO LIGHT GREY SEGMENTS
Figure 5. Two-Character, 1/2 Duty, LCD Interface Example
32
____________________________________________________________________
Low-Power LCD Microcontroller
• Integrated development environments (IDEs)
• JTAG-to-serial converters for programming and
debugging
A partial list of development tool vendors can be found
on our website at www.maxim-ic.com/microcontrollers.
Technical support is available through email at
[email protected]
A variety of highly versatile, affordably priced development
tools for this microcontroller are available from Maxim/
Dallas Semiconductor and third-party suppliers, including:
• Compilers
• In-circuit emulators
52 P7.0/TX0/INT14
53 P7.1/RX0/INT15
54 VLCD
55 VLCD1
56 VLCD2
57 VADJ
58 SEG0/P0.0
59 SEG1/P0.1
60 SEG2/P0.2
61 SEG3/P0.3
62 SEG4/P0.4/INT0
63 SEG5/P0.5/INT1
65 SEG7/P0.7/INT3
64 SEG6/P0.6/INT2
66 SEG8/P1.0
68 SEG10/P1.2
TOP VIEW
67 SEG9/P1.1
Pin Configurations
SEG11/P1.3
1
51
HFXIN
SEG12/P1.4
2
50
HFXOUT
SEG13/P1.5
3
49
VDD
SEG14/P1.6
4
48
P6.5/T0/WKOUT1
SEG15/P1.7
5
47
P6.4/T0B/WKOUT0
SEG16/P2.0
6
46
P6.3/T2/OW_IN
SEG17/P2.1
7
45
P6.2/T2B/OW_OUT
SEG18/P2.2
8
44
P6.1/T1/INT13
SEG19/P2.3
9
43
P6.0/T1B/INT12
SEG20/P2.4
10
42
GND
SEG21/P2.5
11
41
P5.7/MISO
SEG22/P2.6
12
40
P5.6/SCLK
SEG23/P2.7
13
39
P5.5/MOSI
SEG24/P3.0
14
38
P.4/SS
SEG25/P3.1
15
37
P5.3/TX1/INT11
SEG26/P3.2
16
36
P5.2/RX1/INT10
SEG27/P3.3
17
35
32KOUT
MAXQ2000
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
SEG28/P3.4/INT4
SEG29/P3.5/INT5
SEG30/P3.6/INT6
SEG31/P3.7/INT7
SEG32
SEG33/COM3
SEG34/COM2
SEG35/COM1
COM0
VDDIO
GND
P4.0/TCK/INT8
P4.1/TDI/INT9
P4.2/TMS
P4.3/TDO
RESET
32KIN
(132-SEGMENT LCD)
QFN
____________________________________________________________________
33
MAXQ2000
Development and
Technical Support
Low-Power LCD Microcontroller
SEG8/P1.0
1
42
HFXIN
SEG9/P1.1
2
41
HFXOUT
SEG10/P1.2
3
40
VDD
SEG11/P1.3
4
39
P6.5/T0/WKOUT1
SEG12/P1.4
5
38
P6.4/T0B/WKOUT0
SEG13/P1.5
6
37
P6.1/T1/INT13
SEG14/P1.6
7
36
P6.0/T1B/INT12
SEG15/P1.7
8
35
GND
SEG16/P2.4
9
34
P5.7/MISO
SEG17/P2.5
10
33
P5.6/SCLK
SEG18/P2.6
11
32
P5.5/MOSI
SEG19/P2.7
12
31
P5.4/SS
SEG20/P3.4/INT4
13
30
32KOUT
SEG21/P3.5/INT5
14
29
32KIN
MAXQ2000
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SEG23/P3.7/INT7
SEG24
SEG25/COM3
SEG26/COM2
SEG27/COM1
COM0
VDDIO
GND
P4.0/TCK/INT8
P4.1/TDI/INT9
P4.2/TMS
P4.3/TDO
RESET
(100-SEGMENT LCD)
TQFN
34
43 P7.0/TXO/INT14
44 P7.1/RXO/INT15
45 VLCD
46 VLCD1
47 VLCD2
48 VADJ
49 SEG0/P0.0
50 SEG1/P0.1
51 SEG2/P0.2
52 SEG3/P0.3
53 SEG4/P0.4/INT0
54 SEG5/P0.5/INT1
55 SEG6/P0.6/INT2
56 SEG7/P0.7/INT3
TOP VIEW
SEG22/P3.6/INT6
MAXQ2000
Pin Configurations (continued)
____________________________________________________________________
Low-Power LCD Microcontroller
VSS
1-WIRE EEPROM
GLUCOSE MICROCONTROLLER
SERIAL DATA
DOWNLOAD
CONNECTOR
RS-232 SERIAL PORT
PC_RX
+3.3V
TX
+3.3V
RS-232
RX
PC_TX
CHIP
DATA
CPOUT
P7.1RX0/INT15
5kΩ
VDDIO
VSS
CAL PORT
CONNECTOR
MAXQ2000
UART1
P7.0TX0/INT14
INTERFACE CABLE
GND
VLCD (+3.3V)
GND
GND
METER CAL
PARAMETERS
AND PATIENT
DATA STORAGE
P6.2/T2B/OW_OUT
1-WIRE
INTERFACE
1-WIRE EPROM
DATA
P6.3/T2/OW_IN
TEST STRIP CAL
PARAMETERS
VSS
GND
VLCD (+3.3V)
JTAG
DOWNLOAD/
DEBUG
CONNECTOR
TDO
P4.3/TDO
TMS
P4.2/TMS
VDDIO
P5.5/MOSI
TDI
P4.1/TDI/INT9
TCK
P4.0/TCK/INT8
JTAG
DIN
P5.7/MISO
4-WIRE
SPI
INTERFACE
DOUT
P5.6/SCLK
SCLK
P5.4/SS
UPIO2
UPIO3
CSI
UPIO4
GNDIO
GNDIO
VDDIO
MAX1358
MAX1359
MAX1360
P6.1/T1/INT13
PIEZO
BUZZER
VBATT
VDDIO
32KCLK
TIMER 0
P6.0/T1B/INT12
VDD
MAX
1678
VDDIO
STRIP
INSERTED
FBA
TEST STRIP
PORT
CONNECTOR
AGND
GNDIO
200kΩ
ON
SWA
GND
200kΩ
OUTA
DVDD
2 AAA OR
1 LITHIUM
COIN CELL
(+1.8V TO
+3.6V)
GNDIO
VDDIO
DIFFERENTIALLY DRIVEN AT
±6.6V AND -2kHz TO 10kHz
AVDD
DACA
DGND
VSS
TEST
STRIP
OUTB
SEG31/P3.7/INT7
P6.5/T0/WKOUT
OR
SEG29/P3.5/INT5
UPI01
SWB
WAKEUP
FBB
VSS
GNDIO
VLCD (+3.3V)
VLCD
REGULATED
+3.3V
CPOUT
ADC
DACB
SNO1
VSS
VLCD1
116 SEGMENT
LCD GLASS
CHARGEPUMP
DOUBLER
CF-
VLCD2
SEG[28:5]
SEG[0:3]
SEG[32]
SNC1
OUT1
VADJ
COM[3:1]/SEG[35:33]
LINEAR
REG
VSS
COM[0]
STRIP
INSERTED
INM1
REG
LCD
DRIVERS
VSS
SCM1
CF+
INP1
BG
REF
DVDD
NOTE THAT UP TO 132 LCD
SEGMENTS CAN BE DRIVEN IF
OTHER MUXED PIN FUNCTIONS
ARE NOT USED
SNO2
GNDIO
32/64kB
FLASH/
MASK
SCM2
RTC AND
SYSTEM
TIMERS/
ALARMS
32KOUT
32K
OSC
200kΩ
200kΩ
200kΩ
VSS
32KOUT
32KIN
32kHz MICRO CLOCK (OPTIONAL) CLK32K
HFXIN
HIGH-FREQUENCY MICRO CLOCK
32K
OSC
1-5MHz
FLL
VSS
AIN1
REMOTE
TEMPERATURE
MEASUREMENT
DIODE
AIN2
CLK
HF
OSC HFXOUT
VDDIO
SEG30/
MEM P3.6/INT6
P5.3/
UP TX1/INT11
P5.2/
DOWN RX1/INT10
SNC2
VSS 32KIN
32.768kHz
WATCH
XTAL
16-BIT RISC
MICRO
INT
INT
INT
GNDIO
VSS
RESET
SEG4/P0.4/INTO
RESET
MAX1358/9/60 INTERRUPT
INT
WATCHDOG
TIMER
GLUCOSE METER CIRCUIT BOARD
____________________________________________________________________
35
MAXQ2000
Typical Operating Circuit
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/DallasPackInfo).
68L QFN.EPS
MAXQ2000
Low-Power LCD Microcontroller
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM
1
C
21-0122
2
36
____________________________________________________________________
Low-Power LCD Microcontroller
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM
1
C
21-0122
2
____________________________________________________________________
37
MAXQ2000
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/DallasPackInfo).
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/DallasPackInfo).
56L THIN QFN.EPS
MAXQ2000
Low-Power LCD Microcontroller
38
____________________________________________________________________
Low-Power LCD Microcontroller
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 39
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Dallas Semiconductor Corporation.
is a registered trademark of Maxim Integrated Products.
MAXQ2000
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/DallasPackInfo).