Revised April 2005 74VHCT245A Octal Buffer/Line Driver with 3-STATE Outputs General Description Features The VHCT245A is an advanced high speed CMOS octal bus transceiver fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The VHCT245A is intended for bidirectional asynchronous communication between data busses. The direction of data transmission is determined by the level of the T/R input. The enable input can be used to disable the device so that the busses are effectively isolated. ■ High Speed: tPD 5.4 ns (typ) at VCC 5V ■ Power Down Protection on Inputs and Outputs ■ Low Power Dissipation: ICC 4 PA (Max) @ TA 25qC ■ Pin and Function Compatible with 74HCT245 Protection circuits ensure that 0V to 7V can be applied to the input and output (Note 1) pins without regard to the supply voltage. These circuits prevent device destruction due to mismatched supply and input/output voltages. This device can be used to interface 5V to 3V systems and two supply systems such as battery back up. Note 1: Outputs in OFF-State Ordering Code: Order Number Package Number 74VHCT245AM 74VHCT245ASJ 74VHCT245AMTC 74VHCT245AN Package Description M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC20 N20A 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDED J-STD-020B. Logic Symbol Connection Diagram IEEE/IEC © 2005 Fairchild Semiconductor Corporation DS500004 www.fairchildsemi.com 74VHCT245A Octal Buffer/Line Driver with 3-STATE Outputs March 1997 74VHCT245A Pin Descriptions Pin Names Description OE Output Enable Input T/R Transmit/Receive Input A0–A7 Side A Inputs or 3-STATE Outputs B0–B7 Side B Inputs or 3-STATE Outputs Truth Table Inputs Outputs OE T/R L L Bus B Data to Bus A L H Bus A Data to Bus B H X HIGH-Z State H HIGH Voltage Level L LOW Voltage Level X Immaterial www.fairchildsemi.com 2 Recommended Operating Conditions (Note 6) 0.5V to 7.0V 0.5V to 7.0V Supply Voltage (VCC) DC Input Voltage (VIN) 4.5V to 5.5V Supply Voltage (VCC) DC Output Voltage (VOUT ) 0V to 5.5V Input Voltage (VIN) (Note 3) (Note 4) Input Diode Current (IIK) Output Diode Current (IOK) (Note 5) DC Output Current (IOUT ) DC VCC/GND Current (ICC) Storage Temperature (TSTG) 0.5V to VCC 0.5V 0.5V to 7.0V 20 mA r20 mA r25 mA r75 mA 65qC to 150qC Output Voltage (VOUT) 0V to VCC 0V to 5.5V 40qC to 85qC Operating Temperature (TOPR) Input Rise and Fall Time (tr, tf) VCC 5.0V r 0.5V 0 ns/V a 20 ns/V Note 2: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications. Lead Temperature (TL) 260qC (Soldering, 10 seconds) (Note 3) (Note 4) Note 3: HIGH or LOW state. IOUT absolute maximum rating must be observed. OV. Note 4: When outputs are in OFF-State or when VCC Note 5: VOUT GND, V OUT ! VCC (Outputs Active). Note 6: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH VIL VOH Parameter TA Min 25qC TA Typ Max 40qC to 85qC Min 4.5 2.0 2.0 Input Voltage 5.5 2.0 2.0 Max 4.5 0.8 0.8 Input Voltage 5.5 0.8 0.8 HIGH Level LOW Level 3-STATE Output 4.5 4.40 4.50 3.94 V 4.40 V 3.80 V Input Leakage ICC Quiescent Supply VIH IOH 50 PA or VIL IOH 8 mA VIN VIH IOL 50 PA or VIL IOL 8 mA 0.1 V 0.36 0.44 V 5.5 r0.25 r2.5 PA 0–5.5 r0.1 r1.0 PA VIN 5.5V or GND 5.5 4.0 40.0 PA VIN VCC or GND 5.5 1.35 1.50 mA VIN 3.4V Off-State Current IIN Conditions 0.1 4.5 0.0 Units V LOW Level Output Voltage IOZ (V) HIGH Level Output Voltage VOL V CC VIN VIN VOUT VIH or VIL VCC or GND Current Current ICCT Maximum ICC/Input Other Input IOFF Output Leakage Current 0.0 0.5 5.0 PA VOUT VCC or GND 5.5V (Power Down State) 3 www.fairchildsemi.com 74VHCT245A Absolute Maximum Ratings(Note 2) 74VHCT245A Noise Characteristics Symbol VCC Parameter TA 25qC (V) Typ Limits Units Conditions VOLP (Note 7) Quiet Output Maximum Dynamic VOL 5.0 1.2 1.6 V CL 50 pF VOLV (Note 7) Quiet Output Minimum Dynamic VOL 5.0 1.2 1.6 V CL 50 pF VIHD (Note 7) Minimum HIGH Level Dynamic Input Voltage 5.0 2.0 V CL 50 pF VILD (Note 7) Maximum LOW Level Dynamic Input Voltage 5.0 0.8 V CL 50 pF Note 7: Parameter guaranteed by design. AC Electrical Characteristics Symbol Parameter tPLH Propagation Delay tPHL Time tPZL 3-STATE Output tPZH Enable Time tPLZ 3-STATE Output tPHZ Disable Time tOSLH Output to tOSHL Output Skew CIN V CC TA (V) Min 5.0 r 0.5 5.0 r 0.5 5.0 r 0.5 25qC Units Conditions Max Min Max 4.9 7.7 1.0 8.5 5.4 8.7 1.0 9.5 9.4 13.8 1.0 15.0 9.9 14.8 1.0 16.0 10.1 15.4 1.0 16.5 ns RL 1.0 1.0 ns (Note 8) 10 10 pF VCC Open 13 pF VCC 5.0V 16 pF (Note 9) 5.0 r 0.5 Input 40qC to 85qC TA Typ 4 ns ns RL 1 k: 1 k: CL 15 pF CL 50 pF CL 15 pF CL 50 pF CL 50 pF Capacitance COUT Output Capacitance CPD Power Dissipation Capacitance Note 8: Parameter guaranteed by design. tOSLH |tPLH max t PLH min|; tOSHL |tPHL max tPHL min| Note 9: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr.) CPD * VCC * fIN ICC/8 (per F/F). The total CPD when n pcs. of the Octal D Flip-Flop operates can be calculated by the equation: CPD (total) 20 12n. www.fairchildsemi.com 4 74VHCT245A Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com 74VHCT245A Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 6 74VHCT245A Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 7 www.fairchildsemi.com 74VHCT245A Octal Buffer/Line Driver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8