MOTOROLA MC74HC4060DT

SEMICONDUCTOR TECHNICAL DATA
# ! " High–Performance Silicon–Gate CMOS
The MC54/74HC4060 is identical in pinout to the standard CMOS
MC14060B. The device inputs are compatible with standard CMOS outputs;
with pullup resistors, they are compatible with LSTTL outputs.
This device consists of 14 master–slave flip–flops and an oscillator with a
frequency that is controlled either by a crystal or by an RC circuit connected
externally. The output of each flip–flop feeds the next, and the frequency at
each output is half that of the preceding one. The state of the counter
advances on the negative–going edge of Osc In. The active–high Reset is
asynchronous and disables the oscillator to allow very low power consumption during standby operation.
State changes of the Q outputs do not occur simultaneously because of
internal ripple delays. Therefore, decoded output signals are subject to
decoding spikes and may need to be gated with Osc Out 2 of the HC4060.
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
1
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 390 FETs or 97.5 Equivalent Gates
ORDERING INFORMATION
MC54HCXXXXJ
MC74HCXXXXN
MC74HCXXXXDT
Q12
1
16
VCC
Q13
2
15
Q10
Q14
3
14
Q8
Q6
4
13
Q9
Q5
5
12
RESET
Q4
Q7
6
11
OSC IN
Q5
Q4
7
10
OSC OUT 1
Q6
GND
8
9
OSC OUT 2
OSC OUT 2
9
7
5
OSC IN
11
4
6
14
13
15
1
2
3
RESET
Q7
Q8
Q9
FUNCTION TABLE
Q10
Q12
Clock
Reset
Output State
X
L
L
H
No Change
Advance to Next State
All Outputs are Low
Q13
Q14
12
PIN 16 = VCC
PIN 8 = GND
10/95
 Motorola, Inc. 1995
Ceramic
Plastic
TSSOP
PIN ASSIGNMENT
LOGIC DIAGRAM
OSC OUT 1
10
DT SUFFIX
TSSOP PACKAGE
CASE 948F–01
16
1
REV 6
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MC54/74HC4060
MAXIMUM RATINGS*
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
Value
Unit
– 0.5 to + 7.0
V
V
Vin
DC Input Voltage (Referenced to GND)
– 1.5 to VCC + 1.5
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air, Plastic or Ceramic DIP†
TSSOP Package†
750
450
mW
Tstg
Storage Temperature
– 65 to + 150
_C
Iin
TL
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
v
v
_C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or TSSOP Package)
(Ceramic DIP)
260
300
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
Min
Max
Unit
2.5**
6.0
V
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
(Figure 1)
0
VCC
V
– 55
+ 125
_C
VCC = 2.0 V
0
1000
ns
VCC = 4.5 V
0
500
VCC = 6.0 V
0
400
** The oscillator is guaranteed to function at 2.5 V minimum. However, parametrics are tested at
2.0 V by driving Pin 11 with an external clock source.
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
– 55 to
25_C
85_C
125_C
Unit
VIH
Minimum High–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
42
V
VIL
Maximum Low–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
Minimum High–Level Output
Voltage (Q4–Q10, Q12–Q14)
Vin = VIH or VIL
|Iout|
20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
VOH
Vin = VIH or VIL |Iout|
|Iout|
VOL
Maximum Low–Level Output
Voltage (Q4–Q10, Q12–Q14)
4.0 mA
5.2 mA
Vin = VIH or VIL
|Iout|
20 µA
Vin = VIH or VIL |Iout|
|Iout|
4.0 mA
5.2 mA
V
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
MOTOROLA
2
High–Speed CMOS Logic Data
DL129 — Rev 6
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MC54/74HC4060
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) (Continued)
Guaranteed Limit
Symbol
VOH
Parameter
Test Conditions
Minimum High–Level Output
Voltage (Osc Out 1, Osc Out 2)
Vin = VCC or GND
IIoutI
20 µA
Vin = VCC or GND IIoutI
IIoutI
VOL
Maximum Low–Level Output
Voltage (Osc Out 1, Osc Out 2)
Vin = VCC or GND
IIoutI
20 µA
Vin = VCC or GND IIoutI
IIoutI
Iin
ICC
1.0 mA
1.3 mA
1.0 mA
1.3 mA
VCC
V
– 55 to
25_C
85_C
125_C
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
Unit
V
V
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
µA
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
6.0
8
80
160
µA
NOTE: Information on typical parametric values can be found in Chapter 4.
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
VCC
V
– 55 to
25_C
85_C
125_C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0
4.5
6.0
5.0
25
29
4.0
20
24
3.4
17
20
MHz
tPLH,
tPHL
Maximum Propagation Delay, Osc In to Q4*
(Figures 1 and 4)
2.0
4.5
6.0
530
106
91
665
133
114
795
159
135
ns
tPLH,
tPHL
Maximum Propagation Delay, Osc In to Q14*
(Figures 1 and 4)
2.0
4.5
6.0
1600
320
272
2000
400
344
2400
480
408
ns
tPHL
Maximum Propagation Delay, Reset to Any Q
(Figures 2 and 4)
2.0
4.5
6.0
240
48
41
300
60
51
360
72
61
ns
tPLH,
tPHL
Maximum Propagation Delay, QN to QN + 1
(Figures 3 and 4)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
Maximum Input Capacitance
—
10
10
10
pF
Cin
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
* For TA = 25_C and CL = 50 pF, typical propagation delay from Osc In to other Q outputs may be calculated with the following equations:
VCC = 2.0 V: tP = [205 + 107.5(N – 1)] ns
VCC = 4.5 V: tP = [41 + 21.5(N – 1)] ns
VCC = 6.0 V: tP = [35 + 18.3(N – 1)] ns
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Package)*
35
pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
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MC54/74HC4060
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Guaranteed Limit
VCC
V
– 55 to
25_C
Minimum Recovery Time, Reset Inactive to Osc In*
(Figure 2)
2.0
4.5
6.0
tw
Minimum Pulse Width, Osc In
(Figure 1)
tw
85_C
125_C
100
20
17
125
25
21
150
30
26
ns
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
Minimum Pulse Width, Reset
(Figure 2)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
Symbol
Parameter
trec
tr, tf
Unit
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
* Osc In driven with external clock.
PIN DESCRIPTIONS
OUTPUTS
INPUTS
Q4 – Q10, Q12 – Q14 (Pins 7, 5, 4, 6, 14, 13, 15, 1, 2, 3)
Active–high outputs. Each QN output divides the oscillator
frequency by 2N. The user should note that Q1, Q2, Q3, and
Q11 are not available as outputs.
Osc In (Pin 11)
Negative–edge triggering clock input. A high–to–low transition on this input advances the state of the counter. Osc In
may be driven by an external clock source.
Osc Out 1, Osc Out 2 (Pins 10, 9)
Oscillator outputs. These pins are used in conjunction with
Osc In and the external components to form an oscillator.
(See Figures 4 and 5). When Osc In is being driven with an
external clock source, Osc Out 1 and Osc Out 2 must be left
open circuited. With the crystal oscillator configuration in Figure 6, Osc Out 2 must be left open circuited.
Reset (Pin 12)
Active–high reset. A high level applied to this input asynchronously resets the counter to its zero state (forcing all Q outputs low) and disables the oscillator.
SWITCHING WAVEFORMS
tf
90%
50%
10%
OSC IN
tw
tr
VCC
RESET
GND
GND
tPHL
tw
1/fmax
tPLH
Q1
VCC
50%
50%
Q
tPHL
90%
50%
10%
trec
VCC
tTLH
50%
CLOCK
tTHL
GND
Figure 2.
Figure 1.
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
VCC
QN 50%
GND
tPHL
tPLH
QN + 1
50%
* Includes all probe and jig capacitance
Figure 3.
MOTOROLA
CL*
Figure 4. Test Circuit
4
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HC4060
EXPANDED LOGIC DIAGRAM
Q4
Q5
7
OSC OUT 1
OSC IN
RESET
RESET
Q13
2
Q14
3
C
Q
C
Q
C
Q
C
Q
C
Q
C
C
Q
C
Q
C
Q
C
Q
C
Q
C
R
R
OSC OUT 2
Q12
1
5
R
R
R
Q
R
9
Q6 = PIN 4
Q7 = PIN 6
Q8 = PIN 14
Q9 = PIN 13
10
Q10 = PIN 15
VCC = PIN 16
GND = PIN 8
11
12
For 2.0 V ≤ VCC ≤ 6.0 V
10 Rtc > RS > 2 Rtc
400 Hz ≤ f ≤ 400 kHz
12
OSC IN 11
OSC OUT 1 10
OSC OUT 2 9
f≈
1
(f in Hz, Rtc in ohms, Ctc in farads)
3 RtcCtc
Rtc
RS
The formula may vary for other frequencies.
Ctc
Figure 5. Oscillator Circuit Using RC Configuration
High–Speed CMOS Logic Data
DL129 — Rev 6
5
MOTOROLA
MC54/74HC4060
RESET
12
11 OSC IN
10 OSC OUT 1
9 OSC OUT 2
Rf
R1
C1
C2
Figure 6. Pierce Crystal Oscillator Circuit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Table 1. Crystal Oscillator Amplifier Specifications
TA = 25_C (Input = Pin 11, Output = Pin 10)
Type
Input Resistance, Rin
Output Impedance, Zout (4.5 V supply)
Input Capacitance, Cin
Output Capacitance, Cout
Series Capacitance, Ca
3 Vdc supply
Open loop voltage
4 Vdc supply
gain with output at
5 Vdc supply
full swing, α
6 Vdc supply
Positive Reactance (Pierce)
60 MΩ minimum
200 Ω (see text)
5 pF typical
7 pF typical
5 pF typical
5.0 expected minimum
4.0 expected minimum
3.3 expected minimum
3.1 expected minimum
PIERCE CRYSTAL OSCILLATOR DESIGN
LS
RS
1
2
1
CS
2
Re
1
Xe
2
CO
Values are supplied by crystal manufacturer (parallel resonant crystal)
Figure 7. Equivalent Crystal Networks
Rs
–jXC2
Ca
Rload
–jXCo
jXLs
–jXCs
R
Zload
–jXC
Cin
Xload
NOTE: C = C1 + Cin and R = R1 + Rout. Co is considered as part of the
load. Ca and Rf typically have minimal effect below 2 MHz.
Values are listed in Table 1.
Figure 8. Series Equivalent Crystal Load
MOTOROLA
Cout
Figure 9. Parasitic Capacitances
of the Amplifier
6
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HC4060
DESIGN PROCEDURES
The following procedure applies for oscillators operating below 2 MHz where Z is a resistor R1. Above 2 MHz, additional impedance elements should be considered: Cout and Ca of the amp, feedback resistor Rf, and amplifier phase shift error from 180_.
Step 1: Calculate the equivalent series circuit of the crystal at the frequency of oscillation.
– jXCo (Rs + jXLs – jXCs
Ze =
= Re + jXe
– jXCo + Rs + jXLs – jXCs
Reactance jXe should be positive, indicating that the crystal is operating as an inductive reactance at the oscillation frequency
The maximum Rs for the crystal should be used in the equation.
Step 2: Determine β, the attenuation, of the feedback network. For a closed–loop gain of 2, Aνβ = 2,β = 2/Aν where Aν is
the gain of the HC4060 amplifier.
Step 3: Determine the manufacturer’s loading capacitance. For example: A manufacturer may specify an external load capacitance of 32 pF at the required frequency.
Step 4: Determine the required Q of the system, and calculate Rload. For example, a manufacturer specifies a crystal Q
of 100,000. In–circuit Q is arbitrarily set at 20% below crystal Q or 80,000. Then Rload = (2πfoLs/Q) – Rs where Ls and Rs are
crystal parameters.
Step 5: Simultaneously solve, using a computer,
β=
XC • XC2
(with feedback phase shift = 180_)
R • Re + XC2 (Xe – XC)
Xe = XC2 + XC +
Rload =
(1)
ReXC2 = X
Cload (where the loading capacitor is an external load, not including Co)
R
RXCoXC2[(XC + XC2) (XC + XCo) – XC(XC + XCo + XC2)]
X2C2(XC + XCo)2 + R2(XC + XCo + XC2)2
(2)
(3)
Here R = Rout + R1. Rout is amp output resistance, R1 is Z. The C corresponding to XC is given by C = C1 + Cin.
Alternately, pick a value for R1 (i.e., let R1 = Rs). Solve Equations 1 and 2 for C1 and C2. Use Equation 3 and the fact that
Q = 2πfoLs/(Rs + Rload) to find in–circuit Q. If Q is not satisfactory pick another value for R1 and repeat the procedure.
CHOOSING R1
the first overtone. Rf must be large enough so as to not affect
the phase of the feedback network in an appreciable manner.
Power is dissipated in the effective series resistance of the
crystal. The drive level specified by the crystal manufacturer
is the maximum stress that a crystal can withstand without
damage or excessive shift in frequency R1 limits the drive
level.
To verify that the maximum dc supply voltage does not
overdrive the crystal, monitor the output frequency as a function of voltage at Osc Out 2 (Pin 9). The frequency should
increase very slightly as the dc supply voltage is increased.
An overdriven crystal will decrease in frequency or become
unstable with an increase in supply voltage. The operating
supply voltage must be reduced or R1 must be increased in
value it the overdriven condition exists. The user should note
that the oscillator start–up time is proportional to the value of
R1.
ACKNOWLEDGEMENTS AND RECOMMENDED
REFERENCES
The following publications were used in preparing this data
sheet and are hereby acknowledged and recommended for
reading:
Technical Note TN–24, Statek Corp.
Technical Note TN–7, Statek Corp.
D. Babin, “Designing Crystal Oscillators”, Machine Design,
March 7, 1985.
D. Babin, “Guidelines for Crystal Oscillator Design”,
Machine Design, April 25, 1985.
ALSO RECOMMENDED FOR READING:
E. Hafner, “The Piezoelectric Crystal Unit – Definitions and
Method of Measurement”, Proc. IEEE, Vol. 57, No. 2, Feb.
1969.
D. Kemper, L. Rosine, “Quartz Crystals for Frequency
Control”, Electro–Technology, June, 1969.
P. J. Ottowitz, “A Guide to Crystal Selection”, Electronic
Design, May, 1966.
SELECTING Rf
The feedback resistor, Rf, typically ranges up to 20 MΩ. Rf
determines the gain and bandwidth of the amplifier. Proper
bandwidth insures oscillation at the correct frequency plus
roll–off to minimize gain at undesirable frequencies, such as
High–Speed CMOS Logic Data
DL129 — Rev 6
7
MOTOROLA
MC54/74HC4060
TIMING DIAGRAM
1
2
4
8
16
32
64
128
256
512
1024
2048
4096
8192
16,384
OSC IN
RESET
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
MOTOROLA
8
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HC4060
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
ISSUE V
–A
–
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIM F MAY NARROW TO 0.76 (0.030) WHERE
THE LEAD ENTERS THE CERAMIC BODY.
–B
–
L
C
DIM
A
B
C
D
E
F
G
J
K
L
M
N
–T
N
SEATING
–
PLANE
K
E
M
F
J 16 PL
0.25 (0.010)
G
D 16 PL
0.25 (0.010)
T A
M
M
T B
S
S
INCHES
MIN
MAX
0.750 0.785
0.240 0.295
—
0.200
0.015 0.020
0.050 BSC
0.055 0.065
0.100 BSC
0.008 0.015
0.125 0.170
0.300 BSC
15°
0°
0.020 0.040
MILLIMETERS
MIN
MAX
19.05 19.93
6.10
7.49
—
5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
15°
0°
1.01
0.51
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A
–
16
9
1
8
B
F
C
L
S
–T
–
SEATING
PLANE
K
H
D 16 PL
0.25 (0.010)
High–Speed CMOS Logic Data
DL129 — Rev 6
M
M
J
G
T A
M
9
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MILLIMETERS
MIN
MAX
MIN
MAX
0.740 0.770 18.80 19.55
6.35
0.250 0.270
6.85
3.69
0.145 0.175
4.44
0.39
0.015 0.021
0.53
1.02
0.040 0.070
1.77
0.100 BSC
2.54 BSC
0.050 BSC
1.27 BSC
0.21
0.008 0.015
0.38
2.80
0.110 0.130
3.30
7.50
0.295 0.305
7.74
0°
0°
10°
10°
0.020 0.040
0.51
1.01
MOTOROLA
MC54/74HC4060
OUTLINE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F–01
ISSUE O
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
ÉÉ
ÇÇ
ÇÇ
ÉÉ
ÇÇ
ÉÉ
ÇÇ
ÉÉ
S
S
K
K1
2X
L/2
16
9
J1
B
–U–
L
SECTION N–N
J
PIN 1
IDENT.
8
1
N
0.25 (0.010)
0.15 (0.006) T U
S
A
–V–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE –W–.
M
N
F
DETAIL E
–W–
C
0.10 (0.004)
–T– SEATING
PLANE
H
D
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
–––
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
–––
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.007
0.011
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
G
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*MC54/74HC4060/D*
10
MC54/74HC4060/D
High–Speed CMOS Logic Data
DL129 — Rev 6