19-1785; Rev 1; 3/01 Low-Cost, Low-Power 6-Bit DACs with 2-Wire Serial Interface in SOT23 Package The MAX5360/MAX5361/MAX5362 also include an output buffer, a low-power shutdown mode, and a poweron reset that ensures the DAC outputs are at zero when power is initially applied. In shutdown mode, the supply current is reduced to less than 1µA and the output is pulled down with a 10kΩ resistor to GND. The MAX5360/MAX5361/MAX5362 are available in miniature 5-pin SOT23 packages. Applications Automatic Tuning (VCO) Power Amplifier Bias Control Programmable Threshold Levels Automatic Gain Control Automatic Offset Adjustment I2C is a trademark of Philips Corp. Typical Operating Circuit Features ♦ 6-Bit Accuracy in a Tiny 5-Pin SOT23 Package ♦ Wide +2.7V to +5.5V Supply Range (MAX5362) ♦ 1µA Shutdown Mode ♦ Buffered Output Drives Resistive Loads ♦ Low Glitch Power-On-Reset to Zero DAC Output ♦ Fast I2C-Compatible Serial Interface ♦ ≤-5% Full-Scale Error (MAX5362) ♦ ≤1LSB (max) INL/DNL ♦ Low 230µA max Supply Current Ordering Information PART MAX5360_EUK-T* MAX5361_EUK-T* MAX5362_EUK-T* TEMP. RANGE -40°C to +85°C -40°C to +85°C -40°C to +85°C PIN-PACKAGE 5 SOT23-5 5 SOT23-5 5 SOT23-5 *See Selector Guide for address options. Selector Guide PART ADDRESS REFERENCE MAX5360LEUK MAX5360MEUK MAX5360NEUK MAX5360PEUK MAX5361LEUK MAX5361MEUK MAX5361NEUK MAX5361PEUK MAX5362LEUK MAX5362MEUK MAX5362NEUK MAX5362PEUK 0x60 0x62 0x64 0x66 0x60 0x62 0x64 0x66 0x60 0x62 0x64 0x66 +2.0V +2.0V +2.0V +2.0V +4.0V +4.0V +4.0V +4.0V 0.9 ✕ VDD 0.9 ✕ VDD 0.9 ✕ VDD 0.9 ✕ VDD TOP MARK ADMM ADMY ADNE ADMO ADMU ADNA ADNG ADMQ ADMW ADNC ADNI ADMS Pin Configuration +2.7V TO +5.5V VDD TOP VIEW µC OUT 1 5 SCL 4 SDA VDD PX.0/SDA SDA PX.1/SCL SCL GND MAX5362 OUT GND 2 MAX5360 MAX5361 MAX5362 GND VDD 3 SOT23-5 ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX5360/MAX5361/MAX5362 General Description The MAX5360/MAX5361/MAX5362 are low-cost, 6-bit digital-to-analog converters (DACs) in miniature 5-pin SOT23 packages with a simple 2-wire serial interface that allows communication with multiple devices. The MAX5360 has an internal +2V reference and operates from a +2.7V to +3.6V supply. The MAX5361 has an internal +4V reference and operates from a +4.5V to +5.5V supply. The MAX5362 operates over the full +2.7V to +5.5V supply range and has an internal reference equal to 0.9 ✕ VDD. The fast-mode I2C™-compatible serial interface allows communication at data rates up to 400kbps, minimizing board space and reducing interconnect complexity in many applications. Each device is available with one of four factory-preset addresses (see Selector Guide). MAX5360/MAX5361/MAX5362 Low-Cost, Low-Power 6-Bit DACs with 2-Wire Serial Interface in SOT23 Package ABSOLUTE MAXIMUM RATINGS VDD to GND ..............................................................-0.3V to +6V OUT to GND ...............................................-0.3V to (VDD + 0.3V) SCL, SDA to GND.....................................................-0.3V to +6V Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70°C) 5-Pin SOT23 (derate 7.1mW/°C above +70°C)...........571mW Operating Temperature Range MAX536__EUK-T ............................................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Maximum Junction Temperature .....................................+150°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = 2.7V to 3.6V (MAX5360); VDD = 4.5V to 5.5V (MAX5361); VDD = 2.7V to 5.5V (MAX5362); RL =10kΩ, CL = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC ACCURACY Resolution 6 Bits Integral Linearity Error INL (Note 1) ±1 LSB Differential Linearity Error DNL Guaranteed monotonic (Note 2) ±1 LSB Offset Error VOS Guaranteed monotonic (Note 2) ±2 mV Offset Error Supply Rejection MAX5362 (Notes 2, 3) 3 MAX5362 1 (Note 2) Full-Scale Error Code = 63 Full-Scale Error Supply Rejection Code = 63, MAX5360/MAX5361 (Note 4) Code = 63 dB MAX5360/MAX5361 Offset Error Temperature Coefficient Full-Scale Error Temperature Coefficient ±1 60 ppm/°C MAX5360/MAX5361 10 MAX5362 5 % of Ideal FS 60 dB MAX5360/MAX5361 ±40 MAX5362 ±10 ppm/°C DAC OUTPUT Internal Reference (Note 5) REF MAX5360 1.8 2 2.2 MAX5361 3.6 4 4.4 0.85 ✕ 0.9 ✕ VDD VDD 0.95 ✕ VDD MAX5362 Output Load Regulation Output Resistance DYNAMIC PERFORMANCE Voltage Output Slew Rate Output Settling Time Digital Feedthrough Digital-Analog Glitch Impulse Wake-Up Time 2 Code = 63, 0 to 100µA Code = 0, 0 to -100µA VOUT = 0 to VDD, power-down mode 0.5 0.5 10 Positive and negative To 1/2LSB, 50kΩ and 50pF load (Note 6) Code = 0, all digital inputs from 0 to VDD Code 31 to 32 From software shutdown 0.4 20 2 40 50 _______________________________________________________________________________________ V LSB kΩ V/µs µs nVs nVs µs Low-Cost, Low-Power 6-Bit DACs with 2-Wire Serial Interface in SOT23 Package (VDD = 2.7V to 3.6V (MAX5360); VDD = 4.5V to 5.5V (MAX5361); VDD = 2.7V to 5.5V (MAX5362); RL =10kΩ, CL = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER REQUIREMENTS Supply Voltage VDD Supply Current IDD MAX5360 2.7 3.6 MAX5361 4.5 5.5 MAX5362 2.7 5.5 No load, all digital inputs at 0 or VDD, code = 63 150 230 Shutdown mode 1 V µA DIGITAL INPUTS (SCL, SDA) Input Low Voltage 0.3 ✕ VDD VIL Input High Voltage VIH Input Hysteresis Vhys Input Capacitance CIN Input Leakage Current Pulse Width of Spike Suppressed 0.7 ✕ VDD V 0.05 ✕ VDD (Note 7) V 10 Ii tSP V 0 pF ±10 µA 50 ns DIGITAL OUTPUT (SDA) (open drain) Output Low Voltage Output Fall Time VOL tof ISINK = 3mA 0 0.4 ISINK = 6mA 0 0.6 VIH min to VIL max, bus capacitance 10pF to 400pF ISINK = 3mA 250 ISINK = 6mA 250 V ns TIMING CHARACTERISTICS (VDD = 2.7V to 3.6V (MAX5360); VDD = 4.5V to 5.5V (MAX5361); VDD = 2.7V to 5.5V (MAX5362); RL =10kΩ, CL = 50pF, TA = TMAX to TMIN, Figure 3, unless otherwise noted. Typical values are TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 400 kHz SCL Clock Frequency fSCL 0 Bus-Free Time Between a STOP and a START Condition tBUF 1.3 µs tHD, STA 0.6 µs Low Period of the SCL Clock tLOW 1.3 µs High Period of the SCL Clock tHIGH 0.6 µs Hold Time (Repeated) START Condition _______________________________________________________________________________________ 3 MAX5360/MAX5361/MAX5362 ELECTRICAL CHARACTERISTICS (continued) TIMING CHARACTERISTICS (continued) (VDD = 2.7V to 3.6V (MAX5360); VDD = 4.5V to 5.5V (MAX5361); VDD = 2.7V to 5.5V (MAX5362); RL =10kΩ, CL = 50pF, TA = TMAX to TMIN, Figure 3, unless otherwise noted. Typical values are TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN Setup Time for a Repeated START Condition tSU, STA Data Hold Time tHD, DAT 0 Data Setup Time tSU, DAT 100 TYP MAX UNITS 0.6 µs 0.9 µs ns Rise Time of Both SDA and SCL Signals tr 300 ns Fall Time of Both SDA and SCL Signals tf 300 ns Setup Time for STOP Condition Capacitive Load for Each Bus Line Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: tSU, STO 0.6 µs Cb 400 pF Guaranteed from code 1 to code 63. The offset value extrapolated from the range over which the INL is guaranteed. MAX5362, tested at VDD = 5V ±10%. MAX5360, tested at VDD = 3V ±10%; MAX5361, tested at VDD = 5V ±10%. Actual output voltage at full scale is 63/64 ✕ VREF. Output settling time is measured by taking the code from code 1 to code 63, and from code 63 to code 1. Guaranteed by design. Typical Operating Characteristics (VDD = 3V (MAX5360), VDD = 5V (MAX5361/MAX5362), TA = +25°C, unless otherwise noted.) 25 50 CODE 75 MAX5360/1/2-03 MAX5360/1/2-02 INL (LSB) INL (LSB) 0 -0.025 -0.025 -0.050 -0.050 0 4 0 MAX5360/1/2-01 0.030 0.025 0.020 0.015 0.010 0.005 0 -0.005 -0.010 -0.015 -0.020 -0.025 -0.030 -0.035 -0.040 -0.045 INTEGRAL NONLINEARITY vs. TEMPERATURE INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGE INTEGRAL NONLINEARITY vs. CODE INL (LSB) MAX5360/MAX5361/MAX5362 Low-Cost, Low-Power 6-Bit DACs with 2-Wire Serial Interface in SOT23 Package 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 5.5 -40 -20 0 20 40 60 TEMPERATURE (°C) _______________________________________________________________________________________ 80 100 Low-Cost, Low-Power 6-Bit DACs with 2-Wire Serial Interface in SOT23 Package MAX5360/MAX5361/MAX5362 Typical Operating Characteristics (continued) (VDD = 3V (MAX5360), VDD = 5V (MAX5361/MAX5362), TA = +25°C, unless otherwise noted.) DIFFERENTIAL NONLINEARITY vs. SUPPLY VOLTAGE -0.005 -0.005 -0.005 -0.010 DNL (LSB) DNL (LSB) 0 0 MAX5360/1/2-05 0.005 DNL (LSB) 0 MAX5360/1/2-04 0.010 DIFFERENTIAL NONLINEARITY vs. TEMPERATURE MAX5360/1/2-06 DIFFERENTIAL NONLINEARITY vs. CODE -0.015 -0.010 -0.015 -0.010 -0.020 -0.015 -0.020 -0.020 -0.025 25 50 -0.025 2.5 75 3.0 3.5 4.0 4.5 5.0 5.5 -40 -20 0 SUPPLY VOLTAGE (V) CODE OFFSET ERROR vs. SUPPLY VOLTAGE TOTAL UNADJUSTED ERROR vs. CODE 60 80 100 0 MAX5360/1/2-08 0.10 40 OFFSET ERROR vs. TEMPERATURE 0 MAX5360/1/2-07 0.15 20 TEMPERATURE (°C) MAX5360/1/2-09 0 0 -0.05 VOS VOS (mV) TUE (LSB) 0.05 -0.25 -0.25 -0.10 -0.15 -0.50 0 25 50 -0.50 2.5 75 3.0 4.0 4.5 5.0 5.5 -40 -20 0 SUPPLY VOLTAGE (V) CODE MAX5360/1/2-10 MAX5361 1.2 0.75 0.8 0.50 20 40 60 80 100 TEMPERATURE (°C) SUPPLY CURRENT vs. SUPPLY VOLTAGE FULL-SCALE ERROR vs. TEMPERATURE FULL-SCALE ERROR vs. TEMPERATURE 0.75 3.5 MAX5360/1/2-11 200 1.2 0 0 -0.25 -0.4 -0.50 -0.8 MAX5360 MAX5361 0.25 0.4 0 0 MAX5362 -0.25 -0.4 -0.50 -0.8 -1.2 -0.75 3.0 MAX5360 140 120 MAX5362 100 80 60 40 20 NO LOAD 2.5 MAX5361 160 SUPPLY CURRENT (µA) 0.4 MAX5362 0.8 FULL-SCALE ERROR (%) 0.25 FULL-SCALE ERROR (LSB) FULL-SCALE ERROR (LSB) MAX5360 FULL-SCALE ERROR (%) 180 0.50 MAX5360/1/2-12 -0.20 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 5.5 -1.2 -0.75 -40 -20 0 20 40 60 TEMPERATURE (°C) 80 100 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 5 Typical Operating Characteristics (continued) (VDD = 3V (MAX5360), VDD = 5V (MAX5361/MAX5362), TA = +25°C, unless otherwise noted.) 150 145 MAX5362 140 MAX5360 135 08 150 145 140 MAX5360 VDD = 5V 135 130 MAX5362 VDD = 5V 1.0 MAX5360 VDD = 3V 0 20 40 60 80 100 8 16 24 TEMPERATURE (°C) 32 40 48 56 2.5 64 0.6 VDD = 5V 0.4 3.5 OUT 50mV/div 3.0 2.5 B 2.0 C 0.2 D 0.2 E 0.1 0 0 -20 0 20 40 60 TEMPERATURE (°C) 80 100 0 1 2 3 4 5 6 7 8 9 VDD 2V/div 10 LOAD CURRENT (mA) A: MAX5361/MAX5362, VDD = 4.5V, FULL-SCALE OR SOURCING B: MAX5360, FULL-SCALE, VDD = 2.7V SINKING, VDD = 5V SOURCING C: MAX5360, FULL-SCALE, VDD = 2.7V, SOURCING D: ZERO CODE, VDD = 2.7V, SINKING E: ZERO CODE, VDD = 5.5V SINKING 6 4.5 5.0 5.5 MAX5360/1/2-18 A 4.0 1.5 VDD = 3V 4.0 MAX5360/1/2-17 4.5 VOUT FULL SCALE (V) 0.8 3.5 OUTPUT VOLTAGE ON POWER-UP OUTPUT LOAD REGULATION MAX5360/1/2-16 1.0 3.0 SUPPLY VOLTAGE (V) CODE SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE -40 0.4 0 0 VOUT ZERO CODE (V) -20 0.6 0.2 130 -40 MAX5360/1/2-15 155 SUPPLY CURRENT (µA) MAX5361 MAX5361 VDD = 5V SUPPLY CURRENT (µA) 155 SUPPLY CURRENT (µA) 160 MAX5360/1/2-13 160 SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE SUPPLY CURRENT vs. CODE MAX5360/1/2-14 SUPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT (µA) MAX5360/MAX5361/MAX5362 Low-Cost, Low-Power 6-Bit DACs with 2-Wire Serial Interface in SOT23 Package _______________________________________________________________________________________ 4µs/div Low-Cost, Low-Power 6-Bit DACs with 2-Wire Serial Interface in SOT23 Package MAX5360 OUTPUT VOLTAGE ENTERING SHUTDOWN MAX5360/1/2-21 MAX5360 OUTPUT SETTLING FROM 1/4 FS TO 3/4 FS MAX5360/1/2-19 MAX5360/1/2-20 MAX5360 OUTPUT VOLTAGE EXITING SHUTDOWN OUT 500mV/div OUT 500mV/div OUT 0.5V/div SDA 3V/div SDA 3V/div SDA 3V/div 1µs/div 1µs/div MAX5360 OUTPUT SETTLING FROM 3/4 FS TO 1/4 FS MAX5360 OUTPUT SETTLING 1/4LSB STEP-UP MAX5360 OUTPUT SETTLING 1/4LSB STEP-DOWN MAX5360/1/2-24 MAX5360/1/2-22 MAX5360/1/2-23 10µs/div OUT 0.5V/div OUT 20mV/div AC-COUPLED OUT 20mV/div AC-COUPLED SDA 3V/div SDA 3V/div SDA 3V/div 1µs/div 2µs/div 0 x 7F TO 0 x 80 01111111 TO 10000000 2µs/div 0 x 80 TO 0 x 7F 10000000 TO 01111111 Pin Description PIN NAME FUNCTION 1 OUT DAC Voltage Output 2 GND Ground 3 VDD Power-Supply Input 4 SDA Serial Data Input 5 SCL Serial Clock Input _______________________________________________________________________________________ 7 MAX5360/MAX5361/MAX5362 Typical Operating Characteristics (continued) (VDD = 3V (MAX5360), VDD = 5V (MAX5361/MAX5362), TA = +25°C, unless otherwise noted.) MAX5360/MAX5361/MAX5362 Low-Cost, Low-Power 6-Bit DACs with 2-Wire Serial Interface in SOT23 Package VDD VREF CURRENTSTEERING DAC REF OUT SW1 255 SDA SCL DATA LATCH 6+2 CONTROL LOGIC SERIAL INPUT REGISTER MAX5360 MAX5361 MAX5362 SW2 SW255 10k OUT GND Figure 1. Functional Diagram Figure 2. Current-Steering Topology Table 1. Unipolar Code Current OUTPUT VOLTAGE DAC CODE 6 BITS + 2 SUBBITS MAX5360 MAX5361 MAX5362 111111 (00) 2V ✕ (63/64) 4V ✕ (63/64) 0.9 ✕ VDD ✕ (63/64) 100000 (00) 1V 2V 0.9 ✕ VDD / 2 000001 (00) 31mV 62mV 0.9 ✕ VDD / 64 000000 (00) 0 0 0 Detailed Description The MAX5360/MAX5361/MAX5362 voltage-output, 6-bit DACs offer full 6-bit performance with less than 1LSB integral nonlinearity (INL) error and less than 1LSB differential nonlinearity (DNL) error ensuring monotonic performance. The devices use a simple two-wire, fastmode I2C-compatible serial interface that operates up to 400kHz. The MAX5360/MAX5361/MAX5362 include an internal reference, an output buffer, and low-current shutdown mode, making them ideal for low-power, highly integrated applications. Figure 1 shows the devices’ functional diagram. Analog Section The MAX5360/MAX5361/MAX5362 employ a currentsteering DAC topology as shown in Figure 2. At the core of the DAC is a reference voltage-to-current converter (V/I) that generates a reference current. This current is mirrored to 255 equally weighted current sources. DAC switches control the outputs of these current mirrors, so only the desired fraction of the total current-mirror currents is steered to the DAC output. The 8 current is then converted to a voltage across a resistor, and this voltage is buffered by the output buffer amplifier. Output Voltage Table 1 shows the relationship between the DAC code and the analog output voltage. The 6-bit DAC code is binary unipolar with 1LSB = (VREF / 64). The MAX5360/ MAX5361 have a full-scale output voltage of (+2V 1LSB) and (+4V - 1LSB), respectively, set by the internal references. The MAX5362 has a full-scale output voltage of (0.9 ✕ VDD - 1LSB). Each device accepts 8-bit DAC codes, but the accuracy is guaranteed only for 6 bits. Output Buffer The DAC voltage output is an internally buffered unitygain follower that typically slews at ±0.4V/µs. The output can swing from 0 to full scale. With a 1/4 FS to 3/4 FS output transition, the amplifier outputs typically settle to 1/2LSB in less than 5µs when loaded with 10kΩ in parallel with 50pF. The buffer amplifiers are stable with any combination of resistive loads >10kΩ and capacitive loads <50pF. _______________________________________________________________________________________ Low-Cost, Low-Power 6-Bit DACs with 2-Wire Serial Interface in SOT23 Package tSU, DAT tBUF tSU, STA tHD, STA tLOW tSU, STO tHD, DAT SCL tHIGH tHD, STA tR tF START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION Figure 3. Two-Wire Serial Interface Timing Diagram VDD µC SDA SCL SCL R S* VDD MAX5360M 2V REFERENCE SDA OUT Shutdown Mode The MAX5360/MAX5361/MAX5362 include a softwarecontrolled shutdown mode that reduces the supply current to <1µA. All internal circuitry is disabled and an internal 10kΩ resistor is placed from OUT to GND to ensure 0V at OUT while in shutdown. The device enters shutdown in less than 5µs and exits shutdown in less than 50µs. OFFSET ADJUSTMENT Digital Section SCL VDD MAX5361N 4V REFERENCE SDA OUT SCL THRESHOLD ADJUSTMENT VDD MAX5362P VDD REFERENCE SDA OUT GAIN ADJUSTMENT RS* IS OPTIONAL. Figure 4. Typical Application Circuit Power-On Reset The MAX5360/MAX5361/MAX5362 have a power-on reset circuit to set the DAC’s output to 0 when VDD is first applied or when VDD dips below 1.7V. This ensures that unwanted DAC output voltages will not occur immediately following a system startup, such as after a loss of power. The output glitch on startup is typically <50mV. Serial interface The MAX5360/MAX5361/MAX5362 use a simple twowire serial interface requiring only two I/O lines (twowire bus) of a standard microprocessor (µP) port. Figure 3 shows the timing diagram for signals on the 2wire bus. The two bus lines (SDA and SCL) must be high when the bus is not in use. The MAX5360/MAX5361/ MAX5362 are receive-only devices (slaves) and must be controlled by a bus master device. Figure 4 shows a typical application where multiple devices can be connected to the bus provided they have different address settings. External pullup resistors are not necessary on these lines (when driven by push-pull drivers), though the MAX5360/MAX5361/MAX5362 can be used in applications where pullup resistors are required (such as in I2C systems) to maintain compatibility with existing circuitry. The serial interface operates at SCL rates up to 400kHz. The SDA state is allowed to change only while SCL is low, with the exception of START and STOP conditions as shown in Figure 5. Each transmission consists of a START condition sent by the bus master device, followed by the MAX5360/MAX5361/ MAX5362’s preset slave address, a power-mode bit, _______________________________________________________________________________________ 9 MAX5360/MAX5361/MAX5362 SDA MAX5360/MAX5361/MAX5362 Low-Cost, Low-Power 6-Bit DACs with 2-Wire Serial Interface in SOT23 Package Slave Address The MAX5360/MAX5361/MAX5362 are available with one of four preset slave addresses. Each address option is identified by the suffix L, M, N, or P added to the part number. The address is defined as the 7 most significant bits (MSBs) sent by the master after a START condition. The address options are 0x60, 0x62, 0x64, and 0x66 (left justified with LSB set to 0). The 8th bit, typically used to define a write or read protocol, sets the device’s power mode (SHDN); the device is powered down when SHDN is set to 1. During a device search routine, the MAX5360/MAX5361/MAX5362 acknowledge both options (SHDN = 0 or SHDN = 1) but does not change its power state if a stop condition (or restart) is issued immediately. The second byte (DAC data) must be sent/received for the device to update both power mode and DAC output. SDA SCL START CONDITION STOP CONDITION Figure 5. Start and Stop Conditions DAC Data The 6-bit DAC data is decoded as straight binary MSB first with 1LSB = (VREF / 64) and converted into the corresponding analog voltage as shown in Table 1. Two subbits complete the data byte; these 2 bits should be set to zero since they are not tested to guaranteedmonotonic performance. the DAC data (6 bits + 2 subbits), and finally, a STOP condition (Figure 6). The bus is then free for another transmission. SDA’s state is sampled, and therefore must remain stable while SCL is high. Data is transmitted in 8-bit bytes. Nine clock cycles are required to transfer each byte to the MAX5360/MAX5361/MAX5362. Release SDA during the 9th clock cycle as the selected device acknowledges the receipt of the byte, by pulling SDA low during this time. A series resistor on the SDA line may be needed if the master’s output is forced high while the selected device acknowledges (Figure 4). After receiving the data byte, the MAX5360/MAX5361/ MAX5362 acknowledge its receipt and expect a STOP condition, at which point the DAC output is updated. The devices update the output and the power mode only if the second byte is clocked in (SHDN = 0) or out (SHDN = 1) of the device. When SHDN = 1, the master will read all ones when clocking out a data byte. The MAX5360/MAX5361/MAX5362 do not drive SDA except for the acknowledge bit. SLAVE ADDRESS BYTE 0 SDA 1 1 0 0 DAC CODE X MSB 1 SCL X SHDN ACK LSB 2 3 4 5 6 7 D6 D4 D3 D2 D1 D0 S1 MSB 8 9 10 11 12 13 14 15 16 START CONDITION Figure 6. Complete Serial Transmission 10 S0 ACK LSB ______________________________________________________________________________________ 17 18 STOP CONDITION Low-Cost, Low-Power 6-Bit DACs with 2-Wire Serial Interface in SOT23 Package µC SDA SCL SCL VDD MAX5360L 2V REFERENCE SDA OUT SCL Applications Information Digital Inputs and Interface Logic OFFSET ADJUSTMENT VDD MAX5361M 4V REFERENCE OUT SDA THRESHOLD ADJUSTMENT The serial 2-wire interface has logic levels defined as VOL = 0.3 ✕ VDD and VOH = 0.7 ✕ VDD. All of the inputs include Schmitt-trigger buffers to accept slow-transition interfaces. This means that optocouplers can interface directly to the MAX5360/MAX5361/MAX5362 without additional external logic. The digital inputs are compatible with CMOS logic levels and must not be driven with voltages higher than VDD. Power-Supply Bypassing and Layout SCL VDD MAX5362P VDD REFERENCE OUT SDA GAIN ADJUSTMENT Figure 7. I2C Typical Application I 2C Compatibility The MAX5360/MAX5361/MAX5362 are compatible with existing I2C systems. SCL and SDA are high-impedance inputs; SDA has an open drain that pulls the data line low during the 9th clock pulse. Figure 7 shows a Careful PC board layout is important for best system performance. To reduce crosstalk and noise injection, keep analog and digital signals separate. Ensure that the ground return from GND to the supply ground is short and low impedance; a ground plane is recommended. Bypass VDD with a 0.1µF to ground as close as possible to the device. If the supply is excessively noisy, connect a 10Ω resistor in series with the supply and VDD, and add additional capacitance Chip Information TRANSISTOR COUNT: 2910 PROCESS: BiCMOS ______________________________________________________________________________________ 11 MAX5360/MAX5361/MAX5362 typical I2C application. The communication protocol supports the standard I2C 8-bit communications. The general call address is ignored, and CBUS formats are not supported. The MAX5360/MAX5361/MAX5362 address is compatible with the 7-bit I2C addressing protocol only. No 10-bit formats are supported. RESTART protocol is supported, but an immediate STOP condition is necessary to update the DAC. VDD Low-Cost, Low-Power 6-Bit DACs with 2-Wire Serial Interface in SOT23 Package SOT5L.EPS MAX5360/MAX5361/MAX5362 Package Information Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.