19-2340; Rev 0; 1/02 12-Bit Low-Power, 2-Wire, Serial Voltage-Output DAC Applications Digital Gain and Offset Adjustments Features ♦ Ultra-Low Supply Current 100µA at VDD = 3.6V 130µA at VDD = 5.5V ♦ 300nA Low-Power Power-Down Mode ♦ Single 2.7V to 5.5V Supply Voltage ♦ Fast 400kHz I2C-Compatible 2-Wire Serial Interface ♦ Schmitt-Trigger Inputs for Direct Interfacing to Optocouplers ♦ Rail-to-Rail Output Buffer Amplifier ♦ Three Software-Selectable Power-Down Output Impedances 100kΩ, 1kΩ, and High Impedance ♦ Read-Back Mode for Bus and Data Checking ♦ Power-On Reset to Zero ♦ Miniature 6-Pin SOT23 Package Ordering Information PART TEMP RANGE PINPACKAGE TOP MARK MAX5812LEUT -40°C to +85°C 6 SOT23 AAYT Programmable Voltage and Current Sources MAX5812MEUT -40°C to +85°C 6 SOT23 AAYV Programmable Attenuation MAX5812NEUT -40°C to +85°C 6 SOT23 AAYX VCO/Varactor Diode Control MAX5812PEUT -40°C to +85°C 6 SOT23 AAYZ Selector Guide appears at end of data sheet. Functional Diagram appears at end of data sheet. Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. I2C is a trademark of Philips Corporation. Low-Cost Instrumentation Battery-Operated Equipment Pin Configuration Typical Operating Circuit VDD µC SDA TOP VIEW VDD SCL RP RP RS SCL RS SDA VDD MAX5812 OUT VDD 1 GND 2 MAX5812 SDA 3 RS SCL RS SDA 6 OUT 5 ADD 4 SCL VDD MAX5812 OUT SOT23 ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX5812 General Description The MAX5812 is a single, 12-bit voltage-output, digital-toanalog converter (DAC) with an I2C™-compatible 2-wire interface that operates at clock rates up to 400kHz. The device operates from a single 2.7V to 5.5V supply and draws only 100µA at VDD = 3.6V. A low-power powerdown mode decreases current consumption to less than 1µA. The MAX5812 features three software-selectable power-down output impedances: 100kΩ, 1kΩ, and high impedance. Other features include an internal precision Rail-to-Rail® output buffer and a power-on reset circuit that powers up the DAC in the 100kΩ power-down mode. The MAX5812 features a double-buffered I2C-compatible serial interface that allows multiple devices to share a single bus. All logic inputs are CMOS-logic compatible and buffered with Schmitt triggers, allowing direct interfacing to optocoupled and transformer-isolated interfaces. The MAX5812 minimizes digital noise feedthrough by disconnecting the clock (SCL) signal from the rest of the device when an address mismatch is detected. The MAX5812 is specified over the extended temperature range of -40°C to +85°C and is available in a space-saving 6-pin SOT23 package. Refer to the MAX5811 for the 10-bit version. MAX5812 12-Bit Low-Power, 2-Wire, Serial Voltage-Output DAC ABSOLUTE MAXIMUM RATINGS VDD, SCL, SDA to GND ............................................-0.3V to +6V OUT, ADD to GND ........................................-0.3V to VDD + 0.3V Maximum Current Into Any Pin ...........................................50mA Continuous Power Dissipation (TA = +70°C) 6-Pin SOT23 (derate 9.1mW above +70°C).................727mW Operating Temperature Range ...........................-40°C to +85°C Maximum Junction Temperature .....................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +2.7V to +5.5V, GND = 0, RL = 5kΩ, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +5V, TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ±2 ±16 LSB ±1 LSB STATIC ACCURACY (Note 2) Resolution N 12 Integral Nonlinearity INL (Note 3) Differential Nonlinearity DNL Zero-Code Error ZCE Guaranteed monotonic (Note 3) Code = 000 hex, VDD = 2.7V ±6 Zero-Code Error Tempco Gain Error Bits ±40 GE Code = FFF hex -0.8 Gain-Error Tempco mV ppm/oC 2.3 -3 %FS ppm/oC 0.26 DAC OUTPUT Output Voltage Range No load (Note 4) DC Output Impedance Code = 800 hex 1.2 VDD = 5V, VOUT = full scale (short to GND) 42.2 VDD = 3V, VOUT = full scale (short to GND) 15.1 Short-Circuit Current Wake-Up Time 0 VDD = 5V 8 VDD = 3V 8 Power-down mode = high impedance, VDD = 5.5V, VOUT = VDD or GND DAC Output Leakage Current VDD ±0.1 V Ω mA µs ±1 µA DIGITAL INPUTS (SCL, SDA) Input High Voltage VIH Input Low Voltage VIL 0.7 ✕ VDD V 0.3 ✕ VDD 0.05 ✕ VDD Input Hysteresis Input Leakage Current Digital inputs = 0 or VDD Input Capacitance V V ±0.1 ±1 6 µA pF DIGITAL OUTPUT (SDA) Output Logic Low Voltage Three-State Leakage Current VOL IL ISINK = 3mA Digital inputs = 0 or VDD Three-State Output Capacitance ±0.1 0.4 V ±1 µA 6 pF 0.5 V/µs DYNAMIC PERFORMANCE Voltage-Output Slew Rate Voltage-Output Settling Time 2 SR To 1/2LSB code 400 hex to C00 hex or C00 hex to 400 hex (Note 5) 4 _______________________________________________________________________________________ 12 µs 12-Bit Low-Power, 2-Wire, Serial Voltage-Output DAC (VDD = +2.7V to +5.5V, GND = 0, RL = 5kΩ, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +5V, TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Digital Feedthrough Code = 000 hex, digital inputs from 0 to VDD 0.2 nV-s Digital-to-Analog Glitch Impulse Major carry transition, code = 7FF hex to 800 hex and 800 hex to 7FF hex 12 nV-s POWER SUPPLIES Supply Voltage Range VDD Supply Current with No Load Power-Down Supply Current 2.7 5.5 V All digital inputs at 0 or VDD = 3.6V 100 170 All digital inputs at 0 or VDD = 5.5V 130 190 All digital inputs at 0 or VDD = 5.5V 0.3 1 µA 400 kHz µA TIMING CHARACTERISTICS (Figure 1) Serial Clock Frequency fSCL 0 Bus Free Time Between STOP and START Conditions tBUF 1.3 µs 0.6 µs START Condition Hold Time tHD, STA SCL Pulse Width Low tLOW 1.3 µs SCL Pulse Width High tHIGH 0.6 µs Repeated START Setup Time tSU, STA 0.6 µs Data Hold Time tHD, DAT 0 Data Setup Time tSU, DAT 100 0.9 µs ns SDA and SCL Receiving Rise Time tr (Note 5) 0 300 ns SDA and SCL Receiving Fall Time tf (Note 5) 0 300 ns SDA Transmitting Fall Time tf (Note 5) 20 + 0.1Cb 250 ns STOP Condition Setup Time tSU-STO 400 pF 50 ns Bus Capacitance Cb Maximum Duration of Suppressed Pulse Widths tSP Note 1: Note 2: Note 3: Note 4: Note 5: 0.6 (Note 5) 0 µs All devices are 100% production tested at TA = +25°C and are guaranteed by design for TA = TMIN to TMAX. Static specifications are tested with the output unloaded. Linearity is guaranteed from codes 115 to 3981. Offset and gain error limit the FSR. Guaranteed by design. Not production tested. _______________________________________________________________________________________ 3 MAX5812 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (VDD = +5V, RL = 5kΩ, TA = +25°C.) INTEGRAL NONLINEARITY vs. INPUT CODE 1 0 -1 -2 4 3 2 1 5 MAX5812 toc03 MAX5812 toc02 INTEGRAL NONLINEARITY vs. TEMPERATURE INTEGRAL NONLINEARITY (LSB) 2 5 INTEGRAL NONLINEARITY (LSB) 3 INTEGRAL NONLINEARITY (LSB) INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGE MAX5812 toc01 4 4 3 2 1 -3 -4 0 3072 4096 0 2.7 3.4 INPUT CODE 4.8 0.50 0.25 0 -0.25 -0.50 -0.75 -1.00 2048 MAX5812 toc05 -0.25 -0.50 -0.75 3072 4096 3.4 4.1 4.8 -0.75 5.5 -40 -15 10 2 6 4 4.8 -1.6 -1.2 -0.8 NO LOAD NO LOAD 0 0 4.1 5.5 85 -0.4 2 0 60 -2.0 MAX5812 toc08 8 NO LOAD SUPPLY VOLTAGE (V) 35 GAIN ERROR vs. SUPPLY VOLTAGE GAIN ERROR (%FSR) ZERO-CODE ERROR (mV) 4 3.4 -0.50 TEMPERATURE (°C) 10 MAX8512 toc07 6 85 -0.25 ZERO-CODE ERROR vs. TEMPERATURE ZERO-CODE ERROR vs. SUPPLY VOLTAGE 8 60 0 SUPPLY VOLTAGE (V) 10 35 -1.00 2.7 INPUT CODE 2.7 10 DIFFERENTIAL NONLINEARITY vs. TEMPERATURE -1.00 1024 -15 TEMPERATURE (°C) 0 DIFFERENTIAL NONLINEARITY (LSB) 0.75 0 -40 DIFFERENTIAL NONLINEARITY vs. SUPPLY VOLTAGE MAX5812 toc04 1.00 4 5.5 SUPPLY VOLTAGE (V) DIFFERENTIAL NONLINEARITY vs. INPUT CODE DIFFERENTIAL NONLINEARITY (LSB) 4.1 MAX5812 toc06 2048 MAX5812 toc09 1024 DIFFERENTIAL NONLINEARITY (LSB) 0 ZERO-CODE ERROR (mV) MAX5812 12-Bit Low-Power, 2-Wire, Serial Voltage-Output DAC -40 -15 10 35 TEMPERATURE (°C) 60 85 2.7 3.4 4.1 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 4.8 5.5 12-Bit Low-Power, 2-Wire, Serial Voltage-Output DAC DAC OUTPUT VOLTAGE vs. OUTPUT SOURCE CURRENT (NOTE 6) -0.8 -0.4 DAC OUTPUT VOLTAGE (V) -1.2 4 3 2 0 -15 10 35 60 1.0 0 0 85 2 4 6 8 10 0 2 4 6 8 OUTPUT SOURCE CURRENT (mA) OUTPUT SINK CURRENT (mA) SUPPLY CURRENT vs. INPUT CODE SUPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT vs. SUPPLY VOLTAGE 60 40 90 85 20 0 1638 2457 3276 4096 70 CODE = FFF hex NO LOAD 50 80 819 80 60 NO LOAD CODE = FFF hex NO LOAD MAX5812 toc15 90 SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) 80 95 -40 -15 10 35 INPUT CODE TEMPERATURE (°C) POWER-DOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE POWER-UP GLITCH 60 85 2.7 3.4 MAX5812 toc16 400 4.8 5.5 EXITING SHUTDOWN MAX5812 toc18 5V VDD TA = -40°C 300 4.1 SUPPLY VOLTAGE (V) MAX5812 toc17 500 10 100 MAX5812 toc14 100 MAX5812 toc13 100 POWER-DOWN SUPPLY CURRENT (nA) CODE = 400 hex TEMPERATURE (°C) 120 0 1.5 CODE = FFF hex 0 -40 2.0 0.5 1 NO LOAD SUPPLY CURRENT (µA) 2.5 MAX5812 toc11 5 DAC OUTPUT VOLTAGE (V) -1.6 GAIN ERROR (%FSR) 6 MAX5812 toc10 -2.0 DAC OUTPUT VOLTAGE vs. OUTPUT SINK CURRENT (NOTE 6) MAX5812 toc12 GAIN ERROR vs. TEMPERATURE TA = +25°C 0 OUT 500mV/div 200 10mV/div OUT TA = +85°C 100 ZOUT = HIGH IMPEDANCE NO LOAD 0 2.7 3.4 MAX5812 Typical Operating Characteristics (continued) (VDD = +5V, RL = 5kΩ, TA = +25°C.) 4.1 4.8 5.5 SUPPLY VOLTAGE (V) 100µs/div CLOAD = 200pF 2µs/div CODE = 800 hex Note 6: The ability to drive loads less than 5kΩ is not implied. _______________________________________________________________________________________ 5 MAX5812 12-Bit Low-Power, 2-Wire, Serial Voltage-Output DAC Typical Operating Characteristics (continued) (VDD = +5V, RL = 5kΩ, TA = +25°C.) MAJOR CARRY TRANSITION (NEGATIVE) MAJOR CARRY TRANSITION (POSITIVE) MAX5812 toc20 MAX5812 toc19 OUT 5mV/div CLOAD = 200pF RL = 5kΩ SETTLING TIME (POSITIVE) 2µs/div CODE = 7FF hex TO 800 hex OUT MAX5812 toc21 5mV/div OUT CLOAD = 200pF RL = 5kΩ 2µs/div CODE = 7FF hex TO 800 hex SETTLING TIME (NEGATIVE) 2µs/div CODE = 400 hex to C00 hex MAX5812 toc23 SCL 2V/div OUT 2mV/div 500mV/div CLOAD = 200pF 6 CLOAD = 200pF DIGITAL FEEDTHROUGH MAX5812 toc22 OUT 500mV/div 2µs/div CODE = C00 hex to 400 hex CLOAD = 200pF fSCL = 12kHz 40µs/div CODE = 000 hex _______________________________________________________________________________________ 12-Bit Low-Power, 2-Wire, Serial Voltage-Output DAC PIN NAME 1 VDD Power Supply and DAC Reference Input FUNCTION 2 GND Ground 3 SDA Bidirectional Serial Data I/O 4 SCL Serial Clock Line 5 ADD Address Select. A logic high sets the address LSB to 1; a logic low sets the address LSB to 0. 6 OUT Analog Output Detailed Description The MAX5812 is a 12-bit, voltage-output DAC with an I2C/SMBus-compatible 2-wire interface. The device consists of a serial interface, power-down circuitry, input and DAC registers, a 12-bit resistor string DAC, unitygain output buffer, and output resistor network. The serial interface decodes the address and control bits, routing the data to either the input or DAC register. Data can be directly written to the DAC register immediately updating the device output, or can be written to the input register without changing the DAC output. Both registers retain data as long as the device is powered. DAC Operation The MAX5812 uses a segmented resistor string DAC architecture, which saves power in the overall system and guarantees output monotonicity. The MAX5812’s input coding is straight binary with the output voltage given by the following equation: × (D) V VOUT = REFN 2 where N = 12(bits), and D = the decimal value of the input code (0 to 4095). Output Buffer The MAX5812 analog output is buffered by a precision unity-gain follower that slews 0.5V/µs. The buffer output swings rail-to-rail and is capable of driving 5kΩ in parallel with 200pF. The output settles to ±0.5LSB within 4µs. Power-On Reset The MAX5812 features an internal power-on-reset (POR) circuit that initializes the device upon power-up. The DAC registers are set to zero-scale and the device is powered down with the output buffer disabled and the output pulled to GND through the 100kΩ termination resistor. Following power-up, a wake-up command must be initiated before conversions are performed. Power-Down Modes The MAX5812 has three software-controlled, lowpower, power-down modes. All three modes disable the output buffer and disconnect the DAC resistor string from V DD , reducing supply current draw to 300nA. In power-down mode 0, the device output is high impedance. In power-down mode 1, the device output is internally pulled to GND by a 1kΩ termination resistor. In power-down mode 2, the device output is internally pulled to GND by a 100kΩ termination resistor. Table 1 shows the power-down mode command words. Upon wake-up, the DAC output is restored to its previous value. Data is retained in the input and DAC registers during power-down mode. Digital Interface The MAX5812 features an I 2 C/SMBus-compatible 2-wire interface consisting of a serial data line (SDA) Table 1. Power-Down Command Bits POWER-DOWN COMMAND BITS MODE/FUNCTION PD1 PD0 0 0 Power-up device. DAC output restored to previous value. 0 1 Power-down mode 0. Powers down device with output floating. 1 0 Power-down mode 1. Powers down device with output terminated with 1kΩ to GND. 1 1 Power-down mode 2. Powers down device with output terminated with 100kΩ to GND. _______________________________________________________________________________________ 7 MAX5812 Pin Description MAX5812 12-Bit Low-Power, 2-Wire, Serial Voltage-Output DAC SDA tSU, STA tSU, DAT tLOW tBUF tHD, STA tSP tSU, STO tHD, DAT SCL tHIGH tHD, STA tR tF START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION Figure 1. Two-Wire Serial lnterface Timing Diagram and a serial clock line (SCL). The MAX5812 is SMBus compatible within the range of VDD = 2.7V to 3.6V. SDA and SCL facilitate bidirectional communication between the MAX5812 and the master at rates up to 400kHz. Figure 1 shows the 2-wire interface timing diagram. The MAX5812 is a transmit/receive slave-only device, relying upon a master to generate a clock signal. The master, typically a microcontroller, initiates data transfer on the bus and generates SCL to permit that transfer. A master device communicates to the MAX5812 by transmitting the proper address followed by command and/or data words. Each transmit sequence is framed by a START (S) or REPEATED START (Sr) condition and a STOP (P) condition. Each word transmitted over the bus is 8 bits long and is always followed by an acknowledge clock pulse. The MAX5812 SDA and SCL drivers are open-drain outputs, requiring a pullup resistor (500Ω or greater) to generate a logic high voltage (see the Typical Operating Circuit). Series resistors RS are optional. These series resistors protect the input stages of the MAX5812 from high-voltage spikes on the bus lines and minimize crosstalk and undershoot of the bus signals. Bit Transfer One data bit is transferred during each SCL clock cycle. The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while the SCL is high are control signals (see the START and STOP Conditions section). SDA and SCL idle high when the I2C bus is not busy. S Sr SCL SDA Figure 2. START/STOP Conditions SCL SDA STOP START LEGAL STOP CONDITION SCL SDA START ILLEGAL STOP ILLEGAL EARLY STOP CONDITION Figure 3. Early STOP condition START and STOP Conditions When the serial interface is inactive, SDA and SCL idle high. A master device initiates communication by issuing a START condition. A START condition is a high-to8 _______________________________________________________________________________________ P 12-Bit Low-Power, 2-Wire, Serial Voltage-Output DAC Early STOP Conditions The MAX5812 recognizes a STOP condition at any point during transmission except when a STOP condition occurs in the same high pulse as a START condition (Figure 3). This condition is not a legal I2C format, at least one clock pulse must separate any START and STOP conditions. Repeated START Conditions A repeated start (Sr) condition might indicate a change of data direction on the bus. Such a change occurs when a command word is required to initiate a read operation. Sr also can be used when the bus master is writing to several I2C devices and does not want to relinquish control of the bus. The MAX5812 serial interface supports continuous write operations with or without an Sr condition separating them. Continuous read operations require Sr conditions because of the change in direction of data flow. Acknowledge Bit (ACK) The acknowledge bit (ACK) is the ninth bit attached to any 8-bit data word. ACK is always generated by the receiving device. The MAX5812 generates an ACK when receiving an address or data by pulling SDA low during the ninth clock period. When transmitting data, the MAX5812 waits for the receiving device to generate an ACK. Monitoring ACK allows detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time. Slave Address A bus master initiates communication with a slave device by issuing a START condition followed by the 7-bit slave address (Figure 4). When idle, the MAX5812 waits for a START condition followed by its slave address. The serial interface compares each address MAX5812 low transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA while SCL is high (Figure 2). A START condition from the master signals the beginning of a transmission to the MAX5812. The master terminates transmission by issuing a not acknowledge followed by a STOP condition (see the Acknowledge Bit section). The STOP condition frees the bus. If a repeated START condition (Sr) is generated instead of a STOP condition, the bus remains active. When a STOP condition or incorrect address is detected, the MAX5812 internally disconnects SCL from the serial interface until the next START condition, minimizing digital noise and feedthrough. Table 2. MAX5812 I2C Slave Addresses DEVICE ADDRESS (A6...A0) PART VADD MAX5812L GND 0010 000 MAX5812L VDD 0010 001 MAX5812M GND 0010 010 MAX5812M VDD 0010 011 MAX5812N GND 0110 100 MAX5812N VDD 0110 101 MAX5812P GND 1010 100 MAX5812P VDD 1010 101 S A6 A5 A4 A3 A2 A1 A0 R/W Figure 4. Slave Address Byte Definition C3 C2 C1 C0 D11 D10 D9 D8 Figure 5. Command Byte Definition value bit-by-bit, allowing the interface to power-down immediately when an incorrect address is detected. The LSB of the address word is the Read/Write (R/W) bit. R/W indicates whether the master is writing to or reading from the MAX5812 (R/W = 0 selects the write condition, R/W = 1 selects the read condition). After receiving the proper address, the MAX5812 issues an ACK by pulling SDA low for one clock cycle. The MAX5812 has eight factory/user-programmed addresses (Table 2). Address bits A6 through A1 are preset; A0 is controlled by ADD. Connecting ADD to GND sets A0 = 0. Connecting ADD to VDD sets A0 = 1. This feature allows up to eight MAX5812s to share a bus. Write Data Format In write mode (R/W = 0), data that follows the address byte controls the MAX5812 (Figure 5). Bits C3–C0 configure the MAX5812 (Table 3). Bits D11–D0 are DAC data. Input and DAC registers update on the falling edge of SCL during the acknowledge bit. Should the write cycle be prematurely aborted, data will not be updated and the write cycle must be repeated. Figure 6 shows two example write data sequences. _______________________________________________________________________________________ 9 MAX5812 12-Bit Low-Power, 2-Wire, Serial Voltage-Output DAC Table 3. Command Byte Definitions SERIAL DATA INPUT C3 C2 C1 FUNCTION C0 D11/PD1* D10/PD0* D9–D8 DAC DATA DAC DATA Load DAC with a new data from the following data byte and update DAC output simultaneously as soon as data is available from the serial bus. The DAC and input registers are updated with the new data. 1 1 0 0 DAC DATA 1 1 0 1 DAC DATA DAC DATA DAC DATA Load input register with the data from the following data byte. DAC output remains unchanged. 1 1 1 0 DAC DATA DAC DATA DAC DATA Load input register with data from the following data byte. Update DAC output to the previously stored data. 1 1 1 1 X X XX Update DAC output from input register. The device will ignore any new data. 1 0 X X X X XX Read data request. Data bits are ignored. The contents of the DAC register are available on the bus. 0 1 X X 0 0 XX Powers up device. 0 1 X X 0 1 XX Power-down mode 0. Powers down device with output floating. 0 1 X X 1 0 XX Power-down mode 1. Powers down device with output terminated with 1kΩ to GND. 0 1 X X 1 1 XX Power-down mode 2. Powers down device with output terminated with 100kΩ to GND. *When C3 = 0 and C2 = 1, data bits D11 and D10 write to the power-down registers (PD1 and PD0). X = Don’t care. MSB S LSB A6 A5 A4 A3 A2 A1 A0 R/W MSB D7 MSB ACK C3 LSB C2 C1 C0 D11 D10 D9 D8 ACK LSB D6 D5 D4 D3 D2 D1 D0 ACK P EXAMPLE WRITE DATA SEQUENCE MSB S LSB A6 A5 A4 A3 A2 A1 A0 R/W MSB ACK C3 LSB C2 X X PD1 PD0 X X EXAMPLE WRITE TO POWER-DOWN REGISTER SEQUENCE Figure 6. Example Write Command Sequences 10 ______________________________________________________________________________________ ACK P 12-Bit Low-Power, 2-Wire, Serial Voltage-Output DAC LSB A6 R/W =0 A4 A5 A3 A2 A1 A0 MSB ACK MAX5812 S MSB LSB C3 C2 X X X X X X ACK DATA BYTES GENERATED BY MASTER DEVICE Sr MSB LSB A6 R/W =1 A4 A5 A3 A2 A1 A0 MSB ACK X X PD1 PD0 D11 D10 D9 D8 ACK ACK GENERATED BY MASTER DEVICE DATA BYTES GENERATED BY MAX5812 MSB LSB LSB D7 D6 D5 D4 D3 D2 D1 D0 ACK P Figure 7. Example Read Word Data Sequence IN patible only with the 7-bit I2C addressing protocol. Tenbit address formats are not supported. OUT VDD MAX6030/ MAX6050 GND MAX5812 Digital Feedthrough Suppression OUT GND Figure 8. Powering the MAX5812 from An External Reference Read Data Format In read mode (R/W = 1), the MAX5812 writes the contents of the DAC register to the bus. The direction of data flow reverses after the address acknowledge by the MAX5812. The device transmits the first byte of data, waits for the master to acknowledge, and then transmits the second byte. Figure 7 shows an exampleread data sequence. I 2C Compatibility The MAX5812 is compatible with existing I2C systems. SCL and SDA are high-impedance inputs; SDA has an open drain that pulls the data line low during the ninth clock pulse. The Typical Operating Circuit shows a typical I2C application. The communication protocol supports standard I2C 8-bit communications. The general call address is ignored. The MAX5812 address is com- When the MAX5812 detects an address mismatch, the serial interface disconnects the SCL signal from the core circuitry. This minimizes digital feedthrough caused by the SCL signal on a static output. The serial interface reconnects the SCL signal when a valid START condition is detected. Applications Information Powering the Device From an External Reference The MAX5812 uses the VDD as the DAC voltage reference. Any power-supply noise is directly coupled to the device output. The circuit in Figure 8 uses a precision voltage reference to power the MAX5812, isolating the device from any power-supply noise. Powering the MAX5812 in such a manner greatly improves overall performance, especially in noisy systems. The MAX6030 (3V, 75ppm/°C) or the MAX6050 (5V, 75ppm/°C) precision voltage references are ideal choices because of the low power requirements of the MAX5812. Digital Inputs and Interface Logic The MAX5812 2-wire digital interface is I2C and SMBuscompatible. The two digital inputs (SCL and SDA) load ______________________________________________________________________________________ 11 12-Bit Low-Power, 2-Wire, Serial Voltage-Output DAC MAX5812 Functional Diagram VDD INPUT REGISTER MUX AND DAC REGISTER 12-BIT DAC OUT RESISTOR NETWORK SERIAL INTERFACE SDA ADD POWER-DOWN CIRCUITRY SCL MAX5812 GND the digital input serially into the DAC. Schmitt-trigger buffered inputs allow slow transition interfaces such as optocouplers to interface directly to the device. The digital inputs are compatible with CMOS logic levels. Chip Information TRANSISTOR COUNT: 7172 PROCESS: BiCMOS Power-Supply Bypassing and Ground Management Careful PC board layout is important for optimal system performance. Keep analog and digital signals separate to reduce noise injection and digital feedthrough. Use a ground plane to ensure that the ground return from GND to the power supply ground is short and low impedance. Bypass V DD with a 0.1µF capacitor to ground as close to the device as possible. Selector Guide 12 PART ADDRESS MAX5812LEUT 0010 00X MAX5812MEUT 0010 01X MAX5812NEUT 0110 10X MAX5812PEUT 1010 10X ______________________________________________________________________________________ 12-Bit Low-Power, 2-Wire, Serial Voltage-Output DAC Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX5812 Package Information